1 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
2 ; RUN: < %s | FileCheck %s
3 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
4 ; RUN: < %s | FileCheck %s
5 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
6 ; RUN: < %s | FileCheck %s -check-prefix=mips32r2
7 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
8 ; RUN: < %s | FileCheck %s -check-prefix=mips32
9 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32r2 \
10 ; RUN: < %s | FileCheck %s -check-prefix=CHECK2
11 ; RUN: llc -march=mipsel -relocation-model=pic -O0 -mips-fast-isel -fast-isel-abort -mcpu=mips32 \
12 ; RUN: < %s | FileCheck %s -check-prefix=CHECK2
15 @c1 = global i8 -45, align 1
16 @uc1 = global i8 27, align 1
17 @s1 = global i16 -1789, align 2
18 @us1 = global i16 1256, align 2
20 ; Function Attrs: nounwind
21 define void @cxi() #0 {
25 ; CHECK-DAG: addiu $4, $zero, 10
26 ; CHECK-DAG: lw $25, %got(xi)(${{[0-9]+}})
32 declare void @xi(i32) #1
34 ; Function Attrs: nounwind
35 define void @cxii() #0 {
38 call void @xii(i32 746, i32 892)
39 ; CHECK-DAG: addiu $4, $zero, 746
40 ; CHECK-DAG: addiu $5, $zero, 892
41 ; CHECK-DAG: lw $25, %got(xii)(${{[0-9]+}})
47 declare void @xii(i32, i32) #1
49 ; Function Attrs: nounwind
50 define void @cxiii() #0 {
53 call void @xiii(i32 88, i32 44, i32 11)
54 ; CHECK-DAG: addiu $4, $zero, 88
55 ; CHECK-DAG: addiu $5, $zero, 44
56 ; CHECK-DAG: addiu $6, $zero, 11
57 ; CHECK-DAG: lw $25, %got(xiii)(${{[0-9]+}})
62 declare void @xiii(i32, i32, i32) #1
64 ; Function Attrs: nounwind
65 define void @cxiiii() #0 {
68 call void @xiiii(i32 167, i32 320, i32 97, i32 14)
69 ; CHECK-DAG: addiu $4, $zero, 167
70 ; CHECK-DAG: addiu $5, $zero, 320
71 ; CHECK-DAG: addiu $6, $zero, 97
72 ; CHECK-DAG: addiu $7, $zero, 14
73 ; CHECK-DAG: lw $25, %got(xiiii)(${{[0-9]+}})
79 declare void @xiiii(i32, i32, i32, i32) #1
81 ; Function Attrs: nounwind
82 define void @cxiiiiconv() #0 {
84 ; CHECK-LABEL: cxiiiiconv
85 ; mips32r2-LABEL: cxiiiiconv
86 ; mips32-LABEL: cxiiiiconv
87 %0 = load i8* @c1, align 1
88 %conv = sext i8 %0 to i32
89 %1 = load i8* @uc1, align 1
90 %conv1 = zext i8 %1 to i32
91 %2 = load i16* @s1, align 2
92 %conv2 = sext i16 %2 to i32
93 %3 = load i16* @us1, align 2
94 %conv3 = zext i16 %3 to i32
95 call void @xiiii(i32 %conv, i32 %conv1, i32 %conv2, i32 %conv3)
96 ; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
97 ; mips32r2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
98 ; mips32: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
99 ; mips32r2-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]])
100 ; mips32r2-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]])
101 ; mips32r2-DAG seb $3, $[[REG_C1]]
102 ; mips32-DAG: lw $[[REG_C1_ADDR:[0-9]+]], %got(c1)($[[REG_GP]])
103 ; mips32-DAG: lbu $[[REG_C1:[0-9]+]], 0($[[REG_C1_ADDR]])
104 ; mips32-DAG: sll $[[REG_C1_1:[0-9]+]], $[[REG_C1]], 24
105 ; mips32-DAG: sra $4, $[[REG_C1_1]], 24
106 ; CHECK-DAG: lw $[[REG_UC1_ADDR:[0-9]+]], %got(uc1)($[[REG_GP]])
107 ; CHECK-DAG: lbu $[[REG_UC1:[0-9]+]], 0($[[REG_UC1_ADDR]])
108 ; FIXME andi is superfulous
109 ; CHECK-DAG: andi $5, $[[REG_UC1]], 255
110 ; mips32r2-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
111 ; mips32r2-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])
112 ; mips32r2-DAG: seh $6, $[[REG_S1]]
113 ; mips32-DAG: lw $[[REG_S1_ADDR:[0-9]+]], %got(s1)($[[REG_GP]])
114 ; mips32-DAG: lhu $[[REG_S1:[0-9]+]], 0($[[REG_S1_ADDR]])
115 ; mips32-DAG: sll $[[REG_S1_1:[0-9]+]], $[[REG_S1]], 16
116 ; mips32-DAG: sra $6, $[[REG_S1_1]], 16
117 ; CHECK-DAG: lw $[[REG_US1_ADDR:[0-9]+]], %got(us1)($[[REG_GP]])
118 ; CHECK-DAG: lhu $[[REG_US1:[0-9]+]], 0($[[REG_US1_ADDR]])
119 ; FIXME andi is superfulous
120 ; CHECK-DAG: andi $7, $[[REG_US1]], 65535
127 ; Function Attrs: nounwind
128 define void @cxf() #0 {
131 call void @xf(float 0x40BBC85560000000)
132 ; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
133 ; CHECK: lui $[[REG_FPCONST_1:[0-9]+]], 17886
134 ; CHECK: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 17067
135 ; CHECK: mtc1 $[[REG_FPCONST]], $f12
136 ; CHECK: lw $25, %got(xf)($[[REG_GP]])
141 declare void @xf(float) #1
143 ; Function Attrs: nounwind
144 define void @cxff() #0 {
147 call void @xff(float 0x3FF74A6CA0000000, float 0x401A2C0840000000)
148 ; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
149 ; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16314
150 ; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 21349
151 ; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12
152 ; CHECK-DAG: lui $[[REG_FPCONST_2:[0-9]+]], 16593
153 ; CHECK-DAG: ori $[[REG_FPCONST_3:[0-9]+]], $[[REG_FPCONST_2]], 24642
154 ; CHECK-DAG: mtc1 $[[REG_FPCONST_3]], $f14
155 ; CHECK: lw $25, %got(xff)($[[REG_GP]])
160 declare void @xff(float, float) #1
162 ; Function Attrs: nounwind
163 define void @cxfi() #0 {
166 call void @xfi(float 0x4013906240000000, i32 102)
167 ; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
168 ; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16540
169 ; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 33554
170 ; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12
171 ; CHECK-DAG: addiu $5, $zero, 102
172 ; CHECK: lw $25, %got(xfi)($[[REG_GP]])
178 declare void @xfi(float, i32) #1
180 ; Function Attrs: nounwind
181 define void @cxfii() #0 {
184 call void @xfii(float 0x405EC7EE00000000, i32 9993, i32 10922)
185 ; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
186 ; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17142
187 ; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 16240
188 ; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12
189 ; CHECK-DAG: addiu $5, $zero, 9993
190 ; CHECK-DAG: addiu $6, $zero, 10922
191 ; CHECK: lw $25, %got(xfii)($[[REG_GP]])
196 declare void @xfii(float, i32, i32) #1
198 ; Function Attrs: nounwind
199 define void @cxfiii() #0 {
201 ; CHECK-LABEL: cxfiii
202 call void @xfiii(float 0x405C072B20000000, i32 3948, i32 89011, i32 111222)
203 ; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
204 ; CHECK-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 17120
205 ; CHECK-DAG: ori $[[REG_FPCONST:[0-9]+]], $[[REG_FPCONST_1]], 14681
206 ; CHECK-DAG: mtc1 $[[REG_FPCONST]], $f12
207 ; CHECK-DAG: addiu $5, $zero, 3948
208 ; CHECK-DAG: lui $[[REG_I_1:[0-9]+]], 1
209 ; CHECK-DAG: ori $6, $[[REG_I_1]], 23475
210 ; CHECK-DAG: lui $[[REG_I_2:[0-9]+]], 1
211 ; CHECK-DAG: ori $7, $[[REG_I_2]], 45686
212 ; CHECK: lw $25, %got(xfiii)($[[REG_GP]])
217 declare void @xfiii(float, i32, i32, i32) #1
219 ; Function Attrs: nounwind
220 define void @cxd() #0 {
222 ; mips32r2-LABEL: cxd:
224 call void @xd(double 5.994560e+02)
225 ; mips32: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
226 ; mips32-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16514
227 ; mips32-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037
228 ; mips32-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 58195
229 ; mips32-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439
230 ; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f12
231 ; mips32-DAG: mtc1 $[[REG_FPCONST_2]], $f13
232 ; mips32-DAG: lw $25, %got(xd)($[[REG_GP]])
234 ; mips32r2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
235 ; mips32r2-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16514
236 ; mips32r2-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 48037
237 ; mips32r2-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 58195
238 ; mips32r2-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 63439
239 ; mips32r2-DAG: mtc1 $[[REG_FPCONST_4]], $f12
240 ; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f12
241 ; mips32r2-DAG: lw $25, %got(xd)($[[REG_GP]])
242 ; mips32r2 : jalr $25
246 declare void @xd(double) #1
248 ; Function Attrs: nounwind
249 define void @cxdd() #0 {
250 ; mips32r2-LABEL: cxdd:
251 ; mips32-LABEL: cxdd:
253 call void @xdd(double 1.234980e+03, double 0x40F5B331F7CED917)
254 ; mips32: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
255 ; mips32-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16531
256 ; mips32-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435
257 ; mips32-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 34078
258 ; mips32-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186
259 ; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f12
260 ; mips32-DAG: mtc1 $[[REG_FPCONST_2]], $f13
261 ; mips32-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16629
262 ; mips32-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873
263 ; mips32-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 63438
264 ; mips32-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575
265 ; mips32-DAG: mtc1 $[[REG_FPCONST_4]], $f14
266 ; mips32-DAG: mtc1 $[[REG_FPCONST_2]], $f15
267 ; mips32-DAG: lw $25, %got(xdd)($[[REG_GP]])
269 ; mips32r2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
270 ; mips32r2-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16531
271 ; mips32r2-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 19435
272 ; mips32r2-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 34078
273 ; mips32r2-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 47186
274 ; mips32r2-DAG: mtc1 $[[REG_FPCONST_4]], $f12
275 ; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f12
276 ; mips32r2-DAG: lui $[[REG_FPCONST_1:[0-9]+]], 16629
277 ; mips32r2-DAG: ori $[[REG_FPCONST_2:[0-9]+]], $[[REG_FPCONST_1]], 45873
278 ; mips32r2-DAG: lui $[[REG_FPCONST_3:[0-9]+]], 63438
279 ; mips32r2-DAG: ori $[[REG_FPCONST_4:[0-9]+]], $[[REG_FPCONST_3]], 55575
280 ; mips32r2-DAG: mtc1 $[[REG_FPCONST_4]], $f14
281 ; mips32r2-DAG: mthc1 $[[REG_FPCONST_2]], $f14
282 ; mips32r2-DAG: lw $25, %got(xdd)($[[REG_GP]])
283 ; mips32r2 : jalr $25
287 declare void @xdd(double, double) #1
289 ; Function Attrs: nounwind
290 define void @cxif() #0 {
293 call void @xif(i32 345, float 0x407BCE5A20000000)
294 ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
295 ; CHECK-DAG: addiu $4, $zero, 345
296 ; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 17374
297 ; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 29393
298 ; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
299 ; CHECK-DAG: mfc1 $5, $f[[REGF_3]]
300 ; CHECK-DAG: lw $25, %got(xif)($[[REG_GP]])
306 declare void @xif(i32, float) #1
308 ; Function Attrs: nounwind
309 define void @cxiff() #0 {
311 ; CHECK-LABEL: cxiff:
312 ; CHECK2-LABEL: cxiff:
313 call void @xiff(i32 12239, float 0x408EDB3340000000, float 0x4013FFE5C0000000)
314 ; We need to do the two floating point parameters in a separate
315 ; check because we can't control the ordering of parts of the sequence
317 ; CHECK: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
318 ; CHECK: addiu $4, $zero, 12239
319 ; CHECK2: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
320 ; CHECK2: addiu $4, $zero, 12239
321 ; CHECK: lui $[[REGF_1:[0-9]+]], 17526
322 ; CHECK: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706
323 ; CHECK: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
324 ; CHECK: mfc1 $5, $f[[REGF_3]]
325 ; CHECK2: lui $[[REGF2_1:[0-9]+]], 16543
326 ; CHECK2: ori $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 65326
327 ; CHECK2: mtc1 $[[REGF2_2]], $f[[REGF2_3:[0-9]+]]
328 ; CHECK2: mfc1 $6, $f[[REGF2_3]]
329 ; CHECK: lw $25, %got(xiff)($[[REG_GP]])
330 ; CHECK2: lw $25, %got(xiff)($[[REG_GP]])
336 declare void @xiff(i32, float, float) #1
338 ; Function Attrs: nounwind
339 define void @cxifi() #0 {
342 call void @xifi(i32 887, float 0x402277CEE0000000, i32 888)
343 ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
344 ; CHECK-DAG: addiu $4, $zero, 887
345 ; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 16659
346 ; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 48759
347 ; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
348 ; CHECK-DAG: mfc1 $5, $f[[REGF_3]]
349 ; CHECk-DAG: addiu $6, $zero, 888
350 ; CHECK-DAG: lw $25, %got(xifi)($[[REG_GP]])
356 declare void @xifi(i32, float, i32) #1
358 ; Function Attrs: nounwind
359 define void @cxifif() #0 {
363 call void @xifif(i32 67774, float 0x408EE0FBE0000000, i32 9991, float 0x40B15C8CC0000000)
364 ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
365 ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
366 ; CHECK-DAG: lui $[[REGI:[0-9]+]], 1
367 ; CHECK-DAG: ori $4, $[[REGI]], 2238
368 ; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 17527
369 ; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 2015
370 ; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
371 ; CHECK-DAG: mfc1 $5, $f[[REGF_3]]
372 ; CHECk-DAG: addiu $6, $zero, 888
373 ; CHECK2: lui $[[REGF2_1:[0-9]+]], 17802
374 ; CHECK2: ori $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 58470
375 ; CHECK2: mtc1 $[[REGF2_2]], $f[[REGF2_3:[0-9]+]]
376 ; CHECK2: mfc1 $7, $f[[REGF2_3]]
377 ; CHECK: lw $25, %got(xifif)($[[REG_GP]])
378 ; CHECK2: lw $25, %got(xifif)($[[REG_GP]])
385 declare void @xifif(i32, float, i32, float) #1
387 ; Function Attrs: nounwind
388 define void @cxiffi() #0 {
390 ; CHECK-label: cxiffi:
391 ; CHECK2-label: cxiffi:
392 call void @xiffi(i32 45, float 0x3FF6666660000000, float 0x408F333340000000, i32 234)
393 ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
394 ; CHECK-DAG: addiu $4, $zero, 45
395 ; CHECK2-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
396 ; CHECK2-DAG: addiu $4, $zero, 45
397 ; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 16307
398 ; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 13107
399 ; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
400 ; CHECK-DAG: mfc1 $5, $f[[REGF_3]]
401 ; CHECK2: lui $[[REGF2_1:[0-9]+]], 17529
402 ; CHECK2: ori $[[REGF2_2:[0-9]+]], $[[REGF2_1]], 39322
403 ; CHECK2: mtc1 $[[REGF2_2]], $f[[REGF2_3:[0-9]+]]
404 ; CHECK2: mfc1 $6, $f[[REGF2_3]]
405 ; CHECK-DAG: lw $25, %got(xiffi)($[[REG_GP]])
406 ; CHECK-DAG: addiu $7, $zero, 234
407 ; CHECK2-DAG: lw $25, %got(xiffi)($[[REG_GP]])
414 declare void @xiffi(i32, float, float, i32) #1
416 ; Function Attrs: nounwind
417 define void @cxifii() #0 {
420 call void @xifii(i32 12239, float 0x408EDB3340000000, i32 998877, i32 1234)
421 ; CHECK-DAG: addu $[[REG_GP:[0-9]+]], ${{[0-9]+}}, ${{[0-9+]}}
422 ; CHECK-DAG: addiu $4, $zero, 12239
423 ; CHECK-DAG: lui $[[REGF_1:[0-9]+]], 17526
424 ; CHECK-DAG: ori $[[REGF_2:[0-9]+]], $[[REGF_1]], 55706
425 ; CHECK-DAG: mtc1 $[[REGF_2]], $f[[REGF_3:[0-9]+]]
426 ; CHECK-DAG: mfc1 $5, $f[[REGF_3]]
427 ; CHECK-DAG: lui $[[REGI2:[0-9]+]], 15
428 ; CHECK-DAG: ori $6, $[[REGI2]], 15837
429 ; CHECk-DAG: addiu $7, $zero, 1234
430 ; CHECK-DAG: lw $25, %got(xifii)($[[REG_GP]])
435 declare void @xifii(i32, float, i32, i32) #1
437 ; FIXME: this function will not pass yet.
438 ; Function Attrs: nounwind
439 ; define void @cxfid() #0 {
441 ; call void @xfid(float 0x4013B851E0000000, i32 811123, double 0x40934BFF487FCB92)
445 declare void @xfid(float, i32, double) #1
447 ; Function Attrs: nounwind
448 define void @g() #0 {
454 call void @cxiiiiconv()
472 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
473 attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
477 !0 = metadata !{metadata !"clang version 3.6.0 (gitosis@dmz-portal.mips.com:clang 43992fe7b17de5553ac06d323cb80cc6723a9ae3) (gitosis@dmz-portal.mips.com:llvm.git 0834e6839eb170197c81bb02e916258d1527e312)"}