1 ; RUN: llc -march=hexagon -mcpu=hexagonv5 < %s | FileCheck %s
3 ; Verify that the mpy intrinsics with accumulation are lowered into
4 ; the right instructions. These instructions have a 64-bit destination register.
6 @c = external global i64
8 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l)
10 define void @test1(i32 %a1, i32 %b1) #0 {
12 %0 = load i64* @c, align 8
13 %1 = tail call i64 @llvm.hexagon.M2.mpyd.acc.ll.s0(i64 %0, i32 %a1, i32 %b1)
14 store i64 %1, i64* @c, align 8
18 declare i64 @llvm.hexagon.M2.mpyd.acc.ll.s0(i64, i32, i32) #1
20 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h)
22 define void @test2(i32 %a2, i32 %b2) #0 {
24 %0 = load i64* @c, align 8
25 %1 = tail call i64 @llvm.hexagon.M2.mpyd.acc.lh.s0(i64 %0, i32 %a2, i32 %b2)
26 store i64 %1, i64* @c, align 8
30 declare i64 @llvm.hexagon.M2.mpyd.acc.lh.s0(i64, i32, i32) #1
32 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l)
34 define void @test3(i32 %a3, i32 %b3) #0 {
36 %0 = load i64* @c, align 8
37 %1 = tail call i64 @llvm.hexagon.M2.mpyd.acc.hl.s0(i64 %0, i32 %a3, i32 %b3)
38 store i64 %1, i64* @c, align 8
42 declare i64 @llvm.hexagon.M2.mpyd.acc.hl.s0(i64, i32, i32) #1
44 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h)
46 define void @test4(i32 %a4, i32 %b4) #0 {
48 %0 = load i64* @c, align 8
49 %1 = tail call i64 @llvm.hexagon.M2.mpyd.acc.hh.s0(i64 %0, i32 %a4, i32 %b4)
50 store i64 %1, i64* @c, align 8
54 declare i64 @llvm.hexagon.M2.mpyd.acc.hh.s0(i64, i32, i32) #1
56 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}-={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l)
58 define void @test5(i32 %a5, i32 %b5) #0 {
60 %0 = load i64* @c, align 8
61 %1 = tail call i64 @llvm.hexagon.M2.mpyd.nac.ll.s0(i64 %0, i32 %a5, i32 %b5)
62 store i64 %1, i64* @c, align 8
66 declare i64 @llvm.hexagon.M2.mpyd.nac.ll.s0(i64, i32, i32) #1
68 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}-={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h)
70 define void @test6(i32 %a6, i32 %b6) #0 {
72 %0 = load i64* @c, align 8
73 %1 = tail call i64 @llvm.hexagon.M2.mpyd.nac.lh.s0(i64 %0, i32 %a6, i32 %b6)
74 store i64 %1, i64* @c, align 8
78 declare i64 @llvm.hexagon.M2.mpyd.nac.lh.s0(i64, i32, i32) #1
80 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}-={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l)
82 define void @test7(i32 %a7, i32 %b7) #0 {
84 %0 = load i64* @c, align 8
85 %1 = tail call i64 @llvm.hexagon.M2.mpyd.nac.hl.s0(i64 %0, i32 %a7, i32 %b7)
86 store i64 %1, i64* @c, align 8
90 declare i64 @llvm.hexagon.M2.mpyd.nac.hl.s0(i64, i32, i32) #1
92 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}-={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h)
94 define void @test8(i32 %a8, i32 %b8) #0 {
96 %0 = load i64* @c, align 8
97 %1 = tail call i64 @llvm.hexagon.M2.mpyd.nac.hh.s0(i64 %0, i32 %a8, i32 %b8)
98 store i64 %1, i64* @c, align 8
102 declare i64 @llvm.hexagon.M2.mpyd.nac.hh.s0(i64, i32, i32) #1
104 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l)
106 define void @test9(i32 %a9, i32 %b9) #0 {
108 %0 = load i64* @c, align 8
109 %1 = tail call i64 @llvm.hexagon.M2.mpyud.acc.ll.s0(i64 %0, i32 %a9, i32 %b9)
110 store i64 %1, i64* @c, align 8
114 declare i64 @llvm.hexagon.M2.mpyud.acc.ll.s0(i64, i32, i32) #1
116 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h)
118 define void @test10(i32 %a10, i32 %b10) #0 {
120 %0 = load i64* @c, align 8
121 %1 = tail call i64 @llvm.hexagon.M2.mpyud.acc.lh.s0(i64 %0, i32 %a10, i32 %b10)
122 store i64 %1, i64* @c, align 8
126 declare i64 @llvm.hexagon.M2.mpyud.acc.lh.s0(i64, i32, i32) #1
128 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l)
130 define void @test11(i32 %a11, i32 %b11) #0 {
132 %0 = load i64* @c, align 8
133 %1 = tail call i64 @llvm.hexagon.M2.mpyud.acc.hl.s0(i64 %0, i32 %a11, i32 %b11)
134 store i64 %1, i64* @c, align 8
138 declare i64 @llvm.hexagon.M2.mpyud.acc.hl.s0(i64, i32, i32) #1
140 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h)
142 define void @test12(i32 %a12, i32 %b12) #0 {
144 %0 = load i64* @c, align 8
145 %1 = tail call i64 @llvm.hexagon.M2.mpyud.acc.hh.s0(i64 %0, i32 %a12, i32 %b12)
146 store i64 %1, i64* @c, align 8
150 declare i64 @llvm.hexagon.M2.mpyud.acc.hh.s0(i64, i32, i32) #1
152 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}-={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l)
154 define void @test13(i32 %a13, i32 %b13) #0 {
156 %0 = load i64* @c, align 8
157 %1 = tail call i64 @llvm.hexagon.M2.mpyud.nac.ll.s0(i64 %0, i32 %a13, i32 %b13)
158 store i64 %1, i64* @c, align 8
162 declare i64 @llvm.hexagon.M2.mpyud.nac.ll.s0(i64, i32, i32) #1
164 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}-={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h)
166 define void @test14(i32 %a14, i32 %b14) #0 {
168 %0 = load i64* @c, align 8
169 %1 = tail call i64 @llvm.hexagon.M2.mpyud.nac.lh.s0(i64 %0, i32 %a14, i32 %b14)
170 store i64 %1, i64* @c, align 8
174 declare i64 @llvm.hexagon.M2.mpyud.nac.lh.s0(i64, i32, i32) #1
176 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}-={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l)
178 define void @test15(i32 %a15, i32 %b15) #0 {
180 %0 = load i64* @c, align 8
181 %1 = tail call i64 @llvm.hexagon.M2.mpyud.nac.hl.s0(i64 %0, i32 %a15, i32 %b15)
182 store i64 %1, i64* @c, align 8
186 declare i64 @llvm.hexagon.M2.mpyud.nac.hl.s0(i64, i32, i32) #1
188 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}-={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h)
190 define void @test16(i32 %a16, i32 %b16) #0 {
192 %0 = load i64* @c, align 8
193 %1 = tail call i64 @llvm.hexagon.M2.mpyud.nac.hh.s0(i64 %0, i32 %a16, i32 %b16)
194 store i64 %1, i64* @c, align 8
198 declare i64 @llvm.hexagon.M2.mpyud.nac.hh.s0(i64, i32, i32) #1
200 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1
202 define void @test17(i32 %a17, i32 %b17) #0 {
204 %0 = load i64* @c, align 8
205 %1 = tail call i64 @llvm.hexagon.M2.mpyd.acc.ll.s1(i64 %0, i32 %a17, i32 %b17)
206 store i64 %1, i64* @c, align 8
210 declare i64 @llvm.hexagon.M2.mpyd.acc.ll.s1(i64, i32, i32) #1
212 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1
214 define void @test18(i32 %a18, i32 %b18) #0 {
216 %0 = load i64* @c, align 8
217 %1 = tail call i64 @llvm.hexagon.M2.mpyd.acc.lh.s1(i64 %0, i32 %a18, i32 %b18)
218 store i64 %1, i64* @c, align 8
222 declare i64 @llvm.hexagon.M2.mpyd.acc.lh.s1(i64, i32, i32) #1
224 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1
226 define void @test19(i32 %a19, i32 %b19) #0 {
228 %0 = load i64* @c, align 8
229 %1 = tail call i64 @llvm.hexagon.M2.mpyd.acc.hl.s1(i64 %0, i32 %a19, i32 %b19)
230 store i64 %1, i64* @c, align 8
234 declare i64 @llvm.hexagon.M2.mpyd.acc.hl.s1(i64, i32, i32) #1
236 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1
238 define void @test20(i32 %a20, i32 %b20) #0 {
240 %0 = load i64* @c, align 8
241 %1 = tail call i64 @llvm.hexagon.M2.mpyd.acc.hh.s1(i64 %0, i32 %a20, i32 %b20)
242 store i64 %1, i64* @c, align 8
246 declare i64 @llvm.hexagon.M2.mpyd.acc.hh.s1(i64, i32, i32) #1
248 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}-={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1
250 define void @test21(i32 %a21, i32 %b21) #0 {
252 %0 = load i64* @c, align 8
253 %1 = tail call i64 @llvm.hexagon.M2.mpyd.nac.ll.s1(i64 %0, i32 %a21, i32 %b21)
254 store i64 %1, i64* @c, align 8
258 declare i64 @llvm.hexagon.M2.mpyd.nac.ll.s1(i64, i32, i32) #1
260 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}-={{ *}}mpy(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1
262 define void @test22(i32 %a22, i32 %b22) #0 {
264 %0 = load i64* @c, align 8
265 %1 = tail call i64 @llvm.hexagon.M2.mpyd.nac.lh.s1(i64 %0, i32 %a22, i32 %b22)
266 store i64 %1, i64* @c, align 8
270 declare i64 @llvm.hexagon.M2.mpyd.nac.lh.s1(i64, i32, i32) #1
272 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}-={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1
274 define void @test23(i32 %a23, i32 %b23) #0 {
276 %0 = load i64* @c, align 8
277 %1 = tail call i64 @llvm.hexagon.M2.mpyd.nac.hl.s1(i64 %0, i32 %a23, i32 %b23)
278 store i64 %1, i64* @c, align 8
282 declare i64 @llvm.hexagon.M2.mpyd.nac.hl.s1(i64, i32, i32) #1
284 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}-={{ *}}mpy(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1
286 define void @test24(i32 %a24, i32 %b24) #0 {
288 %0 = load i64* @c, align 8
289 %1 = tail call i64 @llvm.hexagon.M2.mpyd.nac.hh.s1(i64 %0, i32 %a24, i32 %b24)
290 store i64 %1, i64* @c, align 8
294 declare i64 @llvm.hexagon.M2.mpyd.nac.hh.s1(i64, i32, i32) #1
296 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1
298 define void @test25(i32 %a25, i32 %b25) #0 {
300 %0 = load i64* @c, align 8
301 %1 = tail call i64 @llvm.hexagon.M2.mpyud.acc.ll.s1(i64 %0, i32 %a25, i32 %b25)
302 store i64 %1, i64* @c, align 8
306 declare i64 @llvm.hexagon.M2.mpyud.acc.ll.s1(i64, i32, i32) #1
308 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1
310 define void @test26(i32 %a26, i32 %b26) #0 {
312 %0 = load i64* @c, align 8
313 %1 = tail call i64 @llvm.hexagon.M2.mpyud.acc.lh.s1(i64 %0, i32 %a26, i32 %b26)
314 store i64 %1, i64* @c, align 8
318 declare i64 @llvm.hexagon.M2.mpyud.acc.lh.s1(i64, i32, i32) #1
320 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1
322 define void @test27(i32 %a27, i32 %b27) #0 {
324 %0 = load i64* @c, align 8
325 %1 = tail call i64 @llvm.hexagon.M2.mpyud.acc.hl.s1(i64 %0, i32 %a27, i32 %b27)
326 store i64 %1, i64* @c, align 8
330 declare i64 @llvm.hexagon.M2.mpyud.acc.hl.s1(i64, i32, i32) #1
332 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}+={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1
334 define void @test28(i32 %a28, i32 %b28) #0 {
336 %0 = load i64* @c, align 8
337 %1 = tail call i64 @llvm.hexagon.M2.mpyud.acc.hh.s1(i64 %0, i32 %a28, i32 %b28)
338 store i64 %1, i64* @c, align 8
342 declare i64 @llvm.hexagon.M2.mpyud.acc.hh.s1(i64, i32, i32) #1
344 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}-={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.l):<<1
346 define void @test29(i32 %a29, i32 %b29) #0 {
348 %0 = load i64* @c, align 8
349 %1 = tail call i64 @llvm.hexagon.M2.mpyud.nac.ll.s1(i64 %0, i32 %a29, i32 %b29)
350 store i64 %1, i64* @c, align 8
354 declare i64 @llvm.hexagon.M2.mpyud.nac.ll.s1(i64, i32, i32) #1
356 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}-={{ *}}mpyu(r{{[0-9]+}}.l{{ *}},{{ *}}r{{[0-9]+}}.h):<<1
358 define void @test30(i32 %a30, i32 %b30) #0 {
360 %0 = load i64* @c, align 8
361 %1 = tail call i64 @llvm.hexagon.M2.mpyud.nac.lh.s1(i64 %0, i32 %a30, i32 %b30)
362 store i64 %1, i64* @c, align 8
366 declare i64 @llvm.hexagon.M2.mpyud.nac.lh.s1(i64, i32, i32) #1
368 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}-={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.l):<<1
370 define void @test31(i32 %a31, i32 %b31) #0 {
372 %0 = load i64* @c, align 8
373 %1 = tail call i64 @llvm.hexagon.M2.mpyud.nac.hl.s1(i64 %0, i32 %a31, i32 %b31)
374 store i64 %1, i64* @c, align 8
378 declare i64 @llvm.hexagon.M2.mpyud.nac.hl.s1(i64, i32, i32) #1
380 ; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}-={{ *}}mpyu(r{{[0-9]+}}.h{{ *}},{{ *}}r{{[0-9]+}}.h):<<1
382 define void @test32(i32 %a32, i32 %b32) #0 {
384 %0 = load i64* @c, align 8
385 %1 = tail call i64 @llvm.hexagon.M2.mpyud.nac.hh.s1(i64 %0, i32 %a32, i32 %b32)
386 store i64 %1, i64* @c, align 8
390 declare i64 @llvm.hexagon.M2.mpyud.nac.hh.s1(i64, i32, i32) #1