1 ; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
2 ; RUN: grep ilhu %t1.s | count 8 &&
3 ; RUN: grep iohl %t1.s | count 6 &&
4 ; RUN: grep il %t1.s | count 11 &&
5 ; RUN: grep 16429 %t1.s | count 1 &&
6 ; RUN: grep 63572 %t1.s | count 1 &&
7 ; RUN: grep 128 %t1.s | count 1 &&
8 ; RUN: grep 32639 %t1.s | count 1 &&
9 ; RUN: grep 65535 %t1.s | count 1 &&
10 ; RUN: grep 16457 %t1.s | count 1 &&
11 ; RUN: grep 4059 %t1.s | count 1 &&
12 ; RUN: grep 49077 %t1.s | count 1 &&
13 ; RUN: grep 1267 %t1.s | count 2 &&
14 ; RUN: grep 16309 %t1.s | count 1
16 define i32 @test_1() {
17 ret i32 4784128 ;; ILHU via pattern (0x49000)
20 define i32 @test_2() {
21 ret i32 5308431 ;; ILHU/IOHL via pattern (0x5100f)
24 define i32 @test_3() {
25 ret i32 511 ;; IL via pattern
28 define i32 @test_4() {
29 ret i32 -512 ;; IL via pattern
32 ;; double float floatval
33 ;; 0x4005bf0a80000000 0x402d|f854 2.718282
34 define float @float_const_1() {
35 ret float 0x4005BF0A80000000 ;; ILHU/IOHL
38 ;; double float floatval
39 ;; 0x3810000000000000 0x0080|0000 0.000000
40 define float @float_const_2() {
41 ret float 0x3810000000000000 ;; IL 128
44 ;; double float floatval
45 ;; 0x47efffffe0000000 0x7f7f|ffff NaN
46 define float @float_const_3() {
47 ret float 0x47EFFFFFE0000000 ;; ILHU/IOHL via pattern
50 ;; double float floatval
51 ;; 0x400921fb60000000 0x4049|0fdb 3.141593
52 define float @float_const_4() {
53 ret float 0x400921FB60000000 ;; ILHU/IOHL via pattern
56 ;; double float floatval
57 ;; 0xbff6a09e60000000 0xbfb5|04f3 -1.414214
58 define float @float_const_5() {
59 ret float 0xBFF6A09E60000000 ;; ILHU/IOHL via pattern
62 ;; double float floatval
63 ;; 0x3ff6a09e60000000 0x3fb5|04f3 1.414214
64 define float @float_const_6() {
65 ret float 0x3FF6A09E60000000 ;; ILHU/IOHL via pattern
68 define float @float_const_7() {
69 ret float 0.000000e+00 ;; IL 0 via pattern