2 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a53 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
4 ; For Cortex-A53, shiftable operands that are not actually shifted
5 ; are not needed for an additional two cycles.
7 ; CHECK: ********** MI Scheduling **********
9 ; CHECK: *** Final schedule for BB#0 ***
10 ; CHECK: ADDXrr %vreg0, %vreg2
11 ; CHECK: ADDXrs %vreg0, %vreg2, 5
12 ; CHECK: ********** INTERVALS **********
13 define i64 @shiftable(i64 %A, i64 %B) {
14 %tmp0 = sub i64 %B, 20
15 %tmp1 = shl i64 %tmp0, 5;
16 %tmp2 = add i64 %A, %tmp1;
17 %tmp3 = add i64 %A, %tmp0
18 %tmp4 = mul i64 %tmp2, %tmp3