1 ; RUN: llc < %s -march=arm64 -arm64-neon-syntax=apple -arm64-simd-scalar=true -asm-verbose=false | FileCheck %s
2 ; RUN: llc < %s -march=arm64 -arm64-neon-syntax=generic -arm64-simd-scalar=true -asm-verbose=false | FileCheck %s -check-prefix=GENERIC
4 define <2 x i64> @bar(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
6 ; CHECK: add.2d v[[REG:[0-9]+]], v0, v1
7 ; CHECK: add d[[REG3:[0-9]+]], d[[REG]], d1
8 ; CHECK: sub d[[REG2:[0-9]+]], d[[REG]], d1
10 ; GENERIC: add v[[REG:[0-9]+]].2d, v0.2d, v1.2d
11 ; GENERIC: add d[[REG3:[0-9]+]], d[[REG]], d1
12 ; GENERIC: sub d[[REG2:[0-9]+]], d[[REG]], d1
13 %add = add <2 x i64> %a, %b
14 %vgetq_lane = extractelement <2 x i64> %add, i32 0
15 %vgetq_lane2 = extractelement <2 x i64> %b, i32 0
16 %add3 = add i64 %vgetq_lane, %vgetq_lane2
17 %sub = sub i64 %vgetq_lane, %vgetq_lane2
18 %vecinit = insertelement <2 x i64> undef, i64 %add3, i32 0
19 %vecinit8 = insertelement <2 x i64> %vecinit, i64 %sub, i32 1
20 ret <2 x i64> %vecinit8
23 define double @subdd_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
24 ; CHECK-LABEL: subdd_su64:
25 ; CHECK: sub d0, d1, d0
27 ; GENERIC-LABEL: subdd_su64:
28 ; GENERIC: sub d0, d1, d0
30 %vecext = extractelement <2 x i64> %a, i32 0
31 %vecext1 = extractelement <2 x i64> %b, i32 0
32 %sub.i = sub nsw i64 %vecext1, %vecext
33 %retval = bitcast i64 %sub.i to double
37 define double @vaddd_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
38 ; CHECK-LABEL: vaddd_su64:
39 ; CHECK: add d0, d1, d0
41 ; GENERIC-LABEL: vaddd_su64:
42 ; GENERIC: add d0, d1, d0
44 %vecext = extractelement <2 x i64> %a, i32 0
45 %vecext1 = extractelement <2 x i64> %b, i32 0
46 %add.i = add nsw i64 %vecext1, %vecext
47 %retval = bitcast i64 %add.i to double
51 ; sub MI doesn't access dsub register.
52 define double @add_sub_su64(<2 x i64> %a, <2 x i64> %b) nounwind readnone {
53 ; CHECK-LABEL: add_sub_su64:
54 ; CHECK: add d0, d1, d0
55 ; CHECK: sub d0, {{d[0-9]+}}, d0
57 ; GENERIC-LABEL: add_sub_su64:
58 ; GENERIC: add d0, d1, d0
59 ; GENERIC: sub d0, {{d[0-9]+}}, d0
61 %vecext = extractelement <2 x i64> %a, i32 0
62 %vecext1 = extractelement <2 x i64> %b, i32 0
63 %add.i = add i64 %vecext1, %vecext
64 %sub.i = sub i64 0, %add.i
65 %retval = bitcast i64 %sub.i to double