1 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
4 define arm_aapcs_vfpcc i32 @test_pr7158() nounwind {
5 bb.nph55.bb.nph55.split_crit_edge:
8 bb3: ; preds = %bb3, %bb.nph55.bb.nph55.split_crit_edge
9 br i1 undef, label %bb.i19, label %bb3
11 bb.i19: ; preds = %bb.i19, %bb3
12 %0 = insertelement <4 x float> undef, float undef, i32 3 ; <<4 x float>> [#uses=3]
13 %1 = fmul <4 x float> %0, %0 ; <<4 x float>> [#uses=1]
14 %2 = bitcast <4 x float> %1 to <2 x double> ; <<2 x double>> [#uses=0]
15 %3 = fmul <4 x float> %0, undef ; <<4 x float>> [#uses=0]
19 ; Check that the DAG combiner does not arbitrarily modify BUILD_VECTORs
21 define void @test_illegal_build_vector() nounwind {
23 store <2 x i64> undef, <2 x i64>* undef, align 16
24 %0 = load <16 x i8>* undef, align 16 ; <<16 x i8>> [#uses=1]
25 %1 = or <16 x i8> zeroinitializer, %0 ; <<16 x i8>> [#uses=1]
26 store <16 x i8> %1, <16 x i8>* undef, align 16
30 ; Radar 8407927: Make sure that VMOVRRD gets optimized away when the result is
31 ; converted back to be used as a vector type.
32 ; CHECK: test_vmovrrd_combine
33 define <4 x i32> @test_vmovrrd_combine() nounwind {
35 br i1 undef, label %bb1, label %bb2
38 %0 = bitcast <2 x i64> zeroinitializer to <2 x double>
39 %1 = extractelement <2 x double> %0, i32 0
40 %2 = bitcast double %1 to i64
41 %3 = insertelement <1 x i64> undef, i64 %2, i32 0
44 %4 = shufflevector <1 x i64> %3, <1 x i64> undef, <2 x i32> <i32 0, i32 1>
45 %tmp2006.3 = bitcast <2 x i64> %4 to <16 x i8>
46 %5 = shufflevector <16 x i8> %tmp2006.3, <16 x i8> undef, <16 x i32> <i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19>
47 %tmp2004.3 = bitcast <16 x i8> %5 to <4 x i32>
48 br i1 undef, label %bb2, label %bb1
51 %result = phi <4 x i32> [ undef, %entry ], [ %tmp2004.3, %bb1 ]
55 ; Test trying to do a ShiftCombine on illegal types.
56 ; The vector should be split first.
57 define void @lshrIllegalType(<8 x i32>* %A) nounwind {
58 %tmp1 = load <8 x i32>* %A
59 %tmp2 = lshr <8 x i32> %tmp1, < i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>
60 store <8 x i32> %tmp2, <8 x i32>* %A
64 ; Test folding a binary vector operation with constant BUILD_VECTOR
65 ; operands with i16 elements.
66 define void @test_i16_constant_fold() nounwind optsize {
68 %0 = sext <4 x i1> zeroinitializer to <4 x i16>
69 %1 = add <4 x i16> %0, zeroinitializer
70 %2 = shufflevector <4 x i16> %1, <4 x i16> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
71 %3 = add <8 x i16> %2, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
72 %4 = trunc <8 x i16> %3 to <8 x i8>
73 tail call void @llvm.arm.neon.vst1.v8i8(i8* undef, <8 x i8> %4, i32 1)
77 declare void @llvm.arm.neon.vst1.v8i8(i8*, <8 x i8>, i32) nounwind