1 ; RUN: llc -mtriple=thumbv7k-apple-watchos2.0 -o - %s | FileCheck %s
3 %struct = type { i8, i64, i8, double, i8, <2 x float>, i8, <4 x float> }
5 define i32 @test_i64_align() {
6 ; CHECK-LABEL: test_i64_align:
8 ret i32 ptrtoint(i64* getelementptr(%struct, %struct* null, i32 0, i32 1) to i32)
11 define i32 @test_f64_align() {
12 ; CHECK-LABEL: test_f64_align:
14 ret i32 ptrtoint(double* getelementptr(%struct, %struct* null, i32 0, i32 3) to i32)
17 define i32 @test_v2f32_align() {
18 ; CHECK-LABEL: test_v2f32_align:
20 ret i32 ptrtoint(<2 x float>* getelementptr(%struct, %struct* null, i32 0, i32 5) to i32)
23 define i32 @test_v4f32_align() {
24 ; CHECK-LABEL: test_v4f32_align:
26 ret i32 ptrtoint(<4 x float>* getelementptr(%struct, %struct* null, i32 0, i32 7) to i32)
29 ; Key point here is than an extra register has to be saved so that the DPRs end
30 ; up in an aligned location (as prologue/epilogue inserter had calculated).
31 define void @test_dpr_unwind_align() {
32 ; CHECK-LABEL: test_dpr_unwind_align:
33 ; CHECK: push {r5, r6, r7, lr}
35 ; CHECK: vpush {d8, d9}
37 ; CHECK: bl _test_i64_align
39 ; CHECK: vpop {d8, d9}
41 ; CHECK: pop {r5, r6, r7, pc}
43 call void asm sideeffect "", "~{r6},~{d8},~{d9}"()
46 call i32 @test_i64_align()
50 ; This time, there's no viable way to tack CS-registers onto the list: a real SP
51 ; adjustment needs to be performed to put d8 and d9 where they should be.
52 define void @test_dpr_unwind_align_manually() {
53 ; CHECK-LABEL: test_dpr_unwind_align_manually:
54 ; CHECK: push {r4, r5, r6, r7, lr}
56 ; CHECK: push.w {r8, r11}
58 ; CHECK: vpush {d8, d9}
60 ; CHECK: bl _test_i64_align
62 ; CHECK: vpop {d8, d9}
64 ; CHECK: pop.w {r8, r11}
65 ; CHECK: pop {r4, r5, r6, r7, pc}
67 call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{r8},~{d8},~{d9}"()
70 call i32 @test_i64_align()
74 ; If there's only a CS1 area, the sub should be in the right place:
75 define void @test_dpr_unwind_align_just_cs1() {
76 ; CHECK-LABEL: test_dpr_unwind_align_just_cs1:
77 ; CHECK: push {r4, r5, r6, r7, lr}
79 ; CHECK: vpush {d8, d9}
82 ; CHECK: bl _test_i64_align
84 ; CHECK: vpop {d8, d9}
86 ; CHECK: pop {r4, r5, r6, r7, pc}
88 call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7},~{d8},~{d9}"()
91 call i32 @test_i64_align()
95 ; If there are no DPRs, we shouldn't try to align the stack in stages anyway
96 define void @test_dpr_unwind_align_no_dprs() {
97 ; CHECK-LABEL: test_dpr_unwind_align_no_dprs:
98 ; CHECK: push {r4, r5, r6, r7, lr}
101 ; CHECK: bl _test_i64_align
103 ; CHECK: pop {r4, r5, r6, r7, pc}
105 call void asm sideeffect "", "~{r4},~{r5},~{r6},~{r7}"()
108 call i32 @test_i64_align()
112 ; 128-bit vectors should use 128-bit (i.e. correctly aligned) slots on
114 define <4 x float> @test_v128_stack_pass([8 x double], float, <4 x float> %in) {
115 ; CHECK-LABEL: test_v128_stack_pass:
116 ; CHECK: add r[[ADDR:[0-9]+]], sp, #16
117 ; CHECK: vld1.64 {d0, d1}, [r[[ADDR]]:128]
122 declare void @varargs(i32, ...)
124 ; When varargs are enabled, we go down a different route. Still want 128-bit
126 define void @test_v128_stack_pass_varargs(<4 x float> %in) {
127 ; CHECK-LABEL: test_v128_stack_pass_varargs:
128 ; CHECK: add r[[ADDR:[0-9]+]], sp, #16
129 ; CHECK: vst1.64 {d0, d1}, [r[[ADDR]]:128]
131 call void(i32, ...) @varargs(i32 undef, [3 x i32] undef, float undef, <4 x float> %in)
135 ; To be compatible with AAPCS's va_start model (store r0-r3 at incoming SP, give
136 ; a single pointer), 64-bit quantities must be pass
137 define i64 @test_64bit_gpr_align(i32, i64 %r2_r3, i32 %sp) {
138 ; CHECK-LABEL: test_64bit_gpr_align:
139 ; CHECK: ldr [[RHS:r[0-9]+]], [sp]
140 ; CHECK: adds r0, [[RHS]], r2
141 ; CHECK: adc r1, r3, #0
143 %ext = zext i32 %sp to i64
144 %sum = add i64 %ext, %r2_r3