1 ; RUN: llc < %s -mcpu=swift -mtriple=armv7s-apple-ios | FileCheck %s
3 ; vldm with registers not aligned with q registers need more micro-ops so that
4 ; so that there usage becomes unbeneficial on swift.
6 ; CHECK-LABEL: test_vldm
7 ; CHECK: vldmia r1, {d18, d19, d20}
8 ; CHECK-NOT: vldmia r1, {d17, d18, d19, d20}
10 define double @test_vldm(double %a, double %b, double* nocapture %x) {
12 %mul73 = fmul double %a, %b
13 %addr1 = getelementptr double * %x, i32 1
14 %addr2 = getelementptr double * %x, i32 2
15 %addr3 = getelementptr double * %x, i32 3
16 %load0 = load double * %x
17 %load1 = load double * %addr1
18 %load2 = load double * %addr2
19 %load3 = load double * %addr3
20 %sub = fsub double %mul73, %load1
21 %mul = fmul double %mul73, %load0
22 %add = fadd double %mul73, %load2
23 %div = fdiv double %mul73, %load3
24 %red = fadd double %sub, %mul
25 %red2 = fadd double %div, %add
26 %red3 = fsub double %red, %red2