1 ; RUN: llc -mtriple=arm--none-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
2 ; RUN: llc -mtriple=thumb--none-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
4 ; We cannot codegen the smulw[bt] or smlaw[bt] instructions for these functions,
5 ; as the top 16 bits of the result would differ
7 define i32 @f1(i32 %a, i16 %b) {
11 %tmp1 = sext i16 %b to i32
12 %tmp2 = mul i32 %a, %tmp1
13 %tmp3 = ashr i32 %tmp2, 16
17 define i32 @f2(i32 %a, i16 %b, i32 %c) {
20 ; CHECK: add{{.*}}, asr #16
21 %tmp1 = sext i16 %b to i32
22 %tmp2 = mul i32 %a, %tmp1
23 %tmp3 = ashr i32 %tmp2, 16
24 %tmp4 = add i32 %tmp3, %c