1 ; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s -check-prefix=A8
2 ; RUN: llc < %s -mtriple=armv7-apple-darwin -mcpu=cortex-a9 | FileCheck %s -check-prefix=A9
6 define i32 @test1(i32 %X, i32 %Y, i8 %sh) {
8 ; A8: add r0, r0, r1, lsl r2
11 ; A9: add r0, r0, r1, lsl r2
12 %shift.upgrd.1 = zext i8 %sh to i32
13 %A = shl i32 %Y, %shift.upgrd.1
18 define i32 @test2(i32 %X, i32 %Y, i8 %sh) {
20 ; A8: bic r0, r0, r1, asr r2
23 ; A9: bic r0, r0, r1, asr r2
24 %shift.upgrd.2 = zext i8 %sh to i32
25 %A = ashr i32 %Y, %shift.upgrd.2
31 define i32 @test3(i32 %base, i32 %base2, i32 %offset) {
34 ; A8: ldr r0, [r0, r2, lsl #2]
35 ; A8: ldr r1, [r1, r2, lsl #2]
39 ; A9: ldr r0, [r0, r2, lsl #2]
40 ; A9: ldr r1, [r1, r2, lsl #2]
41 %tmp1 = shl i32 %offset, 2
42 %tmp2 = add i32 %base, %tmp1
43 %tmp3 = inttoptr i32 %tmp2 to i32*
44 %tmp4 = add i32 %base2, %tmp1
45 %tmp5 = inttoptr i32 %tmp4 to i32*
46 %tmp6 = load i32, i32* %tmp3
47 %tmp7 = load i32, i32* %tmp5
48 %tmp8 = add i32 %tmp7, %tmp6
52 declare i8* @malloc(...)
54 define fastcc void @test4(i16 %addr) nounwind {
57 ; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
58 ; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
59 ; A8: str [[REG]], [r0, r1, lsl #2]
60 ; A8-NOT: str [[REG]], [r0]
63 ; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
64 ; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
65 ; A9: str [[REG]], [r0, r1, lsl #2]
66 ; A9-NOT: str [[REG]], [r0]
67 %0 = tail call i8* (...) @malloc(i32 undef) nounwind
68 %1 = bitcast i8* %0 to i32*
69 %2 = sext i16 %addr to i32
70 %3 = getelementptr inbounds i32, i32* %1, i32 %2
71 %4 = load i32, i32* %3, align 4
72 %5 = add nsw i32 %4, 1
73 store i32 %5, i32* %3, align 4