ARM pop of a single register encodes as post-indexed LDR.
[oota-llvm.git] / test / CodeGen / ARM / ifcvt9.ll
1 ; RUN: llc < %s -march=arm
2
3 define fastcc void @t() nounwind {
4 entry:
5         br i1 undef, label %bb.i.i3, label %growMapping.exit
6
7 bb.i.i3:                ; preds = %entry
8         unreachable
9
10 growMapping.exit:               ; preds = %entry
11         unreachable
12 }