1 ; This tests that MC/asm header conversion is smooth and that the
2 ; build attributes are correct
4 ; RUN: llc < %s -mtriple=thumbv5-linux-gnueabi -mcpu=xscale | FileCheck %s --check-prefix=XSCALE
5 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi | FileCheck %s --check-prefix=V6
6 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6-FAST
7 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
8 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi | FileCheck %s --check-prefix=V6M
9 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V6M-FAST
10 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s | FileCheck %s --check-prefix=ARM1156T2F-S
11 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=ARM1156T2F-S-FAST
12 ; RUN: llc < %s -mtriple=armv6-linux-gnueabi -mcpu=arm1156t2f-s -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
13 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi | FileCheck %s --check-prefix=V7M
14 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V7M-FAST
15 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
16 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=V7
17 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
18 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V7-FAST
19 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8
20 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=V8-FAST
21 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
22 ; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi | FileCheck %s --check-prefix=Vt8
23 ; RUN: llc < %s -mtriple=thumbv8-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
24 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-neon,-crypto | FileCheck %s --check-prefix=V8-FPARMv8
25 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-fp-armv8,-crypto | FileCheck %s --check-prefix=V8-NEON
26 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mattr=-crypto | FileCheck %s --check-prefix=V8-FPARMv8-NEON
27 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi | FileCheck %s --check-prefix=V8-FPARMv8-NEON-CRYPTO
28 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT
29 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT-FAST
30 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
31 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-neon,+d16 | FileCheck %s --check-prefix=CORTEX-A5-NONEON
32 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A5-NOFPU
33 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-NOFPU-FAST
34 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A9-SOFT
35 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A9-SOFT-FAST
36 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-A9-HARD
37 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=hard -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A9-HARD-FAST
38 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
39 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 | FileCheck %s --check-prefix=CORTEX-A12-DEFAULT
40 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A9-SOFT
41 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A12-DEFAULT-FAST
42 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A12-NOFPU
43 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -mattr=-vfp2 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A12-NOFPU-FAST
44 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
45 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 | FileCheck %s --check-prefix=CORTEX-A15
46 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A15-FAST
47 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
48 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 | FileCheck %s --check-prefix=CORTEX-A17-DEFAULT
49 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A17-FAST
50 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-A17-NOFPU
51 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -mattr=-vfp2 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A17-NOFPU-FAST
52 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
53 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=CORTEX-M0
54 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M0-FAST
55 ; RUN: llc < %s -mtriple=thumbv6m-linux-gnueabi -mcpu=cortex-m0 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
56 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=CORTEX-M3
57 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M3-FAST
58 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m3 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
59 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-M4-SOFT
60 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=soft -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M4-SOFT-FAST
61 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-M4-HARD
62 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M4-HARD-FAST
63 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
64 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=-vfp2 | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-SOFT
65 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=-vfp2 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M7-NOFPU-FAST
66 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=+fp-only-sp | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-SINGLE
67 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=+fp-only-sp -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M7-FAST
68 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 | FileCheck %s --check-prefix=CORTEX-M7-DOUBLE
69 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
70 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=CORTEX-R5
71 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-R5-FAST
72 ; RUN: llc < %s -mtriple=armv7r-linux-gnueabi -mcpu=cortex-r5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
73 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 | FileCheck %s --check-prefix=CORTEX-A53
74 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A53-FAST
75 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a53 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
76 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=CORTEX-A57
77 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A57-FAST
78 ; RUN: llc < %s -mtriple=armv8-linux-gnueabi -mcpu=cortex-a57 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
79 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s --check-prefix=CORTEX-A7-CHECK
80 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-CHECK-FAST
81 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2,-vfp3,-vfp4,-neon | FileCheck %s --check-prefix=CORTEX-A7-NOFPU
82 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2,-vfp3,-vfp4,-neon -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-NOFPU-FAST
83 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,-neon | FileCheck %s --check-prefix=CORTEX-A7-FPUV4
84 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
85 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,-neon -enable-unsafe-fp-math -disable-fp-elim -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-FPUV4-FAST
86 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,,+d16,-neon | FileCheck %s --check-prefix=CORTEX-A7-FPUV4
87 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -relocation-model=pic | FileCheck %s --check-prefix=RELOC-PIC
88 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -relocation-model=static | FileCheck %s --check-prefix=RELOC-OTHER
89 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -relocation-model=default | FileCheck %s --check-prefix=RELOC-OTHER
90 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -relocation-model=dynamic-no-pic | FileCheck %s --check-prefix=RELOC-OTHER
91 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi | FileCheck %s --check-prefix=RELOC-OTHER
92 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi | FileCheck %s --check-prefix=PCS-R9-USE
93 ; RUN: llc < %s -mtriple=arm-none-linux-gnueabi -arm-reserve-r9 | FileCheck %s --check-prefix=PCS-R9-RESERVE
96 ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
97 ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
98 ; RUN: llc < %s -mtriple=armv8-none-linux-gnueabi -mcpu=cortex-a57 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
100 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
101 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
102 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
104 ; RUN: llc < %s -mtriple=armv7r-none-linux-gnueabi -mcpu=cortex-r5 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
105 ; RUN: llc < %s -mtriple=armv7r-none-linux-gnueabi -mcpu=cortex-r5 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
106 ; RUN: llc < %s -mtriple=armv7r-none-linux-gnueabi -mcpu=cortex-r5 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
108 ; RUN: llc < %s -mtriple=thumbv7m-none-linux-gnueabi -mcpu=cortex-m3 -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
109 ; RUN: llc < %s -mtriple=thumbv7m-none-linux-gnueabi -mcpu=cortex-m3 -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
110 ; RUN: llc < %s -mtriple=thumbv7m-none-linux-gnueabi -mcpu=cortex-m3 | FileCheck %s --check-prefix=NO-STRICT-ALIGN
112 ; RUN: llc < %s -mtriple=armv6-none-netbsd-gnueabi -mcpu=arm1136j-s | FileCheck %s --check-prefix=NO-STRICT-ALIGN
113 ; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s | FileCheck %s --check-prefix=STRICT-ALIGN
114 ; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
115 ; RUN: llc < %s -mtriple=armv6-none-linux-gnueabi -mcpu=arm1136j-s -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
117 ; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -arm-no-strict-align -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN
118 ; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -arm-strict-align -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN
119 ; RUN: llc < %s -mtriple=thumbv6m-none-linux-gnueabi -arm-no-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
120 ; RUN: llc < %s -mtriple=thumbv6m-none-linux-gnueabi -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
121 ; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN
122 ; RUN: llc < %s -mtriple=thumb-none-linux-gnueabi -mcpu=cortex-m0 | FileCheck %s --check-prefix=STRICT-ALIGN
124 ; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e -arm-no-strict-align | FileCheck %s --check-prefix=NO-STRICT-ALIGN
125 ; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e -arm-strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
126 ; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e | FileCheck %s --check-prefix=STRICT-ALIGN
128 ; XSCALE: .eabi_attribute 6, 5
129 ; XSCALE: .eabi_attribute 8, 1
130 ; XSCALE: .eabi_attribute 9, 1
132 ; DYN-ROUNDING: .eabi_attribute 19, 1
134 ; V6: .eabi_attribute 6, 6
135 ; V6: .eabi_attribute 8, 1
136 ;; We assume round-to-nearest by default (matches GCC)
137 ; V6-NOT: .eabi_attribute 19
138 ;; The default choice made by llc is for a V6 CPU without an FPU.
139 ;; This is not an interesting detail, but for such CPUs, the default intention is to use
140 ;; software floating-point support. The choice is not important for targets without
142 ; V6: .eabi_attribute 20, 1
143 ; V6: .eabi_attribute 21, 1
144 ; V6-NOT: .eabi_attribute 22
145 ; V6: .eabi_attribute 23, 3
146 ; V6: .eabi_attribute 24, 1
147 ; V6: .eabi_attribute 25, 1
148 ; V6-NOT: .eabi_attribute 27
149 ; V6-NOT: .eabi_attribute 28
150 ; V6-NOT: .eabi_attribute 36
151 ; V6: .eabi_attribute 38, 1
152 ; V6-NOT: .eabi_attribute 42
153 ; V6-NOT: .eabi_attribute 68
155 ; V6-FAST-NOT: .eabi_attribute 19
156 ;; Despite the V6 CPU having no FPU by default, we chose to flush to
157 ;; positive zero here. There's no hardware support doing this, but the
158 ;; fast maths software library might.
159 ; V6-FAST-NOT: .eabi_attribute 20
160 ; V6-FAST-NOT: .eabi_attribute 21
161 ; V6-FAST-NOT: .eabi_attribute 22
162 ; V6-FAST: .eabi_attribute 23, 1
164 ; V6M: .eabi_attribute 6, 12
165 ; V6M-NOT: .eabi_attribute 7
166 ; V6M: .eabi_attribute 8, 0
167 ; V6M: .eabi_attribute 9, 1
168 ; V6M-NOT: .eabi_attribute 19
169 ;; The default choice made by llc is for a V6M CPU without an FPU.
170 ;; This is not an interesting detail, but for such CPUs, the default intention is to use
171 ;; software floating-point support. The choice is not important for targets without
173 ; V6M: .eabi_attribute 20, 1
174 ; V6M: .eabi_attribute 21, 1
175 ; V6M-NOT: .eabi_attribute 22
176 ; V6M: .eabi_attribute 23, 3
177 ; V6M: .eabi_attribute 24, 1
178 ; V6M: .eabi_attribute 25, 1
179 ; V6M-NOT: .eabi_attribute 27
180 ; V6M-NOT: .eabi_attribute 28
181 ; V6M-NOT: .eabi_attribute 36
182 ; V6M: .eabi_attribute 38, 1
183 ; V6M-NOT: .eabi_attribute 42
184 ; V6M-NOT: .eabi_attribute 68
186 ; V6M-FAST-NOT: .eabi_attribute 19
187 ;; Despite the V6M CPU having no FPU by default, we chose to flush to
188 ;; positive zero here. There's no hardware support doing this, but the
189 ;; fast maths software library might.
190 ; V6M-FAST-NOT: .eabi_attribute 20
191 ; V6M-FAST-NOT: .eabi_attribute 21
192 ; V6M-FAST-NOT: .eabi_attribute 22
193 ; V6M-FAST: .eabi_attribute 23, 1
195 ; ARM1156T2F-S: .cpu arm1156t2f-s
196 ; ARM1156T2F-S: .eabi_attribute 6, 8
197 ; ARM1156T2F-S: .eabi_attribute 8, 1
198 ; ARM1156T2F-S: .eabi_attribute 9, 2
199 ; ARM1156T2F-S: .fpu vfpv2
200 ; ARM1156T2F-S-NOT: .eabi_attribute 19
201 ;; We default to IEEE 754 compliance
202 ; ARM1156T2F-S: .eabi_attribute 20, 1
203 ; ARM1156T2F-S: .eabi_attribute 21, 1
204 ; ARM1156T2F-S-NOT: .eabi_attribute 22
205 ; ARM1156T2F-S: .eabi_attribute 23, 3
206 ; ARM1156T2F-S: .eabi_attribute 24, 1
207 ; ARM1156T2F-S: .eabi_attribute 25, 1
208 ; ARM1156T2F-S-NOT: .eabi_attribute 27
209 ; ARM1156T2F-S-NOT: .eabi_attribute 28
210 ; ARM1156T2F-S-NOT: .eabi_attribute 36
211 ; ARM1156T2F-S: .eabi_attribute 38, 1
212 ; ARM1156T2F-S-NOT: .eabi_attribute 42
213 ; ARM1156T2F-S-NOT: .eabi_attribute 68
215 ; ARM1156T2F-S-FAST-NOT: .eabi_attribute 19
216 ;; V6 cores default to flush to positive zero (value 0). Note that value 2 is also equally
217 ;; valid for this core, it's an implementation defined question as to which of 0 and 2 you
218 ;; select. LLVM historically picks 0.
219 ; ARM1156T2F-S-FAST-NOT: .eabi_attribute 20
220 ; ARM1156T2F-S-FAST-NOT: .eabi_attribute 21
221 ; ARM1156T2F-S-FAST-NOT: .eabi_attribute 22
222 ; ARM1156T2F-S-FAST: .eabi_attribute 23, 1
224 ; V7M: .eabi_attribute 6, 10
225 ; V7M: .eabi_attribute 7, 77
226 ; V7M: .eabi_attribute 8, 0
227 ; V7M: .eabi_attribute 9, 2
228 ; V7M-NOT: .eabi_attribute 19
229 ;; The default choice made by llc is for a V7M CPU without an FPU.
230 ;; This is not an interesting detail, but for such CPUs, the default intention is to use
231 ;; software floating-point support. The choice is not important for targets without
233 ; V7M: .eabi_attribute 20, 1
234 ; V7M: .eabi_attribute 21, 1
235 ; V7M-NOT: .eabi_attribute 22
236 ; V7M: .eabi_attribute 23, 3
237 ; V7M: .eabi_attribute 24, 1
238 ; V7M: .eabi_attribute 25, 1
239 ; V7M-NOT: .eabi_attribute 27
240 ; V7M-NOT: .eabi_attribute 28
241 ; V7M-NOT: .eabi_attribute 36
242 ; V7M: .eabi_attribute 38, 1
243 ; V7M-NOT: .eabi_attribute 42
244 ; V7M-NOT: .eabi_attribute 44
245 ; V7M-NOT: .eabi_attribute 68
247 ; V7M-FAST-NOT: .eabi_attribute 19
248 ;; Despite the V7M CPU having no FPU by default, we chose to flush
249 ;; preserving sign. This matches what the hardware would do in the
250 ;; architecture revision were to exist on the current target.
251 ; V7M-FAST: .eabi_attribute 20, 2
252 ; V7M-FAST-NOT: .eabi_attribute 21
253 ; V7M-FAST-NOT: .eabi_attribute 22
254 ; V7M-FAST: .eabi_attribute 23, 1
256 ; V7: .syntax unified
257 ; V7: .eabi_attribute 6, 10
258 ; V7-NOT: .eabi_attribute 19
259 ;; In safe-maths mode we default to an IEEE 754 compliant choice.
260 ; V7: .eabi_attribute 20, 1
261 ; V7: .eabi_attribute 21, 1
262 ; V7-NOT: .eabi_attribute 22
263 ; V7: .eabi_attribute 23, 3
264 ; V7: .eabi_attribute 24, 1
265 ; V7: .eabi_attribute 25, 1
266 ; V7-NOT: .eabi_attribute 27
267 ; V7-NOT: .eabi_attribute 28
268 ; V7-NOT: .eabi_attribute 36
269 ; V7: .eabi_attribute 38, 1
270 ; V7-NOT: .eabi_attribute 42
271 ; V7-NOT: .eabi_attribute 68
273 ; V7-FAST-NOT: .eabi_attribute 19
274 ;; The default CPU does have an FPU and it must be VFPv3 or better, so it flushes
275 ;; denormals to zero preserving the sign.
276 ; V7-FAST: .eabi_attribute 20, 2
277 ; V7-FAST-NOT: .eabi_attribute 21
278 ; V7-FAST-NOT: .eabi_attribute 22
279 ; V7-FAST: .eabi_attribute 23, 1
281 ; V8: .syntax unified
282 ; V8: .eabi_attribute 67, "2.09"
283 ; V8: .eabi_attribute 6, 14
284 ; V8-NOT: .eabi_attribute 19
285 ; V8: .eabi_attribute 20, 1
286 ; V8: .eabi_attribute 21, 1
287 ; V8-NOT: .eabi_attribute 22
288 ; V8: .eabi_attribute 23, 3
290 ; V8-FAST-NOT: .eabi_attribute 19
291 ;; The default does have an FPU, and for V8-A, it flushes preserving sign.
292 ; V8-FAST: .eabi_attribute 20, 2
293 ; V8-FAST-NOT: .eabi_attribute 21
294 ; V8-FAST-NOT: .eabi_attribute 22
295 ; V8-FAST: .eabi_attribute 23, 1
297 ; Vt8: .syntax unified
298 ; Vt8: .eabi_attribute 6, 14
299 ; Vt8-NOT: .eabi_attribute 19
300 ; Vt8: .eabi_attribute 20, 1
301 ; Vt8: .eabi_attribute 21, 1
302 ; Vt8-NOT: .eabi_attribute 22
303 ; Vt8: .eabi_attribute 23, 3
305 ; V8-FPARMv8: .syntax unified
306 ; V8-FPARMv8: .eabi_attribute 6, 14
307 ; V8-FPARMv8: .fpu fp-armv8
309 ; V8-NEON: .syntax unified
310 ; V8-NEON: .eabi_attribute 6, 14
312 ; V8-NEON: .eabi_attribute 12, 3
314 ; V8-FPARMv8-NEON: .syntax unified
315 ; V8-FPARMv8-NEON: .eabi_attribute 6, 14
316 ; V8-FPARMv8-NEON: .fpu neon-fp-armv8
317 ; V8-FPARMv8-NEON: .eabi_attribute 12, 3
319 ; V8-FPARMv8-NEON-CRYPTO: .syntax unified
320 ; V8-FPARMv8-NEON-CRYPTO: .eabi_attribute 6, 14
321 ; V8-FPARMv8-NEON-CRYPTO: .fpu crypto-neon-fp-armv8
322 ; V8-FPARMv8-NEON-CRYPTO: .eabi_attribute 12, 3
324 ; Tag_CPU_unaligned_access
325 ; NO-STRICT-ALIGN: .eabi_attribute 34, 1
326 ; STRICT-ALIGN: .eabi_attribute 34, 0
328 ; Tag_CPU_arch 'ARMv7'
329 ; CORTEX-A7-CHECK: .eabi_attribute 6, 10
330 ; CORTEX-A7-NOFPU: .eabi_attribute 6, 10
332 ; CORTEX-A7-FPUV4: .eabi_attribute 6, 10
334 ; Tag_CPU_arch_profile 'A'
335 ; CORTEX-A7-CHECK: .eabi_attribute 7, 65
336 ; CORTEX-A7-NOFPU: .eabi_attribute 7, 65
337 ; CORTEX-A7-FPUV4: .eabi_attribute 7, 65
340 ; CORTEX-A7-CHECK: .eabi_attribute 8, 1
341 ; CORTEX-A7-NOFPU: .eabi_attribute 8, 1
342 ; CORTEX-A7-FPUV4: .eabi_attribute 8, 1
345 ; CORTEX-A7-CHECK: .eabi_attribute 9, 2
346 ; CORTEX-A7-NOFPU: .eabi_attribute 9, 2
347 ; CORTEX-A7-FPUV4: .eabi_attribute 9, 2
349 ; CORTEX-A7-CHECK: .fpu neon-vfpv4
350 ; CORTEX-A7-NOFPU-NOT: .fpu
351 ; CORTEX-A7-FPUV4: .fpu vfpv4
353 ; CORTEX-A7-CHECK-NOT: .eabi_attribute 19
354 ; Tag_ABI_FP_denormal
355 ;; We default to IEEE 754 compliance
356 ; CORTEX-A7-CHECK: .eabi_attribute 20, 1
357 ;; The A7 has VFPv3 support by default, so flush preserving sign.
358 ; CORTEX-A7-CHECK-FAST: .eabi_attribute 20, 2
359 ; CORTEX-A7-NOFPU: .eabi_attribute 20, 1
360 ;; Despite there being no FPU, we chose to flush to zero preserving
361 ;; sign. This matches what the hardware would do for this architecture
363 ; CORTEX-A7-NOFPU-FAST: .eabi_attribute 20, 2
364 ; CORTEX-A7-FPUV4: .eabi_attribute 20, 1
365 ;; The VFPv4 FPU flushes preserving sign.
366 ; CORTEX-A7-FPUV4-FAST: .eabi_attribute 20, 2
368 ; Tag_ABI_FP_exceptions
369 ; CORTEX-A7-CHECK: .eabi_attribute 21, 1
370 ; CORTEX-A7-NOFPU: .eabi_attribute 21, 1
371 ; CORTEX-A7-FPUV4: .eabi_attribute 21, 1
373 ; Tag_ABI_FP_user_exceptions
374 ; CORTEX-A7-CHECK-NOT: .eabi_attribute 22
375 ; CORTEX-A7-NOFPU-NOT: .eabi_attribute 22
376 ; CORTEX-A7-FPUV4-NOT: .eabi_attribute 22
378 ; Tag_ABI_FP_number_model
379 ; CORTEX-A7-CHECK: .eabi_attribute 23, 3
380 ; CORTEX-A7-NOFPU: .eabi_attribute 23, 3
381 ; CORTEX-A7-FPUV4: .eabi_attribute 23, 3
383 ; Tag_ABI_align_needed
384 ; CORTEX-A7-CHECK: .eabi_attribute 24, 1
385 ; CORTEX-A7-NOFPU: .eabi_attribute 24, 1
386 ; CORTEX-A7-FPUV4: .eabi_attribute 24, 1
388 ; Tag_ABI_align_preserved
389 ; CORTEX-A7-CHECK: .eabi_attribute 25, 1
390 ; CORTEX-A7-NOFPU: .eabi_attribute 25, 1
391 ; CORTEX-A7-FPUV4: .eabi_attribute 25, 1
393 ; Tag_FP_HP_extension
394 ; CORTEX-A7-CHECK: .eabi_attribute 36, 1
395 ; CORTEX-A7-NOFPU: .eabi_attribute 36, 1
396 ; CORTEX-A7-FPUV4: .eabi_attribute 36, 1
398 ; Tag_FP_16bit_format
399 ; CORTEX-A7-CHECK: .eabi_attribute 38, 1
400 ; CORTEX-A7-NOFPU: .eabi_attribute 38, 1
401 ; CORTEX-A7-FPUV4: .eabi_attribute 38, 1
403 ; Tag_MPextension_use
404 ; CORTEX-A7-CHECK: .eabi_attribute 42, 1
405 ; CORTEX-A7-NOFPU: .eabi_attribute 42, 1
406 ; CORTEX-A7-FPUV4: .eabi_attribute 42, 1
409 ; CORTEX-A7-CHECK: .eabi_attribute 44, 2
410 ; CORTEX-A7-NOFPU: .eabi_attribute 44, 2
411 ; CORTEX-A7-FPUV4: .eabi_attribute 44, 2
413 ; Tag_Virtualization_use
414 ; CORTEX-A7-CHECK: .eabi_attribute 68, 3
415 ; CORTEX-A7-NOFPU: .eabi_attribute 68, 3
416 ; CORTEX-A7-FPUV4: .eabi_attribute 68, 3
418 ; CORTEX-A5-DEFAULT: .cpu cortex-a5
419 ; CORTEX-A5-DEFAULT: .eabi_attribute 6, 10
420 ; CORTEX-A5-DEFAULT: .eabi_attribute 7, 65
421 ; CORTEX-A5-DEFAULT: .eabi_attribute 8, 1
422 ; CORTEX-A5-DEFAULT: .eabi_attribute 9, 2
423 ; CORTEX-A5-DEFAULT: .fpu neon-vfpv4
424 ; CORTEX-A5-NOT: .eabi_attribute 19
425 ;; We default to IEEE 754 compliance
426 ; CORTEX-A5-DEFAULT: .eabi_attribute 20, 1
427 ; CORTEX-A5-DEFAULT: .eabi_attribute 21, 1
428 ; CORTEX-A5-DEFAULT-NOT: .eabi_attribute 22
429 ; CORTEX-A5-DEFAULT: .eabi_attribute 23, 3
430 ; CORTEX-A5-DEFAULT: .eabi_attribute 24, 1
431 ; CORTEX-A5-DEFAULT: .eabi_attribute 25, 1
432 ; CORTEX-A5-DEFAULT: .eabi_attribute 42, 1
433 ; CORTEX-A5-DEFAULT: .eabi_attribute 68, 1
435 ; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 19
436 ;; The A5 defaults to a VFPv4 FPU, so it flushed preserving sign when -ffast-math
438 ; CORTEX-A5-DEFAULT-FAST: .eabi_attribute 20, 2
439 ; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 21
440 ; CORTEX-A5-DEFAULT-FAST-NOT: .eabi_attribute 22
441 ; CORTEX-A5-DEFAULT-FAST: .eabi_attribute 23, 1
443 ; CORTEX-A5-NONEON: .cpu cortex-a5
444 ; CORTEX-A5-NONEON: .eabi_attribute 6, 10
445 ; CORTEX-A5-NONEON: .eabi_attribute 7, 65
446 ; CORTEX-A5-NONEON: .eabi_attribute 8, 1
447 ; CORTEX-A5-NONEON: .eabi_attribute 9, 2
448 ; CORTEX-A5-NONEON: .fpu vfpv4-d16
449 ;; We default to IEEE 754 compliance
450 ; CORTEX-A5-NONEON: .eabi_attribute 20, 1
451 ; CORTEX-A5-NONEON: .eabi_attribute 21, 1
452 ; CORTEX-A5-NONEON-NOT: .eabi_attribute 22
453 ; CORTEX-A5-NONEON: .eabi_attribute 23, 3
454 ; CORTEX-A5-NONEON: .eabi_attribute 24, 1
455 ; CORTEX-A5-NONEON: .eabi_attribute 25, 1
456 ; CORTEX-A5-NONEON: .eabi_attribute 42, 1
457 ; CORTEX-A5-NONEON: .eabi_attribute 68, 1
459 ; CORTEX-A5-NONEON-FAST-NOT: .eabi_attribute 19
460 ;; The A5 defaults to a VFPv4 FPU, so it flushed preserving sign when -ffast-math
462 ; CORTEX-A5-NONEON-FAST: .eabi_attribute 20, 2
463 ; CORTEX-A5-NONEON-FAST-NOT: .eabi_attribute 21
464 ; CORTEX-A5-NONEON-FAST-NOT: .eabi_attribute 22
465 ; CORTEX-A5-NONEON-FAST: .eabi_attribute 23, 1
467 ; CORTEX-A5-NOFPU: .cpu cortex-a5
468 ; CORTEX-A5-NOFPU: .eabi_attribute 6, 10
469 ; CORTEX-A5-NOFPU: .eabi_attribute 7, 65
470 ; CORTEX-A5-NOFPU: .eabi_attribute 8, 1
471 ; CORTEX-A5-NOFPU: .eabi_attribute 9, 2
472 ; CORTEX-A5-NOFPU-NOT: .fpu
473 ; CORTEX-A5-NOFPU-NOT: .eabi_attribute 19
474 ;; We default to IEEE 754 compliance
475 ; CORTEX-A5-NOFPU: .eabi_attribute 20, 1
476 ; CORTEX-A5-NOFPU: .eabi_attribute 21, 1
477 ; CORTEX-A5-NOFPU-NOT: .eabi_attribute 22
478 ; CORTEX-A5-NOFPU: .eabi_attribute 23, 3
479 ; CORTEX-A5-NOFPU: .eabi_attribute 24, 1
480 ; CORTEX-A5-NOFPU: .eabi_attribute 25, 1
481 ; CORTEX-A5-NOFPU: .eabi_attribute 42, 1
482 ; CORTEX-A5-NOFPU: .eabi_attribute 68, 1
484 ; CORTEX-A5-NOFPU-FAST-NOT: .eabi_attribute 19
485 ;; Despite there being no FPU, we chose to flush to zero preserving
486 ;; sign. This matches what the hardware would do for this architecture
488 ; CORTEX-A5-NOFPU-FAST: .eabi_attribute 20, 2
489 ; CORTEX-A5-NOFPU-FAST-NOT: .eabi_attribute 21
490 ; CORTEX-A5-NOFPU-FAST-NOT: .eabi_attribute 22
491 ; CORTEX-A5-NOFPU-FAST: .eabi_attribute 23, 1
493 ; CORTEX-A9-SOFT: .cpu cortex-a9
494 ; CORTEX-A9-SOFT: .eabi_attribute 6, 10
495 ; CORTEX-A9-SOFT: .eabi_attribute 7, 65
496 ; CORTEX-A9-SOFT: .eabi_attribute 8, 1
497 ; CORTEX-A9-SOFT: .eabi_attribute 9, 2
498 ; CORTEX-A9-SOFT: .fpu neon
499 ; CORTEX-A9-SOFT-NOT: .eabi_attribute 19
500 ;; We default to IEEE 754 compliance
501 ; CORTEX-A9-SOFT: .eabi_attribute 20, 1
502 ; CORTEX-A9-SOFT: .eabi_attribute 21, 1
503 ; CORTEX-A9-SOFT-NOT: .eabi_attribute 22
504 ; CORTEX-A9-SOFT: .eabi_attribute 23, 3
505 ; CORTEX-A9-SOFT: .eabi_attribute 24, 1
506 ; CORTEX-A9-SOFT: .eabi_attribute 25, 1
507 ; CORTEX-A9-SOFT-NOT: .eabi_attribute 27
508 ; CORTEX-A9-SOFT-NOT: .eabi_attribute 28
509 ; CORTEX-A9-SOFT: .eabi_attribute 36, 1
510 ; CORTEX-A9-SOFT: .eabi_attribute 38, 1
511 ; CORTEX-A9-SOFT: .eabi_attribute 42, 1
512 ; CORTEX-A9-SOFT: .eabi_attribute 68, 1
514 ; CORTEX-A9-SOFT-FAST-NOT: .eabi_attribute 19
515 ;; The A9 defaults to a VFPv3 FPU, so it flushes preseving sign when
516 ;; -ffast-math is specified.
517 ; CORTEX-A9-SOFT-FAST: .eabi_attribute 20, 2
518 ; CORTEX-A5-SOFT-FAST-NOT: .eabi_attribute 21
519 ; CORTEX-A5-SOFT-FAST-NOT: .eabi_attribute 22
520 ; CORTEX-A5-SOFT-FAST: .eabi_attribute 23, 1
522 ; CORTEX-A9-HARD: .cpu cortex-a9
523 ; CORTEX-A9-HARD: .eabi_attribute 6, 10
524 ; CORTEX-A9-HARD: .eabi_attribute 7, 65
525 ; CORTEX-A9-HARD: .eabi_attribute 8, 1
526 ; CORTEX-A9-HARD: .eabi_attribute 9, 2
527 ; CORTEX-A9-HARD: .fpu neon
528 ; CORTEX-A9-HARD-NOT: .eabi_attribute 19
529 ;; We default to IEEE 754 compliance
530 ; CORTEX-A9-HARD: .eabi_attribute 20, 1
531 ; CORTEX-A9-HARD: .eabi_attribute 21, 1
532 ; CORTEX-A9-HARD-NOT: .eabi_attribute 22
533 ; CORTEX-A9-HARD: .eabi_attribute 23, 3
534 ; CORTEX-A9-HARD: .eabi_attribute 24, 1
535 ; CORTEX-A9-HARD: .eabi_attribute 25, 1
536 ; CORTEX-A9-HARD-NOT: .eabi_attribute 27
537 ; CORTEX-A9-HARD: .eabi_attribute 28, 1
538 ; CORTEX-A9-HARD: .eabi_attribute 36, 1
539 ; CORTEX-A9-HARD: .eabi_attribute 38, 1
540 ; CORTEX-A9-HARD: .eabi_attribute 42, 1
541 ; CORTEX-A9-HARD: .eabi_attribute 68, 1
543 ; CORTEX-A9-HARD-FAST-NOT: .eabi_attribute 19
544 ;; The A9 defaults to a VFPv3 FPU, so it flushes preseving sign when
545 ;; -ffast-math is specified.
546 ; CORTEX-A9-HARD-FAST: .eabi_attribute 20, 2
547 ; CORTEX-A9-HARD-FAST-NOT: .eabi_attribute 21
548 ; CORTEX-A9-HARD-FAST-NOT: .eabi_attribute 22
549 ; CORTEX-A9-HARD-FAST: .eabi_attribute 23, 1
551 ; CORTEX-A12-DEFAULT: .cpu cortex-a12
552 ; CORTEX-A12-DEFAULT: .eabi_attribute 6, 10
553 ; CORTEX-A12-DEFAULT: .eabi_attribute 7, 65
554 ; CORTEX-A12-DEFAULT: .eabi_attribute 8, 1
555 ; CORTEX-A12-DEFAULT: .eabi_attribute 9, 2
556 ; CORTEX-A12-DEFAULT: .fpu neon-vfpv4
557 ; CORTEX-A12-DEFAULT-NOT: .eabi_attribute 19
558 ;; We default to IEEE 754 compliance
559 ; CORTEX-A12-DEFAULT: .eabi_attribute 20, 1
560 ; CORTEX-A12-DEFAULT: .eabi_attribute 21, 1
561 ; CORTEX-A12-DEFAULT-NOT: .eabi_attribute 22
562 ; CORTEX-A12-DEFAULT: .eabi_attribute 23, 3
563 ; CORTEX-A12-DEFAULT: .eabi_attribute 24, 1
564 ; CORTEX-A12-DEFAULT: .eabi_attribute 25, 1
565 ; CORTEX-A12-DEFAULT: .eabi_attribute 42, 1
566 ; CORTEX-A12-DEFAULT: .eabi_attribute 44, 2
567 ; CORTEX-A12-DEFAULT: .eabi_attribute 68, 3
569 ; CORTEX-A12-DEFAULT-FAST-NOT: .eabi_attribute 19
570 ;; The A12 defaults to a VFPv3 FPU, so it flushes preseving sign when
571 ;; -ffast-math is specified.
572 ; CORTEX-A12-DEFAULT-FAST: .eabi_attribute 20, 2
573 ; CORTEX-A12-HARD-FAST-NOT: .eabi_attribute 21
574 ; CORTEX-A12-HARD-FAST-NOT: .eabi_attribute 22
575 ; CORTEX-A12-HARD-FAST: .eabi_attribute 23, 1
577 ; CORTEX-A12-NOFPU: .cpu cortex-a12
578 ; CORTEX-A12-NOFPU: .eabi_attribute 6, 10
579 ; CORTEX-A12-NOFPU: .eabi_attribute 7, 65
580 ; CORTEX-A12-NOFPU: .eabi_attribute 8, 1
581 ; CORTEX-A12-NOFPU: .eabi_attribute 9, 2
582 ; CORTEX-A12-NOFPU-NOT: .fpu
583 ; CORTEX-A12-NOFPU-NOT: .eabi_attribute 19
584 ;; We default to IEEE 754 compliance
585 ; CORTEX-A12-NOFPU: .eabi_attribute 20, 1
586 ; CORTEX-A12-NOFPU: .eabi_attribute 21, 1
587 ; CORTEX-A12-NOFPU-NOT: .eabi_attribute 22
588 ; CORTEX-A12-NOFPU: .eabi_attribute 23, 3
589 ; CORTEX-A12-NOFPU: .eabi_attribute 24, 1
590 ; CORTEX-A12-NOFPU: .eabi_attribute 25, 1
591 ; CORTEX-A12-NOFPU: .eabi_attribute 42, 1
592 ; CORTEX-A12-NOFPU: .eabi_attribute 44, 2
593 ; CORTEX-A12-NOFPU: .eabi_attribute 68, 3
595 ; CORTEX-A12-NOFPU-FAST-NOT: .eabi_attribute 19
596 ;; Despite there being no FPU, we chose to flush to zero preserving
597 ;; sign. This matches what the hardware would do for this architecture
599 ; CORTEX-A12-NOFPU-FAST: .eabi_attribute 20, 2
600 ; CORTEX-A12-NOFPU-FAST-NOT: .eabi_attribute 21
601 ; CORTEX-A12-NOFPU-FAST-NOT: .eabi_attribute 22
602 ; CORTEX-A12-NOFPU-FAST: .eabi_attribute 23, 1
604 ; CORTEX-A15: .cpu cortex-a15
605 ; CORTEX-A15: .eabi_attribute 6, 10
606 ; CORTEX-A15: .eabi_attribute 7, 65
607 ; CORTEX-A15: .eabi_attribute 8, 1
608 ; CORTEX-A15: .eabi_attribute 9, 2
609 ; CORTEX-A15: .fpu neon-vfpv4
610 ; CORTEX-A15-NOT: .eabi_attribute 19
611 ;; We default to IEEE 754 compliance
612 ; CORTEX-A15: .eabi_attribute 20, 1
613 ; CORTEX-A15: .eabi_attribute 21, 1
614 ; CORTEX-A15-NOT: .eabi_attribute 22
615 ; CORTEX-A15: .eabi_attribute 23, 3
616 ; CORTEX-A15: .eabi_attribute 24, 1
617 ; CORTEX-A15: .eabi_attribute 25, 1
618 ; CORTEX-A15-NOT: .eabi_attribute 27
619 ; CORTEX-A15-NOT: .eabi_attribute 28
620 ; CORTEX-A15: .eabi_attribute 36, 1
621 ; CORTEX-A15: .eabi_attribute 38, 1
622 ; CORTEX-A15: .eabi_attribute 42, 1
623 ; CORTEX-A15: .eabi_attribute 44, 2
624 ; CORTEX-A15: .eabi_attribute 68, 3
626 ; CORTEX-A15-FAST-NOT: .eabi_attribute 19
627 ;; The A15 defaults to a VFPv3 FPU, so it flushes preseving sign when
628 ;; -ffast-math is specified.
629 ; CORTEX-A15-FAST: .eabi_attribute 20, 2
630 ; CORTEX-A15-FAST-NOT: .eabi_attribute 21
631 ; CORTEX-A15-FAST-NOT: .eabi_attribute 22
632 ; CORTEX-A15-FAST: .eabi_attribute 23, 1
634 ; CORTEX-A17-DEFAULT: .cpu cortex-a17
635 ; CORTEX-A17-DEFAULT: .eabi_attribute 6, 10
636 ; CORTEX-A17-DEFAULT: .eabi_attribute 7, 65
637 ; CORTEX-A17-DEFAULT: .eabi_attribute 8, 1
638 ; CORTEX-A17-DEFAULT: .eabi_attribute 9, 2
639 ; CORTEX-A17-DEFAULT: .fpu neon-vfpv4
640 ; CORTEX-A17-DEFAULT-NOT: .eabi_attribute 19
641 ;; We default to IEEE 754 compliance
642 ; CORTEX-A17-DEFAULT: .eabi_attribute 20, 1
643 ; CORTEX-A17-DEFAULT: .eabi_attribute 21, 1
644 ; CORTEX-A17-DEFAULT-NOT: .eabi_attribute 22
645 ; CORTEX-A17-DEFAULT: .eabi_attribute 23, 3
646 ; CORTEX-A17-DEFAULT: .eabi_attribute 24, 1
647 ; CORTEX-A17-DEFAULT: .eabi_attribute 25, 1
648 ; CORTEX-A17-DEFAULT: .eabi_attribute 42, 1
649 ; CORTEX-A17-DEFAULT: .eabi_attribute 44, 2
650 ; CORTEX-A17-DEFAULT: .eabi_attribute 68, 3
652 ; CORTEX-A17-FAST-NOT: .eabi_attribute 19
653 ;; The A17 defaults to a VFPv3 FPU, so it flushes preseving sign when
654 ;; -ffast-math is specified.
655 ; CORTEX-A17-FAST: .eabi_attribute 20, 2
656 ; CORTEX-A17-FAST-NOT: .eabi_attribute 21
657 ; CORTEX-A17-FAST-NOT: .eabi_attribute 22
658 ; CORTEX-A17-FAST: .eabi_attribute 23, 1
660 ; CORTEX-A17-NOFPU: .cpu cortex-a17
661 ; CORTEX-A17-NOFPU: .eabi_attribute 6, 10
662 ; CORTEX-A17-NOFPU: .eabi_attribute 7, 65
663 ; CORTEX-A17-NOFPU: .eabi_attribute 8, 1
664 ; CORTEX-A17-NOFPU: .eabi_attribute 9, 2
665 ; CORTEX-A17-NOFPU-NOT: .fpu
666 ; CORTEX-A17-NOFPU-NOT: .eabi_attribute 19
667 ;; We default to IEEE 754 compliance
668 ; CORTEX-A17-NOFPU: .eabi_attribute 20, 1
669 ; CORTEX-A17-NOFPU: .eabi_attribute 21, 1
670 ; CORTEX-A17-NOFPU-NOT: .eabi_attribute 22
671 ; CORTEX-A17-NOFPU: .eabi_attribute 23, 3
672 ; CORTEX-A17-NOFPU: .eabi_attribute 24, 1
673 ; CORTEX-A17-NOFPU: .eabi_attribute 25, 1
674 ; CORTEX-A17-NOFPU: .eabi_attribute 42, 1
675 ; CORTEX-A17-NOFPU: .eabi_attribute 44, 2
676 ; CORTEX-A17-NOFPU: .eabi_attribute 68, 3
678 ; CORTEX-A17-NOFPU-NOT: .eabi_attribute 19
679 ;; Despite there being no FPU, we chose to flush to zero preserving
680 ;; sign. This matches what the hardware would do for this architecture
682 ; CORTEX-A17-NOFPU-FAST: .eabi_attribute 20, 2
683 ; CORTEX-A17-NOFPU-FAST-NOT: .eabi_attribute 21
684 ; CORTEX-A17-NOFPU-FAST-NOT: .eabi_attribute 22
685 ; CORTEX-A17-NOFPU-FAST: .eabi_attribute 23, 1
687 ; CORTEX-M0: .cpu cortex-m0
688 ; CORTEX-M0: .eabi_attribute 6, 12
689 ; CORTEX-M0-NOT: .eabi_attribute 7
690 ; CORTEX-M0: .eabi_attribute 8, 0
691 ; CORTEX-M0: .eabi_attribute 9, 1
692 ; CORTEX-M0-NOT: .eabi_attribute 19
693 ;; We default to IEEE 754 compliance
694 ; CORTEX-M0: .eabi_attribute 20, 1
695 ; CORTEX-M0: .eabi_attribute 21, 1
696 ; CORTEX-M0-NOT: .eabi_attribute 22
697 ; CORTEX-M0: .eabi_attribute 23, 3
698 ; CORTEX-M0: .eabi_attribute 24, 1
699 ; CORTEX-M0: .eabi_attribute 25, 1
700 ; CORTEX-M0-NOT: .eabi_attribute 27
701 ; CORTEX-M0-NOT: .eabi_attribute 28
702 ; CORTEX-M0-NOT: .eabi_attribute 36
703 ; CORTEX-M0: .eabi_attribute 38, 1
704 ; CORTEX-M0-NOT: .eabi_attribute 42
705 ; CORTEX-M0-NOT: .eabi_attribute 68
707 ; CORTEX-M0-FAST-NOT: .eabi_attribute 19
708 ;; Despite the M0 CPU having no FPU in this scenario, we chose to
709 ;; flush to positive zero here. There's no hardware support doing
710 ;; this, but the fast maths software library might and such behaviour
711 ;; would match hardware support on this architecture revision if it
713 ; CORTEX-M0-FAST-NOT: .eabi_attribute 20
714 ; CORTEX-M0-FAST-NOT: .eabi_attribute 21
715 ; CORTEX-M0-FAST-NOT: .eabi_attribute 22
716 ; CORTEX-M0-FAST: .eabi_attribute 23, 1
718 ; CORTEX-M3: .cpu cortex-m3
719 ; CORTEX-M3: .eabi_attribute 6, 10
720 ; CORTEX-M3: .eabi_attribute 7, 77
721 ; CORTEX-M3: .eabi_attribute 8, 0
722 ; CORTEX-M3: .eabi_attribute 9, 2
723 ; CORTEX-M3-NOT: .eabi_attribute 19
724 ;; We default to IEEE 754 compliance
725 ; CORTEX-M3: .eabi_attribute 20, 1
726 ; CORTEX-M3: .eabi_attribute 21, 1
727 ; CORTEX-M3-NOT: .eabi_attribute 22
728 ; CORTEX-M3: .eabi_attribute 23, 3
729 ; CORTEX-M3: .eabi_attribute 24, 1
730 ; CORTEX-M3: .eabi_attribute 25, 1
731 ; CORTEX-M3-NOT: .eabi_attribute 27
732 ; CORTEX-M3-NOT: .eabi_attribute 28
733 ; CORTEX-M3-NOT: .eabi_attribute 36
734 ; CORTEX-M3: .eabi_attribute 38, 1
735 ; CORTEX-M3-NOT: .eabi_attribute 42
736 ; CORTEX-M3-NOT: .eabi_attribute 44
737 ; CORTEX-M3-NOT: .eabi_attribute 68
739 ; CORTEX-M3-FAST-NOT: .eabi_attribute 19
740 ;; Despite there being no FPU, we chose to flush to zero preserving
741 ;; sign. This matches what the hardware would do for this architecture
743 ; CORTEX-M3-FAST: .eabi_attribute 20, 2
744 ; CORTEX-M3-FAST-NOT: .eabi_attribute 21
745 ; CORTEX-M3-FAST-NOT: .eabi_attribute 22
746 ; CORTEX-M3-FAST: .eabi_attribute 23, 1
748 ; CORTEX-M4-SOFT: .cpu cortex-m4
749 ; CORTEX-M4-SOFT: .eabi_attribute 6, 13
750 ; CORTEX-M4-SOFT: .eabi_attribute 7, 77
751 ; CORTEX-M4-SOFT: .eabi_attribute 8, 0
752 ; CORTEX-M4-SOFT: .eabi_attribute 9, 2
753 ; CORTEX-M4-SOFT: .fpu vfpv4-d16
754 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 19
755 ;; We default to IEEE 754 compliance
756 ; CORTEX-M4-SOFT: .eabi_attribute 20, 1
757 ; CORTEX-M4-SOFT: .eabi_attribute 21, 1
758 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 22
759 ; CORTEX-M4-SOFT: .eabi_attribute 23, 3
760 ; CORTEX-M4-SOFT: .eabi_attribute 24, 1
761 ; CORTEX-M4-SOFT: .eabi_attribute 25, 1
762 ; CORTEX-M4-SOFT: .eabi_attribute 27, 1
763 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 28
764 ; CORTEX-M4-SOFT: .eabi_attribute 36, 1
765 ; CORTEX-M4-SOFT: .eabi_attribute 38, 1
766 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 42
767 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 44
768 ; CORTEX-M4-SOFT-NOT: .eabi_attribute 68
770 ; CORTEX-M4-SOFT-FAST-NOT: .eabi_attribute 19
771 ;; The M4 defaults to a VFPv4 FPU, so it flushes preseving sign when
772 ;; -ffast-math is specified.
773 ; CORTEX-M4-SOFT-FAST: .eabi_attribute 20, 2
774 ; CORTEX-M4-SOFT-FAST-NOT: .eabi_attribute 21
775 ; CORTEX-M4-SOFT-FAST-NOT: .eabi_attribute 22
776 ; CORTEX-M4-SOFT-FAST: .eabi_attribute 23, 1
778 ; CORTEX-M4-HARD: .cpu cortex-m4
779 ; CORTEX-M4-HARD: .eabi_attribute 6, 13
780 ; CORTEX-M4-HARD: .eabi_attribute 7, 77
781 ; CORTEX-M4-HARD: .eabi_attribute 8, 0
782 ; CORTEX-M4-HARD: .eabi_attribute 9, 2
783 ; CORTEX-M4-HARD: .fpu vfpv4-d16
784 ; CORTEX-M4-HARD-NOT: .eabi_attribute 19
785 ;; We default to IEEE 754 compliance
786 ; CORTEX-M4-HARD: .eabi_attribute 20, 1
787 ; CORTEX-M4-HARD: .eabi_attribute 21, 1
788 ; CORTEX-M4-HARD-NOT: .eabi_attribute 22
789 ; CORTEX-M4-HARD: .eabi_attribute 23, 3
790 ; CORTEX-M4-HARD: .eabi_attribute 24, 1
791 ; CORTEX-M4-HARD: .eabi_attribute 25, 1
792 ; CORTEX-M4-HARD: .eabi_attribute 27, 1
793 ; CORTEX-M4-HARD: .eabi_attribute 28, 1
794 ; CORTEX-M4-HARD: .eabi_attribute 36, 1
795 ; CORTEX-M4-HARD: .eabi_attribute 38, 1
796 ; CORTEX-M4-HARD-NOT: .eabi_attribute 42
797 ; CORTEX-M4-HARD-NOT: .eabi_attribute 44
798 ; CORTEX-M4-HARD-NOT: .eabi_attribute 68
800 ; CORTEX-M4-HARD-FAST-NOT: .eabi_attribute 19
801 ;; The M4 defaults to a VFPv4 FPU, so it flushes preseving sign when
802 ;; -ffast-math is specified.
803 ; CORTEX-M4-HARD-FAST: .eabi_attribute 20, 2
804 ; CORTEX-M4-HARD-FAST-NOT: .eabi_attribute 21
805 ; CORTEX-M4-HARD-FAST-NOT: .eabi_attribute 22
806 ; CORTEX-M4-HARD-FAST: .eabi_attribute 23, 1
808 ; CORTEX-M7: .cpu cortex-m7
809 ; CORTEX-M7: .eabi_attribute 6, 13
810 ; CORTEX-M7: .eabi_attribute 7, 77
811 ; CORTEX-M7: .eabi_attribute 8, 0
812 ; CORTEX-M7: .eabi_attribute 9, 2
813 ; CORTEX-M7-SOFT-NOT: .fpu
814 ; CORTEX-M7-SINGLE: .fpu fpv5-d16
815 ; CORTEX-M7-DOUBLE: .fpu fpv5-d16
816 ; CORTEX-M7: .eabi_attribute 17, 1
817 ; CORTEX-M7-NOT: .eabi_attribute 19
818 ;; We default to IEEE 754 compliance
819 ; CORTEX-M7: .eabi_attribute 20, 1
820 ; CORTEX-M7: .eabi_attribute 21, 1
821 ; CORTEX-M7-NOT: .eabi_attribute 22
822 ; CORTEX-M7: .eabi_attribute 23, 3
823 ; CORTEX-M7: .eabi_attribute 24, 1
824 ; CORTEX-M7: .eabi_attribute 25, 1
825 ; CORTEX-M7-SOFT-NOT: .eabi_attribute 27
826 ; CORTEX-M7-SINGLE: .eabi_attribute 27, 1
827 ; CORTEX-M7-DOUBLE-NOT: .eabi_attribute 27
828 ; CORTEX-M7: .eabi_attribute 36, 1
829 ; CORTEX-M7: .eabi_attribute 38, 1
830 ; CORTEX-M7: .eabi_attribute 14, 0
832 ; CORTEX-M7-NOFPU-FAST-NOT: .eabi_attribute 19
833 ;; The M7 has the ARMv8 FP unit, which always flushes preserving sign.
834 ; CORTEX-M7-FAST: .eabi_attribute 20, 2
835 ;; Despite there being no FPU, we chose to flush to zero preserving
836 ;; sign. This matches what the hardware would do for this architecture
838 ; CORTEX-M7-NOFPU-FAST: .eabi_attribute 20, 2
839 ; CORTEX-M7-NOFPU-FAST-NOT: .eabi_attribute 21
840 ; CORTEX-M7-NOFPU-FAST-NOT: .eabi_attribute 22
841 ; CORTEX-M7-NOFPU-FAST: .eabi_attribute 23, 1
843 ; CORTEX-R5: .cpu cortex-r5
844 ; CORTEX-R5: .eabi_attribute 6, 10
845 ; CORTEX-R5: .eabi_attribute 7, 82
846 ; CORTEX-R5: .eabi_attribute 8, 1
847 ; CORTEX-R5: .eabi_attribute 9, 2
848 ; CORTEX-R5: .fpu vfpv3-d16
849 ; CORTEX-R5-NOT: .eabi_attribute 19
850 ;; We default to IEEE 754 compliance
851 ; CORTEX-R5: .eabi_attribute 20, 1
852 ; CORTEX-R5: .eabi_attribute 21, 1
853 ; CORTEX-R5-NOT: .eabi_attribute 22
854 ; CORTEX-R5: .eabi_attribute 23, 3
855 ; CORTEX-R5: .eabi_attribute 24, 1
856 ; CORTEX-R5: .eabi_attribute 25, 1
857 ; CORTEX-R5: .eabi_attribute 27, 1
858 ; CORTEX-R5-NOT: .eabi_attribute 28
859 ; CORTEX-R5-NOT: .eabi_attribute 36
860 ; CORTEX-R5: .eabi_attribute 38, 1
861 ; CORTEX-R5-NOT: .eabi_attribute 42
862 ; CORTEX-R5: .eabi_attribute 44, 2
863 ; CORTEX-R5-NOT: .eabi_attribute 68
865 ; CORTEX-R5-FAST-NOT: .eabi_attribute 19
866 ;; The R5 has the VFPv3 FP unit, which always flushes preserving sign.
867 ; CORTEX-R5-FAST: .eabi_attribute 20, 2
868 ; CORTEX-R5-FAST-NOT: .eabi_attribute 21
869 ; CORTEX-R5-FAST-NOT: .eabi_attribute 22
870 ; CORTEX-R5-FAST: .eabi_attribute 23, 1
872 ; CORTEX-A53: .cpu cortex-a53
873 ; CORTEX-A53: .eabi_attribute 6, 14
874 ; CORTEX-A53: .eabi_attribute 7, 65
875 ; CORTEX-A53: .eabi_attribute 8, 1
876 ; CORTEX-A53: .eabi_attribute 9, 2
877 ; CORTEX-A53: .fpu crypto-neon-fp-armv8
878 ; CORTEX-A53: .eabi_attribute 12, 3
879 ; CORTEX-A53-NOT: .eabi_attribute 19
880 ;; We default to IEEE 754 compliance
881 ; CORTEX-A53: .eabi_attribute 20, 1
882 ; CORTEX-A53: .eabi_attribute 21, 1
883 ; CORTEX-A53-NOT: .eabi_attribute 22
884 ; CORTEX-A53: .eabi_attribute 23, 3
885 ; CORTEX-A53: .eabi_attribute 24, 1
886 ; CORTEX-A53: .eabi_attribute 25, 1
887 ; CORTEX-A53-NOT: .eabi_attribute 27
888 ; CORTEX-A53-NOT: .eabi_attribute 28
889 ; CORTEX-A53: .eabi_attribute 36, 1
890 ; CORTEX-A53: .eabi_attribute 38, 1
891 ; CORTEX-A53: .eabi_attribute 42, 1
892 ; CORTEX-A53-NOT: .eabi_attribute 44
893 ; CORTEX-A53: .eabi_attribute 68, 3
895 ; CORTEX-A53-FAST-NOT: .eabi_attribute 19
896 ;; The A53 has the ARMv8 FP unit, which always flushes preserving sign.
897 ; CORTEX-A53-FAST: .eabi_attribute 20, 2
898 ; CORTEX-A53-FAST-NOT: .eabi_attribute 21
899 ; CORTEX-A53-FAST-NOT: .eabi_attribute 22
900 ; CORTEX-A53-FAST: .eabi_attribute 23, 1
902 ; CORTEX-A57: .cpu cortex-a57
903 ; CORTEX-A57: .eabi_attribute 6, 14
904 ; CORTEX-A57: .eabi_attribute 7, 65
905 ; CORTEX-A57: .eabi_attribute 8, 1
906 ; CORTEX-A57: .eabi_attribute 9, 2
907 ; CORTEX-A57: .fpu crypto-neon-fp-armv8
908 ; CORTEX-A57: .eabi_attribute 12, 3
909 ; CORTEX-A57-NOT: .eabi_attribute 19
910 ;; We default to IEEE 754 compliance
911 ; CORTEX-A57: .eabi_attribute 20, 1
912 ; CORTEX-A57: .eabi_attribute 21, 1
913 ; CORTEX-A57-NOT: .eabi_attribute 22
914 ; CORTEX-A57: .eabi_attribute 23, 3
915 ; CORTEX-A57: .eabi_attribute 24, 1
916 ; CORTEX-A57: .eabi_attribute 25, 1
917 ; CORTEX-A57-NOT: .eabi_attribute 27
918 ; CORTEX-A57-NOT: .eabi_attribute 28
919 ; CORTEX-A57: .eabi_attribute 36, 1
920 ; CORTEX-A57: .eabi_attribute 38, 1
921 ; CORTEX-A57: .eabi_attribute 42, 1
922 ; CORTEX-A57-NOT: .eabi_attribute 44
923 ; CORTEX-A57: .eabi_attribute 68, 3
925 ; CORTEX-A57-FAST-NOT: .eabi_attribute 19
926 ;; The A57 has the ARMv8 FP unit, which always flushes preserving sign.
927 ; CORTEX-A57-FAST: .eabi_attribute 20, 2
928 ; CORTEX-A57-FAST-NOT: .eabi_attribute 21
929 ; CORTEX-A57-FAST-NOT: .eabi_attribute 22
930 ; CORTEX-A57-FAST: .eabi_attribute 23, 1
932 ; RELOC-PIC: .eabi_attribute 15, 1
933 ; RELOC-PIC: .eabi_attribute 16, 1
934 ; RELOC-PIC: .eabi_attribute 17, 2
935 ; RELOC-OTHER: .eabi_attribute 17, 1
937 ; PCS-R9-USE: .eabi_attribute 14, 0
938 ; PCS-R9-RESERVE: .eabi_attribute 14, 3
940 define i32 @f(i64 %z) {