1 ; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
3 define i64 @test1(i64* %ptr, i64 %val) {
6 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
7 ; CHECK: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
8 ; CHECK: adc [[REG4:(r[0-9]?[13579])]], [[REG2]]
9 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
13 %r = atomicrmw add i64* %ptr, i64 %val seq_cst
17 define i64 @test2(i64* %ptr, i64 %val) {
20 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
21 ; CHECK: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
22 ; CHECK: sbc [[REG4:(r[0-9]?[13579])]], [[REG2]]
23 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
27 %r = atomicrmw sub i64* %ptr, i64 %val seq_cst
31 define i64 @test3(i64* %ptr, i64 %val) {
34 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
35 ; CHECK: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
36 ; CHECK: and [[REG4:(r[0-9]?[13579])]], [[REG2]]
37 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
41 %r = atomicrmw and i64* %ptr, i64 %val seq_cst
45 define i64 @test4(i64* %ptr, i64 %val) {
48 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
49 ; CHECK: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
50 ; CHECK: orr [[REG4:(r[0-9]?[13579])]], [[REG2]]
51 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
55 %r = atomicrmw or i64* %ptr, i64 %val seq_cst
59 define i64 @test5(i64* %ptr, i64 %val) {
62 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
63 ; CHECK: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
64 ; CHECK: eor [[REG4:(r[0-9]?[13579])]], [[REG2]]
65 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
69 %r = atomicrmw xor i64* %ptr, i64 %val seq_cst
73 define i64 @test6(i64* %ptr, i64 %val) {
76 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
77 ; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
81 %r = atomicrmw xchg i64* %ptr, i64 %val seq_cst
85 define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
88 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
90 ; CHECK: cmpeq [[REG2]]
92 ; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
96 %r = cmpxchg i64* %ptr, i64 %val1, i64 %val2 seq_cst
100 ; Compiles down to cmpxchg
101 ; FIXME: Should compile to a single ldrexd
102 define i64 @test8(i64* %ptr) {
104 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
105 ; CHECK: cmp [[REG1]]
106 ; CHECK: cmpeq [[REG2]]
108 ; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
112 %r = load atomic i64* %ptr seq_cst, align 8
116 ; Compiles down to atomicrmw xchg; there really isn't any more efficient
118 define void @test9(i64* %ptr, i64 %val) {
121 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
122 ; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
126 store atomic i64 %val, i64* %ptr seq_cst, align 8
130 define i64 @test10(i64* %ptr, i64 %val) {
133 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
134 ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
135 ; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
137 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
141 %r = atomicrmw min i64* %ptr, i64 %val seq_cst
145 define i64 @test11(i64* %ptr, i64 %val) {
148 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
149 ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
150 ; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
152 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
156 %r = atomicrmw umin i64* %ptr, i64 %val seq_cst
160 define i64 @test12(i64* %ptr, i64 %val) {
163 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
164 ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
165 ; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
167 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
171 %r = atomicrmw max i64* %ptr, i64 %val seq_cst
175 define i64 @test13(i64* %ptr, i64 %val) {
178 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
179 ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
180 ; CHECK: sbcs {{[a-z0-9]+}}, [[REG2]], [[REG4:(r[0-9]?[13579])]]
182 ; CHECK: strexd {{[a-z0-9]+}}, [[REG3]], [[REG4]]
186 %r = atomicrmw umax i64* %ptr, i64 %val seq_cst