1 ; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=NO-REALIGN
2 ; RUN: llc < %s -mtriple=armv7-apple-ios -O0 | FileCheck %s -check-prefix=REALIGN
5 ; When realign-stack is set to false, make sure we are not creating stack
6 ; objects that are assumed to be 64-byte aligned.
7 @T3_retval = common global <16 x float> zeroinitializer, align 16
9 define void @test1(<16 x float>* noalias sret %agg.result) nounwind ssp "no-realign-stack" {
11 ; NO-REALIGN-LABEL: test1
12 ; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128]
13 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
14 ; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
15 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
16 ; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
17 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #48
18 ; NO-REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
20 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1:[0-9]+]], #48
21 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
22 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
23 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
24 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
25 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
26 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
28 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0:0]], #48
29 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
30 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R0]], #32
31 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
32 ; NO-REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
33 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
34 ; NO-REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
35 %retval = alloca <16 x float>, align 16
36 %0 = load <16 x float>* @T3_retval, align 16
37 store <16 x float> %0, <16 x float>* %retval
38 %1 = load <16 x float>* %retval
39 store <16 x float> %1, <16 x float>* %agg.result, align 16
43 define void @test2(<16 x float>* noalias sret %agg.result) nounwind ssp {
45 ; REALIGN-LABEL: test2
46 ; REALIGN: bic sp, sp, #63
47 ; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1:[0-9]+]]:128]
48 ; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #16
49 ; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
50 ; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #32
51 ; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
52 ; REALIGN: add r[[R2:[0-9]+]], r[[R1]], #48
53 ; REALIGN: vld1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
56 ; REALIGN: orr r[[R2:[0-9]+]], r[[R1:[0-9]+]], #48
57 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
58 ; REALIGN: orr r[[R2:[0-9]+]], r[[R1]], #32
59 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
60 ; REALIGN: orr r[[R2:[0-9]+]], r[[R1]], #16
61 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R2]]:128]
62 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
64 ; REALIGN: add r[[R1:[0-9]+]], r[[R0:0]], #48
65 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
66 ; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #32
67 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
68 ; REALIGN: add r[[R1:[0-9]+]], r[[R0]], #16
69 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R1]]:128]
70 ; REALIGN: vst1.64 {{{d[0-9]+, d[0-9]+}}}, [r[[R0]]:128]
71 %retval = alloca <16 x float>, align 16
72 %0 = load <16 x float>* @T3_retval, align 16
73 store <16 x float> %0, <16 x float>* %retval
74 %1 = load <16 x float>* %retval
75 store <16 x float> %1, <16 x float>* %agg.result, align 16