ARM pop of a single register encodes as post-indexed LDR.

[oota-llvm.git] / test / CodeGen / ARM / 2009-07-09-asm-p-constraint.ll

; RUN: llc < %s -march=arm -mattr=+v6

define void @test(i8* %x) nounwind {
entry:
        call void asm sideeffect "pld\09${0:a}", "r,~{cc}"(i8* %x) nounwind
        ret void
}