1 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
2 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
4 declare i32 @llvm.r600.read.tidig.x() #0
5 declare i32 @llvm.r600.read.tidig.y() #0
7 ; In this test both the pointer and the offset operands to the
8 ; BUFFER_LOAD instructions end up being stored in vgprs. This
9 ; requires us to add the pointer and offset together, store the
10 ; result in the offset operand (vaddr), and then store 0 in an
11 ; sgpr register pair and use that for the pointer operand
12 ; (low 64-bits of srsrc).
14 ; GCN-LABEL: {{^}}mubuf:
16 ; Make sure we aren't using VGPRs for the source operand of s_mov_b64
17 ; GCN-NOT: s_mov_b64 s[{{[0-9]+:[0-9]+}}], v
19 ; Make sure we aren't using VGPR's for the srsrc operand of BUFFER_LOAD_*
21 ; GCN: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
22 ; GCN: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
24 define void @mubuf(i32 addrspace(1)* %out, i8 addrspace(1)* %in) #1 {
26 %tmp = call i32 @llvm.r600.read.tidig.x()
27 %tmp1 = call i32 @llvm.r600.read.tidig.y()
28 %tmp2 = sext i32 %tmp to i64
29 %tmp3 = sext i32 %tmp1 to i64
32 loop: ; preds = %loop, %entry
33 %tmp4 = phi i64 [ 0, %entry ], [ %tmp5, %loop ]
34 %tmp5 = add i64 %tmp2, %tmp4
35 %tmp6 = getelementptr i8, i8 addrspace(1)* %in, i64 %tmp5
36 %tmp7 = load i8, i8 addrspace(1)* %tmp6, align 1
37 %tmp8 = or i64 %tmp5, 1
38 %tmp9 = getelementptr i8, i8 addrspace(1)* %in, i64 %tmp8
39 %tmp10 = load i8, i8 addrspace(1)* %tmp9, align 1
40 %tmp11 = add i8 %tmp7, %tmp10
41 %tmp12 = sext i8 %tmp11 to i32
42 store i32 %tmp12, i32 addrspace(1)* %out
43 %tmp13 = icmp slt i64 %tmp5, 10
44 br i1 %tmp13, label %loop, label %done
50 ; Test moving an SMRD instruction to the VALU
52 ; GCN-LABEL: {{^}}smrd_valu:
53 ; GCN: buffer_load_dword [[OUT:v[0-9]+]]
54 ; GCN: buffer_store_dword [[OUT]]
55 define void @smrd_valu(i32 addrspace(2)* addrspace(1)* %in, i32 %a, i32 %b, i32 addrspace(1)* %out) #1 {
57 %tmp = icmp ne i32 %a, 0
58 br i1 %tmp, label %if, label %else
61 %tmp1 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %in
64 else: ; preds = %entry
65 %tmp2 = getelementptr i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %in
66 %tmp3 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %tmp2
69 endif: ; preds = %else, %if
70 %tmp4 = phi i32 addrspace(2)* [ %tmp1, %if ], [ %tmp3, %else ]
71 %tmp5 = getelementptr i32, i32 addrspace(2)* %tmp4, i32 3000
72 %tmp6 = load i32, i32 addrspace(2)* %tmp5
73 store i32 %tmp6, i32 addrspace(1)* %out
77 ; Test moving an SMRD with an immediate offset to the VALU
79 ; GCN-LABEL: {{^}}smrd_valu2:
80 ; GCN: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
81 define void @smrd_valu2(i32 addrspace(1)* %out, [8 x i32] addrspace(2)* %in) #1 {
83 %tmp = call i32 @llvm.r600.read.tidig.x() #0
84 %tmp1 = add i32 %tmp, 4
85 %tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(2)* %in, i32 %tmp, i32 4
86 %tmp3 = load i32, i32 addrspace(2)* %tmp2
87 store i32 %tmp3, i32 addrspace(1)* %out
91 ; Use a big offset that will use the SMRD literal offset on CI
92 ; GCN-LABEL: {{^}}smrd_valu_ci_offset:
93 ; GCN: s_movk_i32 s[[OFFSET:[0-9]+]], 0x4e20{{$}}
94 ; GCN: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[OFFSET]]:{{[0-9]+}}], 0 addr64{{$}}
96 ; GCN: buffer_store_dword
97 define void @smrd_valu_ci_offset(i32 addrspace(1)* %out, i32 addrspace(2)* %in, i32 %c) #1 {
99 %tmp = call i32 @llvm.r600.read.tidig.x() #0
100 %tmp2 = getelementptr i32, i32 addrspace(2)* %in, i32 %tmp
101 %tmp3 = getelementptr i32, i32 addrspace(2)* %tmp2, i32 5000
102 %tmp4 = load i32, i32 addrspace(2)* %tmp3
103 %tmp5 = add i32 %tmp4, %c
104 store i32 %tmp5, i32 addrspace(1)* %out
108 ; GCN-LABEL: {{^}}smrd_valu_ci_offset_x2:
109 ; GCN: s_mov_b32 s[[OFFSET:[0-9]+]], 0x9c40{{$}}
110 ; GCN: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[OFFSET]]:{{[0-9]+}}], 0 addr64{{$}}
111 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
112 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
113 ; GCN: buffer_store_dwordx2
114 define void @smrd_valu_ci_offset_x2(i64 addrspace(1)* %out, i64 addrspace(2)* %in, i64 %c) #1 {
116 %tmp = call i32 @llvm.r600.read.tidig.x() #0
117 %tmp2 = getelementptr i64, i64 addrspace(2)* %in, i32 %tmp
118 %tmp3 = getelementptr i64, i64 addrspace(2)* %tmp2, i32 5000
119 %tmp4 = load i64, i64 addrspace(2)* %tmp3
120 %tmp5 = or i64 %tmp4, %c
121 store i64 %tmp5, i64 addrspace(1)* %out
125 ; GCN-LABEL: {{^}}smrd_valu_ci_offset_x4:
126 ; GCN: s_movk_i32 s[[OFFSET:[0-9]+]], 0x4d20{{$}}
127 ; GCN: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[OFFSET]]:{{[0-9]+}}], 0 addr64{{$}}
128 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
129 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
130 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
131 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
132 ; GCN: buffer_store_dwordx4
133 define void @smrd_valu_ci_offset_x4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(2)* %in, <4 x i32> %c) #1 {
135 %tmp = call i32 @llvm.r600.read.tidig.x() #0
136 %tmp2 = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %in, i32 %tmp
137 %tmp3 = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %tmp2, i32 1234
138 %tmp4 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp3
139 %tmp5 = or <4 x i32> %tmp4, %c
140 store <4 x i32> %tmp5, <4 x i32> addrspace(1)* %out
144 ; Original scalar load uses SGPR offset on SI and 32-bit literal on
147 ; GCN-LABEL: {{^}}smrd_valu_ci_offset_x8:
148 ; GCN: s_mov_b32 s[[OFFSET0:[0-9]+]], 0x9a40{{$}}
149 ; GCN: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[OFFSET0]]:{{[0-9]+}}], 0 addr64{{$}}
151 ; SI: s_add_i32 s[[OFFSET1:[0-9]+]], s[[OFFSET0]], 16
152 ; SI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[OFFSET1]]:{{[0-9]+}}], 0 addr64{{$}}
154 ; CI: s_mov_b32 s[[OFFSET1:[0-9]+]], 0x9a50{{$}}
155 ; CI: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[OFFSET1]]:{{[0-9]+}}], 0 addr64{{$}}
157 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
158 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
159 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
160 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
161 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
162 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
163 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
164 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
165 ; GCN: buffer_store_dwordx4
166 ; GCN: buffer_store_dwordx4
167 define void @smrd_valu_ci_offset_x8(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(2)* %in, <8 x i32> %c) #1 {
169 %tmp = call i32 @llvm.r600.read.tidig.x() #0
170 %tmp2 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %in, i32 %tmp
171 %tmp3 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %tmp2, i32 1234
172 %tmp4 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp3
173 %tmp5 = or <8 x i32> %tmp4, %c
174 store <8 x i32> %tmp5, <8 x i32> addrspace(1)* %out
178 ; FIXME: should use immediate offset instead of using s_add_i32 for adding to constant.
179 ; GCN-LABEL: {{^}}smrd_valu_ci_offset_x16:
181 ; GCN-DAG: s_mov_b32 s[[OFFSET0:[0-9]+]], 0x13480{{$}}
182 ; SI-DAG: s_add_i32 s[[OFFSET1:[0-9]+]], s[[OFFSET0]], 16
183 ; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[OFFSET0]]:{{[0-9]+}}], 0 addr64{{$}}
185 ; CI-DAG: s_mov_b32 s[[OFFSET1:[0-9]+]], 0x13490{{$}}
186 ; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[OFFSET1]]:{{[0-9]+}}], 0 addr64{{$}}
188 ; SI-DAG: s_add_i32 s[[OFFSET2:[0-9]+]], s[[OFFSET0]], 32
189 ; CI-DAG: s_mov_b32 s[[OFFSET2:[0-9]+]], 0x134a0
191 ; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[OFFSET2]]:{{[0-9]+}}], 0 addr64{{$}}
192 ; GCN-DAG: s_add_i32 s[[OFFSET3:[0-9]+]], s[[OFFSET2]], 16
193 ; GCN-DAG: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[OFFSET3]]:{{[0-9]+}}], 0 addr64{{$}}
195 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
196 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
197 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
198 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
199 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
200 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
201 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
202 ; GCN: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
203 ; GCN: buffer_store_dwordx4
204 ; GCN: buffer_store_dwordx4
205 ; GCN: buffer_store_dwordx4
206 ; GCN: buffer_store_dwordx4
209 define void @smrd_valu_ci_offset_x16(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(2)* %in, <16 x i32> %c) #1 {
211 %tmp = call i32 @llvm.r600.read.tidig.x() #0
212 %tmp2 = getelementptr <16 x i32>, <16 x i32> addrspace(2)* %in, i32 %tmp
213 %tmp3 = getelementptr <16 x i32>, <16 x i32> addrspace(2)* %tmp2, i32 1234
214 %tmp4 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp3
215 %tmp5 = or <16 x i32> %tmp4, %c
216 store <16 x i32> %tmp5, <16 x i32> addrspace(1)* %out
220 ; GCN-LABEL: {{^}}smrd_valu2_salu_user:
221 ; GCN: buffer_load_dword [[MOVED:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
222 ; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, s{{[0-9]+}}, [[MOVED]]
223 ; GCN: buffer_store_dword [[ADD]]
224 define void @smrd_valu2_salu_user(i32 addrspace(1)* %out, [8 x i32] addrspace(2)* %in, i32 %a) #1 {
226 %tmp = call i32 @llvm.r600.read.tidig.x() #0
227 %tmp1 = add i32 %tmp, 4
228 %tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(2)* %in, i32 %tmp, i32 4
229 %tmp3 = load i32, i32 addrspace(2)* %tmp2
230 %tmp4 = add i32 %tmp3, %a
231 store i32 %tmp4, i32 addrspace(1)* %out
235 ; GCN-LABEL: {{^}}smrd_valu2_max_smrd_offset:
236 ; GCN: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1020{{$}}
237 define void @smrd_valu2_max_smrd_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(2)* %in) #1 {
239 %tmp = call i32 @llvm.r600.read.tidig.x() #0
240 %tmp1 = add i32 %tmp, 4
241 %tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(2)* %in, i32 %tmp, i32 255
242 %tmp3 = load i32, i32 addrspace(2)* %tmp2
243 store i32 %tmp3, i32 addrspace(1)* %out
247 ; Offset is too big to fit in SMRD 8-bit offset, but small enough to
248 ; fit in MUBUF offset.
249 ; FIXME: We should be using the offset but we don't
251 ; GCN-LABEL: {{^}}smrd_valu2_mubuf_offset:
252 ; SI: s_movk_i32 s[[OFFSET:[0-9]+]], 0x400{{$}}
253 ; SI: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[OFFSET]]:{{[0-9]+\]}}, 0 addr64{{$}}
255 ; CI: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1024{{$}}
256 define void @smrd_valu2_mubuf_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(2)* %in) #1 {
258 %tmp = call i32 @llvm.r600.read.tidig.x() #0
259 %tmp1 = add i32 %tmp, 4
260 %tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(2)* %in, i32 %tmp, i32 256
261 %tmp3 = load i32, i32 addrspace(2)* %tmp2
262 store i32 %tmp3, i32 addrspace(1)* %out
266 ; GCN-LABEL: {{^}}s_load_imm_v8i32:
267 ; GCN: buffer_load_dwordx4
268 ; GCN: buffer_load_dwordx4
269 define void @s_load_imm_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 {
271 %tmp0 = tail call i32 @llvm.r600.read.tidig.x()
272 %tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
273 %tmp2 = bitcast i32 addrspace(2)* %tmp1 to <8 x i32> addrspace(2)*
274 %tmp3 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp2, align 4
275 store <8 x i32> %tmp3, <8 x i32> addrspace(1)* %out, align 32
279 ; GCN-LABEL: {{^}}s_load_imm_v8i32_salu_user:
280 ; GCN: buffer_load_dwordx4
281 ; GCN: buffer_load_dwordx4
289 ; GCN: buffer_store_dword
290 define void @s_load_imm_v8i32_salu_user(i32 addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 {
292 %tmp0 = tail call i32 @llvm.r600.read.tidig.x()
293 %tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
294 %tmp2 = bitcast i32 addrspace(2)* %tmp1 to <8 x i32> addrspace(2)*
295 %tmp3 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp2, align 4
297 %elt0 = extractelement <8 x i32> %tmp3, i32 0
298 %elt1 = extractelement <8 x i32> %tmp3, i32 1
299 %elt2 = extractelement <8 x i32> %tmp3, i32 2
300 %elt3 = extractelement <8 x i32> %tmp3, i32 3
301 %elt4 = extractelement <8 x i32> %tmp3, i32 4
302 %elt5 = extractelement <8 x i32> %tmp3, i32 5
303 %elt6 = extractelement <8 x i32> %tmp3, i32 6
304 %elt7 = extractelement <8 x i32> %tmp3, i32 7
306 %add0 = add i32 %elt0, %elt1
307 %add1 = add i32 %add0, %elt2
308 %add2 = add i32 %add1, %elt3
309 %add3 = add i32 %add2, %elt4
310 %add4 = add i32 %add3, %elt5
311 %add5 = add i32 %add4, %elt6
312 %add6 = add i32 %add5, %elt7
314 store i32 %add6, i32 addrspace(1)* %out
318 ; GCN-LABEL: {{^}}s_load_imm_v16i32:
319 ; GCN: buffer_load_dwordx4
320 ; GCN: buffer_load_dwordx4
321 ; GCN: buffer_load_dwordx4
322 ; GCN: buffer_load_dwordx4
323 define void @s_load_imm_v16i32(<16 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 {
325 %tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1
326 %tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
327 %tmp2 = bitcast i32 addrspace(2)* %tmp1 to <16 x i32> addrspace(2)*
328 %tmp3 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp2, align 4
329 store <16 x i32> %tmp3, <16 x i32> addrspace(1)* %out, align 32
333 ; GCN-LABEL: {{^}}s_load_imm_v16i32_salu_user:
334 ; GCN: buffer_load_dwordx4
335 ; GCN: buffer_load_dwordx4
336 ; GCN: buffer_load_dwordx4
337 ; GCN: buffer_load_dwordx4
353 ; GCN: buffer_store_dword
354 define void @s_load_imm_v16i32_salu_user(i32 addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 {
356 %tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1
357 %tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
358 %tmp2 = bitcast i32 addrspace(2)* %tmp1 to <16 x i32> addrspace(2)*
359 %tmp3 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp2, align 4
361 %elt0 = extractelement <16 x i32> %tmp3, i32 0
362 %elt1 = extractelement <16 x i32> %tmp3, i32 1
363 %elt2 = extractelement <16 x i32> %tmp3, i32 2
364 %elt3 = extractelement <16 x i32> %tmp3, i32 3
365 %elt4 = extractelement <16 x i32> %tmp3, i32 4
366 %elt5 = extractelement <16 x i32> %tmp3, i32 5
367 %elt6 = extractelement <16 x i32> %tmp3, i32 6
368 %elt7 = extractelement <16 x i32> %tmp3, i32 7
369 %elt8 = extractelement <16 x i32> %tmp3, i32 8
370 %elt9 = extractelement <16 x i32> %tmp3, i32 9
371 %elt10 = extractelement <16 x i32> %tmp3, i32 10
372 %elt11 = extractelement <16 x i32> %tmp3, i32 11
373 %elt12 = extractelement <16 x i32> %tmp3, i32 12
374 %elt13 = extractelement <16 x i32> %tmp3, i32 13
375 %elt14 = extractelement <16 x i32> %tmp3, i32 14
376 %elt15 = extractelement <16 x i32> %tmp3, i32 15
378 %add0 = add i32 %elt0, %elt1
379 %add1 = add i32 %add0, %elt2
380 %add2 = add i32 %add1, %elt3
381 %add3 = add i32 %add2, %elt4
382 %add4 = add i32 %add3, %elt5
383 %add5 = add i32 %add4, %elt6
384 %add6 = add i32 %add5, %elt7
385 %add7 = add i32 %add6, %elt8
386 %add8 = add i32 %add7, %elt9
387 %add9 = add i32 %add8, %elt10
388 %add10 = add i32 %add9, %elt11
389 %add11 = add i32 %add10, %elt12
390 %add12 = add i32 %add11, %elt13
391 %add13 = add i32 %add12, %elt14
392 %add14 = add i32 %add13, %elt15
394 store i32 %add14, i32 addrspace(1)* %out
398 attributes #0 = { nounwind readnone }
399 attributes #1 = { nounwind }