1 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
3 declare i32 @llvm.r600.read.tidig.x() #0
4 declare i32 @llvm.r600.read.tidig.y() #0
6 ; In this test both the pointer and the offset operands to the
7 ; BUFFER_LOAD instructions end up being stored in vgprs. This
8 ; requires us to add the pointer and offset together, store the
9 ; result in the offset operand (vaddr), and then store 0 in an
10 ; sgpr register pair and use that for the pointer operand
11 ; (low 64-bits of srsrc).
13 ; GCN-LABEL: {{^}}mubuf:
15 ; Make sure we aren't using VGPRs for the source operand of s_mov_b64
16 ; GCN-NOT: s_mov_b64 s[{{[0-9]+:[0-9]+}}], v
18 ; Make sure we aren't using VGPR's for the srsrc operand of BUFFER_LOAD_*
20 ; GCN: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
21 ; GCN: buffer_load_ubyte v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], 0 addr64
23 define void @mubuf(i32 addrspace(1)* %out, i8 addrspace(1)* %in) #1 {
25 %tmp = call i32 @llvm.r600.read.tidig.x()
26 %tmp1 = call i32 @llvm.r600.read.tidig.y()
27 %tmp2 = sext i32 %tmp to i64
28 %tmp3 = sext i32 %tmp1 to i64
31 loop: ; preds = %loop, %entry
32 %tmp4 = phi i64 [ 0, %entry ], [ %tmp5, %loop ]
33 %tmp5 = add i64 %tmp2, %tmp4
34 %tmp6 = getelementptr i8, i8 addrspace(1)* %in, i64 %tmp5
35 %tmp7 = load i8, i8 addrspace(1)* %tmp6, align 1
36 %tmp8 = or i64 %tmp5, 1
37 %tmp9 = getelementptr i8, i8 addrspace(1)* %in, i64 %tmp8
38 %tmp10 = load i8, i8 addrspace(1)* %tmp9, align 1
39 %tmp11 = add i8 %tmp7, %tmp10
40 %tmp12 = sext i8 %tmp11 to i32
41 store i32 %tmp12, i32 addrspace(1)* %out
42 %tmp13 = icmp slt i64 %tmp5, 10
43 br i1 %tmp13, label %loop, label %done
49 ; Test moving an SMRD instruction to the VALU
51 ; GCN-LABEL: {{^}}smrd_valu:
52 ; GCN: buffer_load_dword [[OUT:v[0-9]+]]
53 ; GCN: buffer_store_dword [[OUT]]
54 define void @smrd_valu(i32 addrspace(2)* addrspace(1)* %in, i32 %a, i32 %b, i32 addrspace(1)* %out) #1 {
56 %tmp = icmp ne i32 %a, 0
57 br i1 %tmp, label %if, label %else
60 %tmp1 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %in
63 else: ; preds = %entry
64 %tmp2 = getelementptr i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %in
65 %tmp3 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %tmp2
68 endif: ; preds = %else, %if
69 %tmp4 = phi i32 addrspace(2)* [ %tmp1, %if ], [ %tmp3, %else ]
70 %tmp5 = getelementptr i32, i32 addrspace(2)* %tmp4, i32 3000
71 %tmp6 = load i32, i32 addrspace(2)* %tmp5
72 store i32 %tmp6, i32 addrspace(1)* %out
76 ; Test moving an SMRD with an immediate offset to the VALU
78 ; GCN-LABEL: {{^}}smrd_valu2:
79 ; GCN: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
80 define void @smrd_valu2(i32 addrspace(1)* %out, [8 x i32] addrspace(2)* %in) #1 {
82 %tmp = call i32 @llvm.r600.read.tidig.x() #0
83 %tmp1 = add i32 %tmp, 4
84 %tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(2)* %in, i32 %tmp, i32 4
85 %tmp3 = load i32, i32 addrspace(2)* %tmp2
86 store i32 %tmp3, i32 addrspace(1)* %out
90 ; GCN-LABEL: {{^}}smrd_valu2_max_smrd_offset:
91 ; GCN: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1020{{$}}
92 define void @smrd_valu2_max_smrd_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(2)* %in) #1 {
94 %tmp = call i32 @llvm.r600.read.tidig.x() #0
95 %tmp1 = add i32 %tmp, 4
96 %tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(2)* %in, i32 %tmp, i32 255
97 %tmp3 = load i32, i32 addrspace(2)* %tmp2
98 store i32 %tmp3, i32 addrspace(1)* %out
102 ; Offset is too big to fit in SMRD 8-bit offset, but small enough to
103 ; fit in MUBUF offset.
104 ; FIXME: We should be using the offset but we don't
106 ; GCN-LABEL: {{^}}smrd_valu2_mubuf_offset:
107 ; GCN: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
108 define void @smrd_valu2_mubuf_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(2)* %in) #1 {
110 %tmp = call i32 @llvm.r600.read.tidig.x() #0
111 %tmp1 = add i32 %tmp, 4
112 %tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(2)* %in, i32 %tmp, i32 256
113 %tmp3 = load i32, i32 addrspace(2)* %tmp2
114 store i32 %tmp3, i32 addrspace(1)* %out
118 ; GCN-LABEL: {{^}}s_load_imm_v8i32:
119 ; GCN: buffer_load_dwordx4
120 ; GCN: buffer_load_dwordx4
121 define void @s_load_imm_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 {
123 %tmp0 = tail call i32 @llvm.r600.read.tidig.x()
124 %tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
125 %tmp2 = bitcast i32 addrspace(2)* %tmp1 to <8 x i32> addrspace(2)*
126 %tmp3 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp2, align 4
127 store <8 x i32> %tmp3, <8 x i32> addrspace(1)* %out, align 32
131 ; GCN-LABEL: {{^}}s_load_imm_v16i32:
132 ; GCN: buffer_load_dwordx4
133 ; GCN: buffer_load_dwordx4
134 ; GCN: buffer_load_dwordx4
135 ; GCN: buffer_load_dwordx4
136 define void @s_load_imm_v16i32(<16 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 {
138 %tmp0 = tail call i32 @llvm.r600.read.tidig.x() #1
139 %tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0
140 %tmp2 = bitcast i32 addrspace(2)* %tmp1 to <16 x i32> addrspace(2)*
141 %tmp3 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp2, align 4
142 store <16 x i32> %tmp3, <16 x i32> addrspace(1)* %out, align 32
146 attributes #0 = { nounwind readnone }
147 attributes #1 = { nounwind }