1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s
2 ; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=SI %s
3 ; RUN: llc < %s -march=amdgcn -mcpu=bonaire -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=CI %s
5 @local_memory_two_objects.local_mem0 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
6 @local_memory_two_objects.local_mem1 = internal unnamed_addr addrspace(3) global [4 x i32] undef, align 4
9 ; Check that the LDS size emitted correctly
13 ; GCN-NEXT: .long 38792
15 ; EG: {{^}}local_memory_two_objects:
17 ; We would like to check the lds writes are using different
18 ; addresses, but due to variations in the scheduler, we can't do
19 ; this consistently on evergreen GPUs.
22 ; GCN: ds_write_b32 {{v[0-9]*}}, v[[ADDRW:[0-9]*]]
23 ; GCN-NOT: ds_write_b32 {{v[0-9]*}}, v[[ADDRW]]
25 ; GROUP_BARRIER must be the last instruction in a clause
29 ; Make sure the lds reads are using different addresses, at different
31 ; EG: LDS_READ_RET {{[*]*}} OQAP, {{PV|T}}[[ADDRR:[0-9]*\.[XYZW]]]
32 ; EG-NOT: LDS_READ_RET {{[*]*}} OQAP, T[[ADDRR]]
33 ; SI: v_add_i32_e32 [[SIPTR:v[0-9]+]], 16, v{{[0-9]+}}
34 ; SI: ds_read_b32 {{v[0-9]+}}, [[SIPTR]]
35 ; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR:v[0-9]+]] offset:16
36 ; CI: ds_read_b32 {{v[0-9]+}}, [[ADDRR]]
38 define void @local_memory_two_objects(i32 addrspace(1)* %out) {
40 %x.i = call i32 @llvm.r600.read.tidig.x() #0
41 %arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %x.i
42 store i32 %x.i, i32 addrspace(3)* %arrayidx, align 4
43 %mul = shl nsw i32 %x.i, 1
44 %arrayidx1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %x.i
45 store i32 %mul, i32 addrspace(3)* %arrayidx1, align 4
46 %sub = sub nsw i32 3, %x.i
47 call void @llvm.AMDGPU.barrier.local()
48 %arrayidx2 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem0, i32 0, i32 %sub
49 %0 = load i32, i32 addrspace(3)* %arrayidx2, align 4
50 %arrayidx3 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %x.i
51 store i32 %0, i32 addrspace(1)* %arrayidx3, align 4
52 %arrayidx4 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(3)* @local_memory_two_objects.local_mem1, i32 0, i32 %sub
53 %1 = load i32, i32 addrspace(3)* %arrayidx4, align 4
54 %add = add nsw i32 %x.i, 4
55 %arrayidx5 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %add
56 store i32 %1, i32 addrspace(1)* %arrayidx5, align 4
60 declare i32 @llvm.r600.read.tidig.x() #0
61 declare void @llvm.AMDGPU.barrier.local()
63 attributes #0 = { readnone }