1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=SI %s
2 ; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -strict-whitespace -check-prefix=GCN -check-prefix=VI %s
4 ; FIXME: Enable for VI.
6 declare i32 @llvm.r600.read.tidig.x() nounwind readnone
7 declare float @llvm.AMDGPU.div.fmas.f32(float, float, float, i1) nounwind readnone
8 declare double @llvm.AMDGPU.div.fmas.f64(double, double, double, i1) nounwind readnone
10 ; GCN-LABEL: {{^}}test_div_fmas_f32:
11 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
12 ; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
13 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
14 ; VI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
15 ; VI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x34
16 ; VI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x30
17 ; GCN-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
18 ; GCN-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
19 ; GCN-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
20 ; GCN: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VB]], [[VA]], [[VC]]
21 ; GCN: buffer_store_dword [[RESULT]],
23 define void @test_div_fmas_f32(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
24 %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %d) nounwind readnone
25 store float %result, float addrspace(1)* %out, align 4
29 ; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_0:
30 ; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
31 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
32 ; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
33 ; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
34 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VB]], [[VC]]
35 ; SI: buffer_store_dword [[RESULT]],
37 define void @test_div_fmas_f32_inline_imm_0(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
38 %result = call float @llvm.AMDGPU.div.fmas.f32(float 1.0, float %b, float %c, i1 %d) nounwind readnone
39 store float %result, float addrspace(1)* %out, align 4
43 ; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_1:
44 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
45 ; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd
46 ; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]]
47 ; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
48 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], 1.0, [[VA]], [[VC]]
49 ; SI: buffer_store_dword [[RESULT]],
51 define void @test_div_fmas_f32_inline_imm_1(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
52 %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float 1.0, float %c, i1 %d) nounwind readnone
53 store float %result, float addrspace(1)* %out, align 4
57 ; GCN-LABEL: {{^}}test_div_fmas_f32_inline_imm_2:
58 ; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
59 ; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc
60 ; SI-DAG: v_mov_b32_e32 [[VA:v[0-9]+]], [[SA]]
61 ; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]]
62 ; SI: v_div_fmas_f32 [[RESULT:v[0-9]+]], [[VA]], [[VB]], 1.0
63 ; SI: buffer_store_dword [[RESULT]],
65 define void @test_div_fmas_f32_inline_imm_2(float addrspace(1)* %out, float %a, float %b, float %c, i1 %d) nounwind {
66 %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float 1.0, i1 %d) nounwind readnone
67 store float %result, float addrspace(1)* %out, align 4
71 ; GCN-LABEL: {{^}}test_div_fmas_f64:
73 define void @test_div_fmas_f64(double addrspace(1)* %out, double %a, double %b, double %c, i1 %d) nounwind {
74 %result = call double @llvm.AMDGPU.div.fmas.f64(double %a, double %b, double %c, i1 %d) nounwind readnone
75 store double %result, double addrspace(1)* %out, align 8
79 ; GCN-LABEL: {{^}}test_div_fmas_f32_cond_to_vcc:
80 ; SI: v_cmp_eq_i32_e64 vcc, 0, s{{[0-9]+}}
81 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
82 define void @test_div_fmas_f32_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c, i32 %i) nounwind {
83 %cmp = icmp eq i32 %i, 0
84 %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %cmp) nounwind readnone
85 store float %result, float addrspace(1)* %out, align 4
89 ; GCN-LABEL: {{^}}test_div_fmas_f32_imm_false_cond_to_vcc:
90 ; SI: s_mov_b64 vcc, 0
91 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
92 define void @test_div_fmas_f32_imm_false_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
93 %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 false) nounwind readnone
94 store float %result, float addrspace(1)* %out, align 4
98 ; GCN-LABEL: {{^}}test_div_fmas_f32_imm_true_cond_to_vcc:
99 ; SI: s_mov_b64 vcc, -1
100 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
101 define void @test_div_fmas_f32_imm_true_cond_to_vcc(float addrspace(1)* %out, float %a, float %b, float %c) nounwind {
102 %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 true) nounwind readnone
103 store float %result, float addrspace(1)* %out, align 4
107 ; GCN-LABEL: {{^}}test_div_fmas_f32_logical_cond_to_vcc:
108 ; SI-DAG: buffer_load_dword [[A:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64{{$}}
109 ; SI-DAG: buffer_load_dword [[B:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:4{{$}}
110 ; SI-DAG: buffer_load_dword [[C:v[0-9]+]], {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:8{{$}}
112 ; SI-DAG: v_cmp_eq_i32_e32 [[CMP0:vcc]], 0, v{{[0-9]+}}
113 ; SI-DAG: v_cmp_ne_i32_e64 [[CMP1:s\[[0-9]+:[0-9]+\]]], 0, s{{[0-9]+}}
114 ; SI: s_and_b64 vcc, [[CMP0]], [[CMP1]]
115 ; SI: v_div_fmas_f32 {{v[0-9]+}}, [[A]], [[B]], [[C]]
117 define void @test_div_fmas_f32_logical_cond_to_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 %d) nounwind {
118 %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
119 %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid
120 %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1
121 %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2
122 %gep.out = getelementptr float, float addrspace(1)* %out, i32 2
124 %a = load float, float addrspace(1)* %gep.a
125 %b = load float, float addrspace(1)* %gep.b
126 %c = load float, float addrspace(1)* %gep.c
128 %cmp0 = icmp eq i32 %tid, 0
129 %cmp1 = icmp ne i32 %d, 0
130 %and = and i1 %cmp0, %cmp1
132 %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %and) nounwind readnone
133 store float %result, float addrspace(1)* %gep.out, align 4
137 ; GCN-LABEL: {{^}}test_div_fmas_f32_i1_phi_vcc:
138 ; SI: v_cmp_eq_i32_e32 vcc, 0, v{{[0-9]+}}
139 ; SI: s_and_saveexec_b64 [[SAVE:s\[[0-9]+:[0-9]+\]]], vcc
140 ; SI: s_xor_b64 [[SAVE]], exec, [[SAVE]]
142 ; SI: buffer_load_dword [[LOAD:v[0-9]+]]
143 ; SI: v_cmp_ne_i32_e32 vcc, 0, [[LOAD]]
144 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, 0, -1, vcc
148 ; SI: s_or_b64 exec, exec, [[SAVE]]
149 ; SI: v_cmp_ne_i32_e32 vcc, 0, v0
150 ; SI: v_div_fmas_f32 {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}, {{v[0-9]+}}
151 ; SI: buffer_store_dword
153 define void @test_div_fmas_f32_i1_phi_vcc(float addrspace(1)* %out, float addrspace(1)* %in, i32 addrspace(1)* %dummy) nounwind {
155 %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
156 %gep.out = getelementptr float, float addrspace(1)* %out, i32 2
157 %gep.a = getelementptr float, float addrspace(1)* %in, i32 %tid
158 %gep.b = getelementptr float, float addrspace(1)* %gep.a, i32 1
159 %gep.c = getelementptr float, float addrspace(1)* %gep.a, i32 2
161 %a = load float, float addrspace(1)* %gep.a
162 %b = load float, float addrspace(1)* %gep.b
163 %c = load float, float addrspace(1)* %gep.c
165 %cmp0 = icmp eq i32 %tid, 0
166 br i1 %cmp0, label %bb, label %exit
169 %val = load i32, i32 addrspace(1)* %dummy
170 %cmp1 = icmp ne i32 %val, 0
174 %cond = phi i1 [false, %entry], [%cmp1, %bb]
175 %result = call float @llvm.AMDGPU.div.fmas.f32(float %a, float %b, float %c, i1 %cond) nounwind readnone
176 store float %result, float addrspace(1)* %gep.out, align 4