1 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -mattr=+load-store-opt < %s | FileCheck -check-prefix=CI %s
3 @lds = addrspace(3) global [512 x float] undef, align 4
4 @lds.v2 = addrspace(3) global [512 x <2 x float>] undef, align 4
5 @lds.v3 = addrspace(3) global [512 x <3 x float>] undef, align 4
6 @lds.v4 = addrspace(3) global [512 x <4 x float>] undef, align 4
7 @lds.v8 = addrspace(3) global [512 x <8 x float>] undef, align 4
8 @lds.v16 = addrspace(3) global [512 x <16 x float>] undef, align 4
10 ; CI-LABEL: {{^}}simple_read2_v2f32_superreg_align4:
11 ; CI: ds_read2_b32 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}
12 ; CI: s_waitcnt lgkmcnt(0)
13 ; CI: buffer_store_dwordx2 [[RESULT]]
15 define void @simple_read2_v2f32_superreg_align4(<2 x float> addrspace(1)* %out) #0 {
16 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
17 %arrayidx0 = getelementptr inbounds [512 x <2 x float>], [512 x <2 x float>] addrspace(3)* @lds.v2, i32 0, i32 %x.i
18 %val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0, align 4
19 %out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i
20 store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep
24 ; CI-LABEL: {{^}}simple_read2_v2f32_superreg:
25 ; CI: ds_read_b64 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}}{{$}}
26 ; CI: s_waitcnt lgkmcnt(0)
27 ; CI: buffer_store_dwordx2 [[RESULT]]
29 define void @simple_read2_v2f32_superreg(<2 x float> addrspace(1)* %out) #0 {
30 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
31 %arrayidx0 = getelementptr inbounds [512 x <2 x float>], [512 x <2 x float>] addrspace(3)* @lds.v2, i32 0, i32 %x.i
32 %val0 = load <2 x float>, <2 x float> addrspace(3)* %arrayidx0
33 %out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i
34 store <2 x float> %val0, <2 x float> addrspace(1)* %out.gep
38 ; FIXME: Shuffling to new superregister
39 ; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align4:
40 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
41 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_Y:[0-9]+]]:[[REG_X:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
42 ; CI-DAG: v_mov_b32_e32 v[[COPY_REG_Y:[0-9]+]], v[[REG_Y]]
43 ; CI-DAG: v_mov_b32_e32 v[[COPY_REG_Z:[0-9]+]], v[[REG_Z]]
44 ; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[COPY_REG_Z]], v[[REG_X]]
45 ; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[REG_W]], v[[COPY_REG_Y]]
46 ; CI: v_add_f32_e32 v[[ADD2:[0-9]+]], v[[ADD1]], v[[ADD0]]
47 ; CI: buffer_store_dword v[[ADD2]]
49 define void @simple_read2_v4f32_superreg_align4(float addrspace(1)* %out) #0 {
50 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
51 %arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i
52 %val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0, align 4
53 %elt0 = extractelement <4 x float> %val0, i32 0
54 %elt1 = extractelement <4 x float> %val0, i32 1
55 %elt2 = extractelement <4 x float> %val0, i32 2
56 %elt3 = extractelement <4 x float> %val0, i32 3
58 %add0 = fadd float %elt0, %elt2
59 %add1 = fadd float %elt1, %elt3
60 %add2 = fadd float %add0, %add1
62 %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
63 store float %add2, float addrspace(1)* %out.gep
67 ; CI-LABEL: {{^}}simple_read2_v3f32_superreg_align4:
68 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
69 ; CI-DAG: ds_read_b32 v[[REG_Z:[0-9]+]], v{{[0-9]+}} offset:8{{$}}
70 ; CI-DAG: v_add_f32_e32 v[[ADD0:[0-9]+]], v[[REG_Z]], v[[REG_X]]
71 ; CI-DAG: v_add_f32_e32 v[[ADD1:[0-9]+]], v[[REG_Y]], v[[ADD0]]
72 ; CI: buffer_store_dword v[[ADD1]]
74 define void @simple_read2_v3f32_superreg_align4(float addrspace(1)* %out) #0 {
75 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
76 %arrayidx0 = getelementptr inbounds [512 x <3 x float>], [512 x <3 x float>] addrspace(3)* @lds.v3, i32 0, i32 %x.i
77 %val0 = load <3 x float>, <3 x float> addrspace(3)* %arrayidx0, align 4
78 %elt0 = extractelement <3 x float> %val0, i32 0
79 %elt1 = extractelement <3 x float> %val0, i32 1
80 %elt2 = extractelement <3 x float> %val0, i32 2
82 %add0 = fadd float %elt0, %elt2
83 %add1 = fadd float %add0, %elt1
85 %out.gep = getelementptr inbounds float, float addrspace(1)* %out, i32 %x.i
86 store float %add1, float addrspace(1)* %out.gep
90 ; CI-LABEL: {{^}}simple_read2_v4f32_superreg_align8:
91 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
92 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
93 ; CI: buffer_store_dwordx4
95 define void @simple_read2_v4f32_superreg_align8(<4 x float> addrspace(1)* %out) #0 {
96 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
97 %arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i
98 %val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0, align 8
99 %out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i
100 store <4 x float> %val0, <4 x float> addrspace(1)* %out.gep
104 ; CI-LABEL: {{^}}simple_read2_v4f32_superreg:
105 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_W:[0-9]+]]:[[REG_Z:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
106 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
107 ; CI: buffer_store_dwordx4
109 define void @simple_read2_v4f32_superreg(<4 x float> addrspace(1)* %out) #0 {
110 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
111 %arrayidx0 = getelementptr inbounds [512 x <4 x float>], [512 x <4 x float>] addrspace(3)* @lds.v4, i32 0, i32 %x.i
112 %val0 = load <4 x float>, <4 x float> addrspace(3)* %arrayidx0
113 %out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i
114 store <4 x float> %val0, <4 x float> addrspace(1)* %out.gep
118 ; CI-LABEL: {{^}}simple_read2_v8f32_superreg:
119 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:7 offset1:6{{$}}
120 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT5:[0-9]+]]:[[REG_ELT4:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:5 offset1:4{{$}}
121 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT3:[0-9]+]]:[[REG_ELT2:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
122 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT1:[0-9]+]]:[[REG_ELT0:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
123 ; CI: buffer_store_dword
124 ; CI: buffer_store_dword
125 ; CI: buffer_store_dword
126 ; CI: buffer_store_dword
127 ; CI: buffer_store_dword
128 ; CI: buffer_store_dword
129 ; CI: buffer_store_dword
130 ; CI: buffer_store_dword
132 define void @simple_read2_v8f32_superreg(<8 x float> addrspace(1)* %out) #0 {
133 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
134 %arrayidx0 = getelementptr inbounds [512 x <8 x float>], [512 x <8 x float>] addrspace(3)* @lds.v8, i32 0, i32 %x.i
135 %val0 = load <8 x float>, <8 x float> addrspace(3)* %arrayidx0
136 %out.gep = getelementptr inbounds <8 x float>, <8 x float> addrspace(1)* %out, i32 %x.i
137 store <8 x float> %val0, <8 x float> addrspace(1)* %out.gep
141 ; CI-LABEL: {{^}}simple_read2_v16f32_superreg:
142 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:15 offset1:14{{$}}
143 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:13 offset1:12{{$}}
144 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:11 offset1:10{{$}}
145 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:9 offset1:8{{$}}
146 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT7:[0-9]+]]:[[REG_ELT6:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:7 offset1:6{{$}}
147 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT5:[0-9]+]]:[[REG_ELT4:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:5 offset1:4{{$}}
148 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT3:[0-9]+]]:[[REG_ELT2:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:3 offset1:2{{$}}
149 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT1:[0-9]+]]:[[REG_ELT0:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:1{{$}}
151 ; CI: s_waitcnt lgkmcnt(0)
152 ; CI: buffer_store_dword
153 ; CI: buffer_store_dword
154 ; CI: buffer_store_dword
155 ; CI: buffer_store_dword
156 ; CI: buffer_store_dword
157 ; CI: buffer_store_dword
158 ; CI: buffer_store_dword
159 ; CI: buffer_store_dword
160 ; CI: buffer_store_dword
161 ; CI: buffer_store_dword
162 ; CI: buffer_store_dword
163 ; CI: buffer_store_dword
164 ; CI: buffer_store_dword
165 ; CI: buffer_store_dword
166 ; CI: buffer_store_dword
167 ; CI: buffer_store_dword
169 define void @simple_read2_v16f32_superreg(<16 x float> addrspace(1)* %out) #0 {
170 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
171 %arrayidx0 = getelementptr inbounds [512 x <16 x float>], [512 x <16 x float>] addrspace(3)* @lds.v16, i32 0, i32 %x.i
172 %val0 = load <16 x float>, <16 x float> addrspace(3)* %arrayidx0
173 %out.gep = getelementptr inbounds <16 x float>, <16 x float> addrspace(1)* %out, i32 %x.i
174 store <16 x float> %val0, <16 x float> addrspace(1)* %out.gep
178 ; Do scalar loads into the super register we need.
179 ; CI-LABEL: {{^}}simple_read2_v2f32_superreg_scalar_loads_align4:
180 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
182 ; CI: buffer_store_dwordx2 v{{\[}}[[REG_ELT0]]:[[REG_ELT1]]{{\]}}
184 define void @simple_read2_v2f32_superreg_scalar_loads_align4(<2 x float> addrspace(1)* %out) #0 {
185 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
186 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
187 %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 1
189 %val0 = load float, float addrspace(3)* %arrayidx0
190 %val1 = load float, float addrspace(3)* %arrayidx1
192 %vec.0 = insertelement <2 x float> undef, float %val0, i32 0
193 %vec.1 = insertelement <2 x float> %vec.0, float %val1, i32 1
195 %out.gep = getelementptr inbounds <2 x float>, <2 x float> addrspace(1)* %out, i32 %x.i
196 store <2 x float> %vec.1, <2 x float> addrspace(1)* %out.gep
200 ; Do scalar loads into the super register we need.
201 ; CI-LABEL: {{^}}simple_read2_v4f32_superreg_scalar_loads_align4:
202 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT0:[0-9]+]]:[[REG_ELT1:[0-9]+]]{{\]}}, v{{[0-9]+}} offset1:1{{$}}
203 ; CI-DAG: ds_read2_b32 v{{\[}}[[REG_ELT2:[0-9]+]]:[[REG_ELT3:[0-9]+]]{{\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
205 ; CI: buffer_store_dwordx4 v{{\[}}[[REG_ELT0]]:[[REG_ELT3]]{{\]}}
207 define void @simple_read2_v4f32_superreg_scalar_loads_align4(<4 x float> addrspace(1)* %out) #0 {
208 %x.i = tail call i32 @llvm.r600.read.tidig.x() #1
209 %arrayidx0 = getelementptr inbounds [512 x float], [512 x float] addrspace(3)* @lds, i32 0, i32 %x.i
210 %arrayidx1 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 1
211 %arrayidx2 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 2
212 %arrayidx3 = getelementptr inbounds float, float addrspace(3)* %arrayidx0, i32 3
214 %val0 = load float, float addrspace(3)* %arrayidx0
215 %val1 = load float, float addrspace(3)* %arrayidx1
216 %val2 = load float, float addrspace(3)* %arrayidx2
217 %val3 = load float, float addrspace(3)* %arrayidx3
219 %vec.0 = insertelement <4 x float> undef, float %val0, i32 0
220 %vec.1 = insertelement <4 x float> %vec.0, float %val1, i32 1
221 %vec.2 = insertelement <4 x float> %vec.1, float %val2, i32 2
222 %vec.3 = insertelement <4 x float> %vec.2, float %val3, i32 3
224 %out.gep = getelementptr inbounds <4 x float>, <4 x float> addrspace(1)* %out, i32 %x.i
225 store <4 x float> %vec.3, <4 x float> addrspace(1)* %out.gep
229 ; Function Attrs: nounwind readnone
230 declare i32 @llvm.r600.read.tgid.x() #1
232 ; Function Attrs: nounwind readnone
233 declare i32 @llvm.r600.read.tgid.y() #1
235 ; Function Attrs: nounwind readnone
236 declare i32 @llvm.r600.read.tidig.x() #1
238 ; Function Attrs: nounwind readnone
239 declare i32 @llvm.r600.read.tidig.y() #1
241 ; Function Attrs: noduplicate nounwind
242 declare void @llvm.AMDGPU.barrier.local() #2
244 attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
245 attributes #1 = { nounwind readnone }
246 attributes #2 = { noduplicate nounwind }