1 ; RUN: llc -march=amdgcn -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
4 declare i64 @llvm.ctpop.i64(i64) nounwind readnone
5 declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64>) nounwind readnone
6 declare <4 x i64> @llvm.ctpop.v4i64(<4 x i64>) nounwind readnone
7 declare <8 x i64> @llvm.ctpop.v8i64(<8 x i64>) nounwind readnone
8 declare <16 x i64> @llvm.ctpop.v16i64(<16 x i64>) nounwind readnone
10 ; FUNC-LABEL: {{^}}s_ctpop_i64:
11 ; SI: s_load_dwordx2 [[SVAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0xb
12 ; VI: s_load_dwordx2 [[SVAL:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, 0x2c
13 ; GCN: s_bcnt1_i32_b64 [[SRESULT:s[0-9]+]], [[SVAL]]
14 ; GCN: v_mov_b32_e32 [[VRESULT:v[0-9]+]], [[SRESULT]]
15 ; GCN: buffer_store_dword [[VRESULT]],
17 define void @s_ctpop_i64(i32 addrspace(1)* noalias %out, i64 %val) nounwind {
18 %ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
19 %truncctpop = trunc i64 %ctpop to i32
20 store i32 %truncctpop, i32 addrspace(1)* %out, align 4
24 ; FUNC-LABEL: {{^}}v_ctpop_i64:
25 ; GCN: buffer_load_dwordx2 v{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}},
26 ; GCN: v_bcnt_u32_b32_e64 [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0
27 ; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
28 ; VI-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
29 ; GCN: buffer_store_dword [[RESULT]],
31 define void @v_ctpop_i64(i32 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind {
32 %val = load i64, i64 addrspace(1)* %in, align 8
33 %ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
34 %truncctpop = trunc i64 %ctpop to i32
35 store i32 %truncctpop, i32 addrspace(1)* %out, align 4
39 ; FIXME: We shouldn't emit the v_mov_b32 0
40 ; FUNC-LABEL: {{^}}v_ctpop_i64_user:
41 ; GCN: buffer_load_dwordx2 v{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}},
42 ; GCN: v_bcnt_u32_b32_e64 [[MIDRESULT:v[0-9]+]], v[[LOVAL]], 0
43 ; SI-NEXT: v_bcnt_u32_b32_e32 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
44 ; VI-NEXT: v_bcnt_u32_b32_e64 [[RESULT:v[0-9]+]], v[[HIVAL]], [[MIDRESULT]]
45 ; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
46 ; GCN-DAG: v_or_b32_e32 v[[RESULT_LO:[0-9]+]], s{{[0-9]+}}, [[RESULT]]
47 ; GCN-DAG: v_or_b32_e32 v[[RESULT_HI:[0-9]+]], s{{[0-9]+}}, v[[ZERO]]
48 ; GCN: buffer_store_dwordx2 v{{\[}}[[RESULT_LO]]:[[RESULT_HI]]{{\]}}
50 define void @v_ctpop_i64_user(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i64 %s.val) nounwind {
51 %val = load i64, i64 addrspace(1)* %in, align 8
52 %ctpop = call i64 @llvm.ctpop.i64(i64 %val) nounwind readnone
53 %or = or i64 %ctpop, %s.val
54 store i64 %or, i64 addrspace(1)* %out
58 ; FUNC-LABEL: {{^}}s_ctpop_v2i64:
59 ; GCN: s_bcnt1_i32_b64
60 ; GCN: s_bcnt1_i32_b64
62 define void @s_ctpop_v2i64(<2 x i32> addrspace(1)* noalias %out, <2 x i64> %val) nounwind {
63 %ctpop = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %val) nounwind readnone
64 %truncctpop = trunc <2 x i64> %ctpop to <2 x i32>
65 store <2 x i32> %truncctpop, <2 x i32> addrspace(1)* %out, align 8
69 ; FUNC-LABEL: {{^}}s_ctpop_v4i64:
70 ; GCN: s_bcnt1_i32_b64
71 ; GCN: s_bcnt1_i32_b64
72 ; GCN: s_bcnt1_i32_b64
73 ; GCN: s_bcnt1_i32_b64
75 define void @s_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> %val) nounwind {
76 %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
77 %truncctpop = trunc <4 x i64> %ctpop to <4 x i32>
78 store <4 x i32> %truncctpop, <4 x i32> addrspace(1)* %out, align 16
82 ; FUNC-LABEL: {{^}}v_ctpop_v2i64:
88 define void @v_ctpop_v2i64(<2 x i32> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in) nounwind {
89 %val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
90 %ctpop = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %val) nounwind readnone
91 %truncctpop = trunc <2 x i64> %ctpop to <2 x i32>
92 store <2 x i32> %truncctpop, <2 x i32> addrspace(1)* %out, align 8
96 ; FUNC-LABEL: {{^}}v_ctpop_v4i64:
100 ; GCN: v_bcnt_u32_b32
101 ; GCN: v_bcnt_u32_b32
102 ; GCN: v_bcnt_u32_b32
103 ; GCN: v_bcnt_u32_b32
104 ; GCN: v_bcnt_u32_b32
106 define void @v_ctpop_v4i64(<4 x i32> addrspace(1)* noalias %out, <4 x i64> addrspace(1)* noalias %in) nounwind {
107 %val = load <4 x i64>, <4 x i64> addrspace(1)* %in, align 32
108 %ctpop = call <4 x i64> @llvm.ctpop.v4i64(<4 x i64> %val) nounwind readnone
109 %truncctpop = trunc <4 x i64> %ctpop to <4 x i32>
110 store <4 x i32> %truncctpop, <4 x i32> addrspace(1)* %out, align 16
114 ; FIXME: We currently disallow SALU instructions in all branches,
115 ; but there are some cases when the should be allowed.
117 ; FUNC-LABEL: {{^}}ctpop_i64_in_br:
118 ; SI: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0xd
119 ; VI: s_load_dwordx2 s{{\[}}[[LOVAL:[0-9]+]]:[[HIVAL:[0-9]+]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0x34
120 ; GCN: s_bcnt1_i32_b64 [[RESULT:s[0-9]+]], {{s\[}}[[LOVAL]]:[[HIVAL]]{{\]}}
121 ; GCN: v_mov_b32_e32 v[[VLO:[0-9]+]], [[RESULT]]
122 ; GCN: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[HIVAL]]
123 ; GCN: buffer_store_dwordx2 {{v\[}}[[VLO]]:[[VHI]]{{\]}}
125 define void @ctpop_i64_in_br(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %ctpop_arg, i32 %cond) {
127 %tmp0 = icmp eq i32 %cond, 0
128 br i1 %tmp0, label %if, label %else
131 %tmp2 = call i64 @llvm.ctpop.i64(i64 %ctpop_arg)
135 %tmp3 = getelementptr i64, i64 addrspace(1)* %in, i32 1
136 %tmp4 = load i64, i64 addrspace(1)* %tmp3
140 %tmp5 = phi i64 [%tmp2, %if], [%tmp4, %else]
141 store i64 %tmp5, i64 addrspace(1)* %out