1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
2 ; arm64 already has these tests: pure intrinsics & trivial shifts.
4 declare <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8>, <8 x i8>)
5 declare <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8>, <8 x i8>)
7 define <8 x i8> @test_uqshl_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
8 ; CHECK: test_uqshl_v8i8:
9 %tmp1 = call <8 x i8> @llvm.arm.neon.vshiftu.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
10 ; CHECK: ushl v0.8b, v0.8b, v1.8b
14 define <8 x i8> @test_sqshl_v8i8(<8 x i8> %lhs, <8 x i8> %rhs) {
15 ; CHECK: test_sqshl_v8i8:
16 %tmp1 = call <8 x i8> @llvm.arm.neon.vshifts.v8i8(<8 x i8> %lhs, <8 x i8> %rhs)
17 ; CHECK: sshl v0.8b, v0.8b, v1.8b
21 declare <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8>, <16 x i8>)
22 declare <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8>, <16 x i8>)
24 define <16 x i8> @test_ushl_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
25 ; CHECK: test_ushl_v16i8:
26 %tmp1 = call <16 x i8> @llvm.arm.neon.vshiftu.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
27 ; CHECK: ushl v0.16b, v0.16b, v1.16b
31 define <16 x i8> @test_sshl_v16i8(<16 x i8> %lhs, <16 x i8> %rhs) {
32 ; CHECK: test_sshl_v16i8:
33 %tmp1 = call <16 x i8> @llvm.arm.neon.vshifts.v16i8(<16 x i8> %lhs, <16 x i8> %rhs)
34 ; CHECK: sshl v0.16b, v0.16b, v1.16b
38 declare <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16>, <4 x i16>)
39 declare <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16>, <4 x i16>)
41 define <4 x i16> @test_ushl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
42 ; CHECK: test_ushl_v4i16:
43 %tmp1 = call <4 x i16> @llvm.arm.neon.vshiftu.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
44 ; CHECK: ushl v0.4h, v0.4h, v1.4h
48 define <4 x i16> @test_sshl_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
49 ; CHECK: test_sshl_v4i16:
50 %tmp1 = call <4 x i16> @llvm.arm.neon.vshifts.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
51 ; CHECK: sshl v0.4h, v0.4h, v1.4h
55 declare <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16>, <8 x i16>)
56 declare <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16>, <8 x i16>)
58 define <8 x i16> @test_ushl_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
59 ; CHECK: test_ushl_v8i16:
60 %tmp1 = call <8 x i16> @llvm.arm.neon.vshiftu.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
61 ; CHECK: ushl v0.8h, v0.8h, v1.8h
65 define <8 x i16> @test_sshl_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
66 ; CHECK: test_sshl_v8i16:
67 %tmp1 = call <8 x i16> @llvm.arm.neon.vshifts.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
68 ; CHECK: sshl v0.8h, v0.8h, v1.8h
72 declare <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32>, <2 x i32>)
73 declare <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32>, <2 x i32>)
75 define <2 x i32> @test_ushl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
76 ; CHECK: test_ushl_v2i32:
77 %tmp1 = call <2 x i32> @llvm.arm.neon.vshiftu.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
78 ; CHECK: ushl v0.2s, v0.2s, v1.2s
82 define <2 x i32> @test_sshl_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
83 ; CHECK: test_sshl_v2i32:
84 %tmp1 = call <2 x i32> @llvm.arm.neon.vshifts.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
85 ; CHECK: sshl v0.2s, v0.2s, v1.2s
89 declare <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32>, <4 x i32>)
90 declare <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32>, <4 x i32>)
92 define <4 x i32> @test_ushl_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
93 ; CHECK: test_ushl_v4i32:
94 %tmp1 = call <4 x i32> @llvm.arm.neon.vshiftu.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
95 ; CHECK: ushl v0.4s, v0.4s, v1.4s
99 define <4 x i32> @test_sshl_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
100 ; CHECK: test_sshl_v4i32:
101 %tmp1 = call <4 x i32> @llvm.arm.neon.vshifts.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
102 ; CHECK: sshl v0.4s, v0.4s, v1.4s
106 declare <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64>, <2 x i64>)
107 declare <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64>, <2 x i64>)
109 define <2 x i64> @test_ushl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
110 ; CHECK: test_ushl_v2i64:
111 %tmp1 = call <2 x i64> @llvm.arm.neon.vshiftu.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
112 ; CHECK: ushl v0.2d, v0.2d, v1.2d
116 define <2 x i64> @test_sshl_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
117 ; CHECK: test_sshl_v2i64:
118 %tmp1 = call <2 x i64> @llvm.arm.neon.vshifts.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
119 ; CHECK: sshl v0.2d, v0.2d, v1.2d
124 define <8 x i8> @test_shl_v8i8(<8 x i8> %a) {
125 ; CHECK: test_shl_v8i8:
126 ; CHECK: shl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #3
127 %tmp = shl <8 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
131 define <4 x i16> @test_shl_v4i16(<4 x i16> %a) {
132 ; CHECK: test_shl_v4i16:
133 ; CHECK: shl {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, #3
134 %tmp = shl <4 x i16> %a, <i16 3, i16 3, i16 3, i16 3>
138 define <2 x i32> @test_shl_v2i32(<2 x i32> %a) {
139 ; CHECK: test_shl_v2i32:
140 ; CHECK: shl {{v[0-9]+}}.2s, {{v[0-9]+}}.2s, #3
141 %tmp = shl <2 x i32> %a, <i32 3, i32 3>
145 define <16 x i8> @test_shl_v16i8(<16 x i8> %a) {
146 ; CHECK: test_shl_v16i8:
147 ; CHECK: shl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, #3
148 %tmp = shl <16 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>
152 define <8 x i16> @test_shl_v8i16(<8 x i16> %a) {
153 ; CHECK: test_shl_v8i16:
154 ; CHECK: shl {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, #3
155 %tmp = shl <8 x i16> %a, <i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3, i16 3>
159 define <4 x i32> @test_shl_v4i32(<4 x i32> %a) {
160 ; CHECK: test_shl_v4i32:
161 ; CHECK: shl {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, #3
162 %tmp = shl <4 x i32> %a, <i32 3, i32 3, i32 3, i32 3>
166 define <2 x i64> @test_shl_v2i64(<2 x i64> %a) {
167 ; CHECK: test_shl_v2i64:
168 ; CHECK: shl {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, #63
169 %tmp = shl <2 x i64> %a, <i64 63, i64 63>