1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
3 declare <1 x i64> @llvm.aarch64.neon.vpadd(<2 x i64>)
5 define <1 x i64> @test_addp_v1i64(<2 x i64> %a) {
6 ; CHECK: test_addp_v1i64:
7 ; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
8 %val = call <1 x i64> @llvm.aarch64.neon.vpadd(<2 x i64> %a)
12 declare <1 x float> @llvm.aarch64.neon.vpfadd.v1f32.v2f32(<2 x float>)
14 define <1 x float> @test_faddp_v1f32(<2 x float> %a) {
15 ; CHECK: test_faddp_v1f32:
16 ; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
17 %val = call <1 x float> @llvm.aarch64.neon.vpfadd.v1f32.v2f32(<2 x float> %a)
21 declare <1 x double> @llvm.aarch64.neon.vpfadd.v1f64.v2f64(<2 x double>)
23 define <1 x double> @test_faddp_v1f64(<2 x double> %a) {
24 ; CHECK: test_faddp_v1f64:
25 ; CHECK: faddp {{d[0-9]+}}, {{v[0-9]+}}.2d
26 %val = call <1 x double> @llvm.aarch64.neon.vpfadd.v1f64.v2f64(<2 x double> %a)
31 declare <1 x float> @llvm.aarch64.neon.vpmax.v1f32.v2f32(<2 x float>)
33 define <1 x float> @test_fmaxp_v1f32(<2 x float> %a) {
34 ; CHECK: test_fmaxp_v1f32:
35 ; CHECK: fmaxp {{s[0-9]+}}, {{v[0-9]+}}.2s
36 %val = call <1 x float> @llvm.aarch64.neon.vpmax.v1f32.v2f32(<2 x float> %a)
40 declare <1 x double> @llvm.aarch64.neon.vpmax.v1f64.v2f64(<2 x double>)
42 define <1 x double> @test_fmaxp_v1f64(<2 x double> %a) {
43 ; CHECK: test_fmaxp_v1f64:
44 ; CHECK: fmaxp {{d[0-9]+}}, {{v[0-9]+}}.2d
45 %val = call <1 x double> @llvm.aarch64.neon.vpmax.v1f64.v2f64(<2 x double> %a)
49 declare <1 x float> @llvm.aarch64.neon.vpmin.v1f32.v2f32(<2 x float>)
51 define <1 x float> @test_fminp_v1f32(<2 x float> %a) {
52 ; CHECK: test_fminp_v1f32:
53 ; CHECK: fminp {{s[0-9]+}}, {{v[0-9]+}}.2s
54 %val = call <1 x float> @llvm.aarch64.neon.vpmin.v1f32.v2f32(<2 x float> %a)
58 declare <1 x double> @llvm.aarch64.neon.vpmin.v1f64.v2f64(<2 x double>)
60 define <1 x double> @test_fminp_v1f64(<2 x double> %a) {
61 ; CHECK: test_fminp_v1f64:
62 ; CHECK: fminp {{d[0-9]+}}, {{v[0-9]+}}.2d
63 %val = call <1 x double> @llvm.aarch64.neon.vpmin.v1f64.v2f64(<2 x double> %a)
67 declare <1 x float> @llvm.aarch64.neon.vpfmaxnm.v1f32.v2f32(<2 x float>)
69 define <1 x float> @test_fmaxnmp_v1f32(<2 x float> %a) {
70 ; CHECK: test_fmaxnmp_v1f32:
71 ; CHECK: fmaxnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
72 %val = call <1 x float> @llvm.aarch64.neon.vpfmaxnm.v1f32.v2f32(<2 x float> %a)
76 declare <1 x double> @llvm.aarch64.neon.vpfmaxnm.v1f64.v2f64(<2 x double>)
78 define <1 x double> @test_fmaxnmp_v1f64(<2 x double> %a) {
79 ; CHECK: test_fmaxnmp_v1f64:
80 ; CHECK: fmaxnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
81 %val = call <1 x double> @llvm.aarch64.neon.vpfmaxnm.v1f64.v2f64(<2 x double> %a)
85 declare <1 x float> @llvm.aarch64.neon.vpfminnm.v1f32.v2f32(<2 x float>)
87 define <1 x float> @test_fminnmp_v1f32(<2 x float> %a) {
88 ; CHECK: test_fminnmp_v1f32:
89 ; CHECK: fminnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
90 %val = call <1 x float> @llvm.aarch64.neon.vpfminnm.v1f32.v2f32(<2 x float> %a)
94 declare <1 x double> @llvm.aarch64.neon.vpfminnm.v1f64.v2f64(<2 x double>)
96 define <1 x double> @test_fminnmp_v1f64(<2 x double> %a) {
97 ; CHECK: test_fminnmp_v1f64:
98 ; CHECK: fminnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
99 %val = call <1 x double> @llvm.aarch64.neon.vpfminnm.v1f64.v2f64(<2 x double> %a)
100 ret <1 x double> %val
103 define float @test_vaddv_f32(<2 x float> %a) {
104 ; CHECK-LABEL: test_vaddv_f32
105 ; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
106 %1 = tail call <1 x float> @llvm.aarch64.neon.vaddv.v1f32.v2f32(<2 x float> %a)
107 %2 = extractelement <1 x float> %1, i32 0
111 define float @test_vaddvq_f32(<4 x float> %a) {
112 ; CHECK-LABEL: test_vaddvq_f32
113 ; CHECK: faddp {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
114 ; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
115 %1 = tail call <1 x float> @llvm.aarch64.neon.vaddv.v1f32.v4f32(<4 x float> %a)
116 %2 = extractelement <1 x float> %1, i32 0
120 define double @test_vaddvq_f64(<2 x double> %a) {
121 ; CHECK-LABEL: test_vaddvq_f64
122 ; CHECK: faddp {{d[0-9]+}}, {{v[0-9]+}}.2d
123 %1 = tail call <1 x double> @llvm.aarch64.neon.vaddv.v1f64.v2f64(<2 x double> %a)
124 %2 = extractelement <1 x double> %1, i32 0
128 define float @test_vmaxv_f32(<2 x float> %a) {
129 ; CHECK-LABEL: test_vmaxv_f32
130 ; CHECK: fmaxp {{s[0-9]+}}, {{v[0-9]+}}.2s
131 %1 = tail call <1 x float> @llvm.aarch64.neon.vmaxv.v1f32.v2f32(<2 x float> %a)
132 %2 = extractelement <1 x float> %1, i32 0
136 define double @test_vmaxvq_f64(<2 x double> %a) {
137 ; CHECK-LABEL: test_vmaxvq_f64
138 ; CHECK: fmaxp {{d[0-9]+}}, {{v[0-9]+}}.2d
139 %1 = tail call <1 x double> @llvm.aarch64.neon.vmaxv.v1f64.v2f64(<2 x double> %a)
140 %2 = extractelement <1 x double> %1, i32 0
144 define float @test_vminv_f32(<2 x float> %a) {
145 ; CHECK-LABEL: test_vminv_f32
146 ; CHECK: fminp {{s[0-9]+}}, {{v[0-9]+}}.2s
147 %1 = tail call <1 x float> @llvm.aarch64.neon.vminv.v1f32.v2f32(<2 x float> %a)
148 %2 = extractelement <1 x float> %1, i32 0
152 define double @test_vminvq_f64(<2 x double> %a) {
153 ; CHECK-LABEL: test_vminvq_f64
154 ; CHECK: fminp {{d[0-9]+}}, {{v[0-9]+}}.2d
155 %1 = tail call <1 x double> @llvm.aarch64.neon.vminv.v1f64.v2f64(<2 x double> %a)
156 %2 = extractelement <1 x double> %1, i32 0
160 define double @test_vmaxnmvq_f64(<2 x double> %a) {
161 ; CHECK-LABEL: test_vmaxnmvq_f64
162 ; CHECK: fmaxnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
163 %1 = tail call <1 x double> @llvm.aarch64.neon.vmaxnmv.v1f64.v2f64(<2 x double> %a)
164 %2 = extractelement <1 x double> %1, i32 0
168 define float @test_vmaxnmv_f32(<2 x float> %a) {
169 ; CHECK-LABEL: test_vmaxnmv_f32
170 ; CHECK: fmaxnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
171 %1 = tail call <1 x float> @llvm.aarch64.neon.vmaxnmv.v1f32.v2f32(<2 x float> %a)
172 %2 = extractelement <1 x float> %1, i32 0
176 define double @test_vminnmvq_f64(<2 x double> %a) {
177 ; CHECK-LABEL: test_vminnmvq_f64
178 ; CHECK: fminnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
179 %1 = tail call <1 x double> @llvm.aarch64.neon.vminnmv.v1f64.v2f64(<2 x double> %a)
180 %2 = extractelement <1 x double> %1, i32 0
184 define float @test_vminnmv_f32(<2 x float> %a) {
185 ; CHECK-LABEL: test_vminnmv_f32
186 ; CHECK: fminnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
187 %1 = tail call <1 x float> @llvm.aarch64.neon.vminnmv.v1f32.v2f32(<2 x float> %a)
188 %2 = extractelement <1 x float> %1, i32 0
192 define <2 x i64> @test_vpaddq_s64(<2 x i64> %a, <2 x i64> %b) {
193 ; CHECK-LABEL: test_vpaddq_s64
194 ; CHECK: addp {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
195 %1 = tail call <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64> %a, <2 x i64> %b)
199 define <2 x i64> @test_vpaddq_u64(<2 x i64> %a, <2 x i64> %b) {
200 ; CHECK-LABEL: test_vpaddq_u64
201 ; CHECK: addp {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
202 %1 = tail call <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64> %a, <2 x i64> %b)
206 define i64 @test_vaddvq_s64(<2 x i64> %a) {
207 ; CHECK-LABEL: test_vaddvq_s64
208 ; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
209 %1 = tail call <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64> %a)
210 %2 = extractelement <1 x i64> %1, i32 0
214 define i64 @test_vaddvq_u64(<2 x i64> %a) {
215 ; CHECK-LABEL: test_vaddvq_u64
216 ; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
217 %1 = tail call <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64> %a)
218 %2 = extractelement <1 x i64> %1, i32 0
222 declare <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64>)
224 declare <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64>, <2 x i64>)
226 declare <1 x float> @llvm.aarch64.neon.vminnmv.v1f32.v2f32(<2 x float>)
228 declare <1 x double> @llvm.aarch64.neon.vminnmv.v1f64.v2f64(<2 x double>)
230 declare <1 x float> @llvm.aarch64.neon.vmaxnmv.v1f32.v2f32(<2 x float>)
232 declare <1 x double> @llvm.aarch64.neon.vmaxnmv.v1f64.v2f64(<2 x double>)
234 declare <1 x double> @llvm.aarch64.neon.vminv.v1f64.v2f64(<2 x double>)
236 declare <1 x float> @llvm.aarch64.neon.vminv.v1f32.v2f32(<2 x float>)
238 declare <1 x double> @llvm.aarch64.neon.vmaxv.v1f64.v2f64(<2 x double>)
240 declare <1 x float> @llvm.aarch64.neon.vmaxv.v1f32.v2f32(<2 x float>)
242 declare <1 x double> @llvm.aarch64.neon.vaddv.v1f64.v2f64(<2 x double>)
244 declare <1 x float> @llvm.aarch64.neon.vaddv.v1f32.v4f32(<4 x float>)
246 declare <1 x float> @llvm.aarch64.neon.vaddv.v1f32.v2f32(<2 x float>)