1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
3 declare <1 x i64> @llvm.aarch64.neon.vpadd(<2 x i64>)
5 define <1 x i64> @test_addp_v1i64(<2 x i64> %a) {
6 ; CHECK: test_addp_v1i64:
7 ; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
8 %val = call <1 x i64> @llvm.aarch64.neon.vpadd(<2 x i64> %a)
12 declare float @llvm.aarch64.neon.vpfadd.f32.v2f32(<2 x float>)
14 define float @test_faddp_f32(<2 x float> %a) {
15 ; CHECK: test_faddp_f32:
16 ; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
17 %val = call float @llvm.aarch64.neon.vpfadd.f32.v2f32(<2 x float> %a)
21 declare double @llvm.aarch64.neon.vpfadd.f64.v2f64(<2 x double>)
23 define double @test_faddp_f64(<2 x double> %a) {
24 ; CHECK: test_faddp_f64:
25 ; CHECK: faddp {{d[0-9]+}}, {{v[0-9]+}}.2d
26 %val = call double @llvm.aarch64.neon.vpfadd.f64.v2f64(<2 x double> %a)
31 declare float @llvm.aarch64.neon.vpmax.f32.v2f32(<2 x float>)
33 define float @test_fmaxp_f32(<2 x float> %a) {
34 ; CHECK: test_fmaxp_f32:
35 ; CHECK: fmaxp {{s[0-9]+}}, {{v[0-9]+}}.2s
36 %val = call float @llvm.aarch64.neon.vpmax.f32.v2f32(<2 x float> %a)
40 declare double @llvm.aarch64.neon.vpmax.f64.v2f64(<2 x double>)
42 define double @test_fmaxp_f64(<2 x double> %a) {
43 ; CHECK: test_fmaxp_f64:
44 ; CHECK: fmaxp {{d[0-9]+}}, {{v[0-9]+}}.2d
45 %val = call double @llvm.aarch64.neon.vpmax.f64.v2f64(<2 x double> %a)
49 declare float @llvm.aarch64.neon.vpmin.f32.v2f32(<2 x float>)
51 define float @test_fminp_f32(<2 x float> %a) {
52 ; CHECK: test_fminp_f32:
53 ; CHECK: fminp {{s[0-9]+}}, {{v[0-9]+}}.2s
54 %val = call float @llvm.aarch64.neon.vpmin.f32.v2f32(<2 x float> %a)
58 declare double @llvm.aarch64.neon.vpmin.f64.v2f64(<2 x double>)
60 define double @test_fminp_f64(<2 x double> %a) {
61 ; CHECK: test_fminp_f64:
62 ; CHECK: fminp {{d[0-9]+}}, {{v[0-9]+}}.2d
63 %val = call double @llvm.aarch64.neon.vpmin.f64.v2f64(<2 x double> %a)
67 declare float @llvm.aarch64.neon.vpfmaxnm.f32.v2f32(<2 x float>)
69 define float @test_fmaxnmp_f32(<2 x float> %a) {
70 ; CHECK: test_fmaxnmp_f32:
71 ; CHECK: fmaxnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
72 %val = call float @llvm.aarch64.neon.vpfmaxnm.f32.v2f32(<2 x float> %a)
76 declare double @llvm.aarch64.neon.vpfmaxnm.f64.v2f64(<2 x double>)
78 define double @test_fmaxnmp_f64(<2 x double> %a) {
79 ; CHECK: test_fmaxnmp_f64:
80 ; CHECK: fmaxnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
81 %val = call double @llvm.aarch64.neon.vpfmaxnm.f64.v2f64(<2 x double> %a)
85 declare float @llvm.aarch64.neon.vpfminnm.f32.v2f32(<2 x float>)
87 define float @test_fminnmp_f32(<2 x float> %a) {
88 ; CHECK: test_fminnmp_f32:
89 ; CHECK: fminnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
90 %val = call float @llvm.aarch64.neon.vpfminnm.f32.v2f32(<2 x float> %a)
94 declare double @llvm.aarch64.neon.vpfminnm.f64.v2f64(<2 x double>)
96 define double @test_fminnmp_f64(<2 x double> %a) {
97 ; CHECK: test_fminnmp_f64:
98 ; CHECK: fminnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
99 %val = call double @llvm.aarch64.neon.vpfminnm.f64.v2f64(<2 x double> %a)
103 define float @test_vaddv_f32(<2 x float> %a) {
104 ; CHECK-LABEL: test_vaddv_f32
105 ; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
106 %1 = call float @llvm.aarch64.neon.vpfadd.f32.v2f32(<2 x float> %a)
110 define float @test_vaddvq_f32(<4 x float> %a) {
111 ; CHECK-LABEL: test_vaddvq_f32
112 ; CHECK: faddp {{v[0-9]+}}.4s, {{v[0-9]+}}.4s, {{v[0-9]+}}.4s
113 ; CHECK: faddp {{s[0-9]+}}, {{v[0-9]+}}.2s
114 %1 = call float @llvm.aarch64.neon.vpfadd.f32.v4f32(<4 x float> %a)
118 define double @test_vaddvq_f64(<2 x double> %a) {
119 ; CHECK-LABEL: test_vaddvq_f64
120 ; CHECK: faddp {{d[0-9]+}}, {{v[0-9]+}}.2d
121 %1 = call double @llvm.aarch64.neon.vpfadd.f64.v2f64(<2 x double> %a)
125 define float @test_vmaxv_f32(<2 x float> %a) {
126 ; CHECK-LABEL: test_vmaxv_f32
127 ; CHECK: fmaxp {{s[0-9]+}}, {{v[0-9]+}}.2s
128 %1 = call float @llvm.aarch64.neon.vpmax.f32.v2f32(<2 x float> %a)
132 define double @test_vmaxvq_f64(<2 x double> %a) {
133 ; CHECK-LABEL: test_vmaxvq_f64
134 ; CHECK: fmaxp {{d[0-9]+}}, {{v[0-9]+}}.2d
135 %1 = call double @llvm.aarch64.neon.vpmax.f64.v2f64(<2 x double> %a)
139 define float @test_vminv_f32(<2 x float> %a) {
140 ; CHECK-LABEL: test_vminv_f32
141 ; CHECK: fminp {{s[0-9]+}}, {{v[0-9]+}}.2s
142 %1 = call float @llvm.aarch64.neon.vpmin.f32.v2f32(<2 x float> %a)
146 define double @test_vminvq_f64(<2 x double> %a) {
147 ; CHECK-LABEL: test_vminvq_f64
148 ; CHECK: fminp {{d[0-9]+}}, {{v[0-9]+}}.2d
149 %1 = call double @llvm.aarch64.neon.vpmin.f64.v2f64(<2 x double> %a)
153 define double @test_vmaxnmvq_f64(<2 x double> %a) {
154 ; CHECK-LABEL: test_vmaxnmvq_f64
155 ; CHECK: fmaxnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
156 %1 = call double @llvm.aarch64.neon.vpfmaxnm.f64.v2f64(<2 x double> %a)
160 define float @test_vmaxnmv_f32(<2 x float> %a) {
161 ; CHECK-LABEL: test_vmaxnmv_f32
162 ; CHECK: fmaxnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
163 %1 = call float @llvm.aarch64.neon.vpfmaxnm.f32.v2f32(<2 x float> %a)
167 define double @test_vminnmvq_f64(<2 x double> %a) {
168 ; CHECK-LABEL: test_vminnmvq_f64
169 ; CHECK: fminnmp {{d[0-9]+}}, {{v[0-9]+}}.2d
170 %1 = call double @llvm.aarch64.neon.vpfminnm.f64.v2f64(<2 x double> %a)
174 define float @test_vminnmv_f32(<2 x float> %a) {
175 ; CHECK-LABEL: test_vminnmv_f32
176 ; CHECK: fminnmp {{s[0-9]+}}, {{v[0-9]+}}.2s
177 %1 = call float @llvm.aarch64.neon.vpfminnm.f32.v2f32(<2 x float> %a)
181 define <2 x i64> @test_vpaddq_s64(<2 x i64> %a, <2 x i64> %b) {
182 ; CHECK-LABEL: test_vpaddq_s64
183 ; CHECK: addp {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
184 %1 = call <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64> %a, <2 x i64> %b)
188 define <2 x i64> @test_vpaddq_u64(<2 x i64> %a, <2 x i64> %b) {
189 ; CHECK-LABEL: test_vpaddq_u64
190 ; CHECK: addp {{v[0-9]+}}.2d, {{v[0-9]+}}.2d, {{v[0-9]+}}.2d
191 %1 = call <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64> %a, <2 x i64> %b)
195 define i64 @test_vaddvq_s64(<2 x i64> %a) {
196 ; CHECK-LABEL: test_vaddvq_s64
197 ; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
198 %1 = call <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64> %a)
199 %2 = extractelement <1 x i64> %1, i32 0
203 define i64 @test_vaddvq_u64(<2 x i64> %a) {
204 ; CHECK-LABEL: test_vaddvq_u64
205 ; CHECK: addp {{d[0-9]+}}, {{v[0-9]+}}.2d
206 %1 = call <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64> %a)
207 %2 = extractelement <1 x i64> %1, i32 0
211 declare <1 x i64> @llvm.aarch64.neon.vaddv.v1i64.v2i64(<2 x i64>)
213 declare <2 x i64> @llvm.arm.neon.vpadd.v2i64(<2 x i64>, <2 x i64>)
215 declare float @llvm.aarch64.neon.vpfadd.f32.v4f32(<4 x float>)