1 ; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon < %s | FileCheck %s
3 ;; Scalar Floating-point Compare
5 define i32 @test_vceqs_f32(float %a, float %b) {
6 ; CHECK: test_vceqs_f32
7 ; CHECK: fcmeq {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
9 %vceq.i = insertelement <1 x float> undef, float %a, i32 0
10 %vceq1.i = insertelement <1 x float> undef, float %b, i32 0
11 %vceq2.i = call <1 x i32> @llvm.aarch64.neon.vceq.v1i32.v1f32.v1f32(<1 x float> %vceq.i, <1 x float> %vceq1.i)
12 %0 = extractelement <1 x i32> %vceq2.i, i32 0
16 define i64 @test_vceqd_f64(double %a, double %b) {
17 ; CHECK: test_vceqd_f64
18 ; CHECK: fcmeq {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
20 %vceq.i = insertelement <1 x double> undef, double %a, i32 0
21 %vceq1.i = insertelement <1 x double> undef, double %b, i32 0
22 %vceq2.i = call <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f64(<1 x double> %vceq.i, <1 x double> %vceq1.i)
23 %0 = extractelement <1 x i64> %vceq2.i, i32 0
27 define <1 x i64> @test_vceqz_f64(<1 x double> %a) #0 {
28 ; CHECK: test_vceqz_f64
29 ; CHECK: fcmeq {{d[0-9]+}}, {{d[0-9]+}}, #0.0
31 %0 = fcmp oeq <1 x double> %a, zeroinitializer
32 %vceqz.i = zext <1 x i1> %0 to <1 x i64>
33 ret <1 x i64> %vceqz.i
36 define i32 @test_vceqzs_f32(float %a) {
37 ; CHECK: test_vceqzs_f32
38 ; CHECK: fcmeq {{s[0-9]}}, {{s[0-9]}}, #0.0
40 %vceq.i = insertelement <1 x float> undef, float %a, i32 0
41 %vceq1.i = call <1 x i32> @llvm.aarch64.neon.vceq.v1i32.v1f32.v1f32(<1 x float> %vceq.i, <1 x float> zeroinitializer)
42 %0 = extractelement <1 x i32> %vceq1.i, i32 0
46 define i64 @test_vceqzd_f64(double %a) {
47 ; CHECK: test_vceqzd_f64
48 ; CHECK: fcmeq {{d[0-9]}}, {{d[0-9]}}, #0.0
50 %vceq.i = insertelement <1 x double> undef, double %a, i32 0
51 %vceq1.i = tail call <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f32(<1 x double> %vceq.i, <1 x float> zeroinitializer) #5
52 %0 = extractelement <1 x i64> %vceq1.i, i32 0
56 define i32 @test_vcges_f32(float %a, float %b) {
57 ; CHECK: test_vcges_f32
58 ; CHECK: fcmge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
60 %vcge.i = insertelement <1 x float> undef, float %a, i32 0
61 %vcge1.i = insertelement <1 x float> undef, float %b, i32 0
62 %vcge2.i = call <1 x i32> @llvm.aarch64.neon.vcge.v1i32.v1f32.v1f32(<1 x float> %vcge.i, <1 x float> %vcge1.i)
63 %0 = extractelement <1 x i32> %vcge2.i, i32 0
67 define i64 @test_vcged_f64(double %a, double %b) {
68 ; CHECK: test_vcged_f64
69 ; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
71 %vcge.i = insertelement <1 x double> undef, double %a, i32 0
72 %vcge1.i = insertelement <1 x double> undef, double %b, i32 0
73 %vcge2.i = call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f64(<1 x double> %vcge.i, <1 x double> %vcge1.i)
74 %0 = extractelement <1 x i64> %vcge2.i, i32 0
78 define i32 @test_vcgezs_f32(float %a) {
79 ; CHECK: test_vcgezs_f32
80 ; CHECK: fcmge {{s[0-9]}}, {{s[0-9]}}, #0.0
82 %vcge.i = insertelement <1 x float> undef, float %a, i32 0
83 %vcge1.i = call <1 x i32> @llvm.aarch64.neon.vcge.v1i32.v1f32.v1f32(<1 x float> %vcge.i, <1 x float> zeroinitializer)
84 %0 = extractelement <1 x i32> %vcge1.i, i32 0
88 define i64 @test_vcgezd_f64(double %a) {
89 ; CHECK: test_vcgezd_f64
90 ; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, #0.0
92 %vcge.i = insertelement <1 x double> undef, double %a, i32 0
93 %vcge1.i = tail call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f32(<1 x double> %vcge.i, <1 x float> zeroinitializer) #5
94 %0 = extractelement <1 x i64> %vcge1.i, i32 0
98 define i32 @test_vcgts_f32(float %a, float %b) {
99 ; CHECK: test_vcgts_f32
100 ; CHECK: fcmgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
102 %vcgt.i = insertelement <1 x float> undef, float %a, i32 0
103 %vcgt1.i = insertelement <1 x float> undef, float %b, i32 0
104 %vcgt2.i = call <1 x i32> @llvm.aarch64.neon.vcgt.v1i32.v1f32.v1f32(<1 x float> %vcgt.i, <1 x float> %vcgt1.i)
105 %0 = extractelement <1 x i32> %vcgt2.i, i32 0
109 define i64 @test_vcgtd_f64(double %a, double %b) {
110 ; CHECK: test_vcgtd_f64
111 ; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
113 %vcgt.i = insertelement <1 x double> undef, double %a, i32 0
114 %vcgt1.i = insertelement <1 x double> undef, double %b, i32 0
115 %vcgt2.i = call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f64(<1 x double> %vcgt.i, <1 x double> %vcgt1.i)
116 %0 = extractelement <1 x i64> %vcgt2.i, i32 0
120 define i32 @test_vcgtzs_f32(float %a) {
121 ; CHECK: test_vcgtzs_f32
122 ; CHECK: fcmgt {{s[0-9]}}, {{s[0-9]}}, #0.0
124 %vcgt.i = insertelement <1 x float> undef, float %a, i32 0
125 %vcgt1.i = call <1 x i32> @llvm.aarch64.neon.vcgt.v1i32.v1f32.v1f32(<1 x float> %vcgt.i, <1 x float> zeroinitializer)
126 %0 = extractelement <1 x i32> %vcgt1.i, i32 0
130 define i64 @test_vcgtzd_f64(double %a) {
131 ; CHECK: test_vcgtzd_f64
132 ; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, #0.0
134 %vcgt.i = insertelement <1 x double> undef, double %a, i32 0
135 %vcgt1.i = tail call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f32(<1 x double> %vcgt.i, <1 x float> zeroinitializer) #5
136 %0 = extractelement <1 x i64> %vcgt1.i, i32 0
140 define i32 @test_vcles_f32(float %a, float %b) {
141 ; CHECK: test_vcles_f32
142 ; CHECK: fcmge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
144 %vcge.i = insertelement <1 x float> undef, float %a, i32 0
145 %vcge1.i = insertelement <1 x float> undef, float %b, i32 0
146 %vcge2.i = call <1 x i32> @llvm.aarch64.neon.vcge.v1i32.v1f32.v1f32(<1 x float> %vcge.i, <1 x float> %vcge1.i)
147 %0 = extractelement <1 x i32> %vcge2.i, i32 0
151 define i64 @test_vcled_f64(double %a, double %b) {
152 ; CHECK: test_vcled_f64
153 ; CHECK: fcmge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
155 %vcge.i = insertelement <1 x double> undef, double %a, i32 0
156 %vcge1.i = insertelement <1 x double> undef, double %b, i32 0
157 %vcge2.i = call <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f64(<1 x double> %vcge.i, <1 x double> %vcge1.i)
158 %0 = extractelement <1 x i64> %vcge2.i, i32 0
162 define i32 @test_vclezs_f32(float %a) {
163 ; CHECK: test_vclezs_f32
164 ; CHECK: fcmle {{s[0-9]}}, {{s[0-9]}}, #0.0
166 %vcle.i = insertelement <1 x float> undef, float %a, i32 0
167 %vcle1.i = call <1 x i32> @llvm.aarch64.neon.vclez.v1i32.v1f32.v1f32(<1 x float> %vcle.i, <1 x float> zeroinitializer)
168 %0 = extractelement <1 x i32> %vcle1.i, i32 0
172 define i64 @test_vclezd_f64(double %a) {
173 ; CHECK: test_vclezd_f64
174 ; CHECK: fcmle {{d[0-9]}}, {{d[0-9]}}, #0.0
176 %vcle.i = insertelement <1 x double> undef, double %a, i32 0
177 %vcle1.i = tail call <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1f64.v1f32(<1 x double> %vcle.i, <1 x float> zeroinitializer) #5
178 %0 = extractelement <1 x i64> %vcle1.i, i32 0
182 define i32 @test_vclts_f32(float %a, float %b) {
183 ; CHECK: test_vclts_f32
184 ; CHECK: fcmgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
186 %vcgt.i = insertelement <1 x float> undef, float %b, i32 0
187 %vcgt1.i = insertelement <1 x float> undef, float %a, i32 0
188 %vcgt2.i = call <1 x i32> @llvm.aarch64.neon.vcgt.v1i32.v1f32.v1f32(<1 x float> %vcgt.i, <1 x float> %vcgt1.i)
189 %0 = extractelement <1 x i32> %vcgt2.i, i32 0
193 define i64 @test_vcltd_f64(double %a, double %b) {
194 ; CHECK: test_vcltd_f64
195 ; CHECK: fcmgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
197 %vcgt.i = insertelement <1 x double> undef, double %b, i32 0
198 %vcgt1.i = insertelement <1 x double> undef, double %a, i32 0
199 %vcgt2.i = call <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f64(<1 x double> %vcgt.i, <1 x double> %vcgt1.i)
200 %0 = extractelement <1 x i64> %vcgt2.i, i32 0
204 define i32 @test_vcltzs_f32(float %a) {
205 ; CHECK: test_vcltzs_f32
206 ; CHECK: fcmlt {{s[0-9]}}, {{s[0-9]}}, #0.0
208 %vclt.i = insertelement <1 x float> undef, float %a, i32 0
209 %vclt1.i = call <1 x i32> @llvm.aarch64.neon.vcltz.v1i32.v1f32.v1f32(<1 x float> %vclt.i, <1 x float> zeroinitializer)
210 %0 = extractelement <1 x i32> %vclt1.i, i32 0
214 define i64 @test_vcltzd_f64(double %a) {
215 ; CHECK: test_vcltzd_f64
216 ; CHECK: fcmlt {{d[0-9]}}, {{d[0-9]}}, #0.0
218 %vclt.i = insertelement <1 x double> undef, double %a, i32 0
219 %vclt1.i = tail call <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1f64.v1f32(<1 x double> %vclt.i, <1 x float> zeroinitializer) #5
220 %0 = extractelement <1 x i64> %vclt1.i, i32 0
224 define i32 @test_vcages_f32(float %a, float %b) {
225 ; CHECK: test_vcages_f32
226 ; CHECK: facge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
228 %vcage.i = insertelement <1 x float> undef, float %a, i32 0
229 %vcage1.i = insertelement <1 x float> undef, float %b, i32 0
230 %vcage2.i = call <1 x i32> @llvm.aarch64.neon.vcage.v1i32.v1f32.v1f32(<1 x float> %vcage.i, <1 x float> %vcage1.i)
231 %0 = extractelement <1 x i32> %vcage2.i, i32 0
235 define i64 @test_vcaged_f64(double %a, double %b) {
236 ; CHECK: test_vcaged_f64
237 ; CHECK: facge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
239 %vcage.i = insertelement <1 x double> undef, double %a, i32 0
240 %vcage1.i = insertelement <1 x double> undef, double %b, i32 0
241 %vcage2.i = call <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double> %vcage.i, <1 x double> %vcage1.i)
242 %0 = extractelement <1 x i64> %vcage2.i, i32 0
246 define i32 @test_vcagts_f32(float %a, float %b) {
247 ; CHECK: test_vcagts_f32
248 ; CHECK: facgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
250 %vcagt.i = insertelement <1 x float> undef, float %a, i32 0
251 %vcagt1.i = insertelement <1 x float> undef, float %b, i32 0
252 %vcagt2.i = call <1 x i32> @llvm.aarch64.neon.vcagt.v1i32.v1f32.v1f32(<1 x float> %vcagt.i, <1 x float> %vcagt1.i)
253 %0 = extractelement <1 x i32> %vcagt2.i, i32 0
257 define i64 @test_vcagtd_f64(double %a, double %b) {
258 ; CHECK: test_vcagtd_f64
259 ; CHECK: facgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
261 %vcagt.i = insertelement <1 x double> undef, double %a, i32 0
262 %vcagt1.i = insertelement <1 x double> undef, double %b, i32 0
263 %vcagt2.i = call <1 x i64> @llvm.aarch64.neon.vcagt.v1i64.v1f64.v1f64(<1 x double> %vcagt.i, <1 x double> %vcagt1.i)
264 %0 = extractelement <1 x i64> %vcagt2.i, i32 0
268 define i32 @test_vcales_f32(float %a, float %b) {
269 ; CHECK: test_vcales_f32
270 ; CHECK: facge {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
272 %vcage.i = insertelement <1 x float> undef, float %b, i32 0
273 %vcage1.i = insertelement <1 x float> undef, float %a, i32 0
274 %vcage2.i = call <1 x i32> @llvm.aarch64.neon.vcage.v1i32.v1f32.v1f32(<1 x float> %vcage.i, <1 x float> %vcage1.i)
275 %0 = extractelement <1 x i32> %vcage2.i, i32 0
279 define i64 @test_vcaled_f64(double %a, double %b) {
280 ; CHECK: test_vcaled_f64
281 ; CHECK: facge {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
283 %vcage.i = insertelement <1 x double> undef, double %b, i32 0
284 %vcage1.i = insertelement <1 x double> undef, double %a, i32 0
285 %vcage2.i = call <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double> %vcage.i, <1 x double> %vcage1.i)
286 %0 = extractelement <1 x i64> %vcage2.i, i32 0
290 define i32 @test_vcalts_f32(float %a, float %b) {
291 ; CHECK: test_vcalts_f32
292 ; CHECK: facgt {{s[0-9]}}, {{s[0-9]}}, {{s[0-9]}}
294 %vcalt.i = insertelement <1 x float> undef, float %b, i32 0
295 %vcalt1.i = insertelement <1 x float> undef, float %a, i32 0
296 %vcalt2.i = call <1 x i32> @llvm.aarch64.neon.vcagt.v1i32.v1f32.v1f32(<1 x float> %vcalt.i, <1 x float> %vcalt1.i)
297 %0 = extractelement <1 x i32> %vcalt2.i, i32 0
301 define i64 @test_vcaltd_f64(double %a, double %b) {
302 ; CHECK: test_vcaltd_f64
303 ; CHECK: facgt {{d[0-9]}}, {{d[0-9]}}, {{d[0-9]}}
305 %vcalt.i = insertelement <1 x double> undef, double %b, i32 0
306 %vcalt1.i = insertelement <1 x double> undef, double %a, i32 0
307 %vcalt2.i = call <1 x i64> @llvm.aarch64.neon.vcagt.v1i64.v1f64.v1f64(<1 x double> %vcalt.i, <1 x double> %vcalt1.i)
308 %0 = extractelement <1 x i64> %vcalt2.i, i32 0
312 declare <1 x i32> @llvm.aarch64.neon.vceq.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
313 declare <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)
314 declare <1 x i64> @llvm.aarch64.neon.vceq.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
315 declare <1 x i32> @llvm.aarch64.neon.vcge.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
316 declare <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)
317 declare <1 x i64> @llvm.aarch64.neon.vcge.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
318 declare <1 x i32> @llvm.aarch64.neon.vclez.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
319 declare <1 x i64> @llvm.aarch64.neon.vclez.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)
320 declare <1 x i32> @llvm.aarch64.neon.vcgt.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
321 declare <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)
322 declare <1 x i64> @llvm.aarch64.neon.vcgt.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
323 declare <1 x i32> @llvm.aarch64.neon.vcltz.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
324 declare <1 x i64> @llvm.aarch64.neon.vcltz.v1i64.v1f64.v1f32(<1 x double>, <1 x float>)
325 declare <1 x i32> @llvm.aarch64.neon.vcage.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
326 declare <1 x i64> @llvm.aarch64.neon.vcage.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)
327 declare <1 x i32> @llvm.aarch64.neon.vcagt.v1i32.v1f32.v1f32(<1 x float>, <1 x float>)
328 declare <1 x i64> @llvm.aarch64.neon.vcagt.v1i64.v1f64.v1f64(<1 x double>, <1 x double>)