1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-AARCH64
2 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-ARM64
4 define <8 x i8> @movi8b() {
6 ; CHECK: movi {{v[0-9]+}}.8b, #{{0x8|8}}
7 ret <8 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
10 define <16 x i8> @movi16b() {
11 ; CHECK-LABEL: movi16b:
12 ; CHECK: movi {{v[0-9]+}}.16b, #{{0x8|8}}
13 ret <16 x i8> < i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8 >
16 define <2 x i32> @movi2s_lsl0() {
17 ; CHECK-LABEL: movi2s_lsl0:
18 ; CHECK-AARCH64: movi {{v[0-9]+}}.2s, #0xff
19 ; CHECK-ARM64: movi {{d[0-9]+}}, #0x0000ff000000ff
20 ret <2 x i32> < i32 255, i32 255 >
23 define <2 x i32> @movi2s_lsl8() {
24 ; CHECK-LABEL: movi2s_lsl8:
25 ; CHECK-AARCH64: movi {{v[0-9]+}}.2s, #0xff, lsl #8
26 ; CHECK-ARM64: movi {{d[0-9]+}}, #0x00ff000000ff00
27 ret <2 x i32> < i32 65280, i32 65280 >
30 define <2 x i32> @movi2s_lsl16() {
31 ; CHECK-LABEL: movi2s_lsl16:
32 ; CHECK-AARCH64: movi {{v[0-9]+}}.2s, #0xff, lsl #16
33 ; CHECK-ARM64: movi {{d[0-9]+}}, #0xff000000ff0000
34 ret <2 x i32> < i32 16711680, i32 16711680 >
38 define <2 x i32> @movi2s_lsl24() {
39 ; CHECK-LABEL: movi2s_lsl24:
40 ; CHECK-AARCH64: movi {{v[0-9]+}}.2s, #0xff, lsl #24
41 ; CHECK-ARM64: movi {{d[0-9]+}}, #0xff000000ff000000
42 ret <2 x i32> < i32 4278190080, i32 4278190080 >
45 define <4 x i32> @movi4s_lsl0() {
46 ; CHECK-LABEL: movi4s_lsl0:
47 ; CHECK-AARCH64: movi {{v[0-9]+}}.4s, #0xff
48 ; CHECK-ARM64: movi {{v[0-9]+}}.2d, #0x0000ff000000ff
49 ret <4 x i32> < i32 255, i32 255, i32 255, i32 255 >
52 define <4 x i32> @movi4s_lsl8() {
53 ; CHECK-LABEL: movi4s_lsl8:
54 ; CHECK-AARCH64: movi {{v[0-9]+}}.4s, #0xff, lsl #8
55 ; CHECK-ARM64: movi {{v[0-9]+}}.2d, #0x00ff000000ff00
56 ret <4 x i32> < i32 65280, i32 65280, i32 65280, i32 65280 >
59 define <4 x i32> @movi4s_lsl16() {
60 ; CHECK-LABEL: movi4s_lsl16:
61 ; CHECK-AARCH64: movi {{v[0-9]+}}.4s, #0xff, lsl #16
62 ; CHECK-ARM64: movi {{v[0-9]+}}.2d, #0xff000000ff0000
63 ret <4 x i32> < i32 16711680, i32 16711680, i32 16711680, i32 16711680 >
67 define <4 x i32> @movi4s_lsl24() {
68 ; CHECK-LABEL: movi4s_lsl24:
69 ; CHECK-AARCH64: movi {{v[0-9]+}}.4s, #0xff, lsl #24
70 ; CHECK-ARM64: movi {{v[0-9]+}}.2d, #0xff000000ff000000
71 ret <4 x i32> < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080 >
74 define <4 x i16> @movi4h_lsl0() {
75 ; CHECK-LABEL: movi4h_lsl0:
76 ; CHECK-AARCH64: movi {{v[0-9]+}}.4h, #0xff
77 ; CHECK-ARM64: movi {{d[0-9]+}}, #0xff00ff00ff00ff
78 ret <4 x i16> < i16 255, i16 255, i16 255, i16 255 >
81 define <4 x i16> @movi4h_lsl8() {
82 ; CHECK-LABEL: movi4h_lsl8:
83 ; CHECK-AARCH64: movi {{v[0-9]+}}.4h, #{{0xff|255}}, lsl #8
84 ; CHECK-ARM64: movi d0, #0xff00ff00ff00ff00
85 ret <4 x i16> < i16 65280, i16 65280, i16 65280, i16 65280 >
88 define <8 x i16> @movi8h_lsl0() {
89 ; CHECK-LABEL: movi8h_lsl0:
90 ; CHECK-AARCH64: movi {{v[0-9]+}}.8h, #{{0xff|255}}
91 ; CHECK-ARM64: movi v0.2d, #0xff00ff00ff00ff
92 ret <8 x i16> < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
95 define <8 x i16> @movi8h_lsl8() {
96 ; CHECK-LABEL: movi8h_lsl8:
97 ; CHECK-AARCH64: movi {{v[0-9]+}}.8h, #{{0xff|255}}, lsl #8
98 ; CHECK-ARM64: movi v0.2d, #0xff00ff00ff00ff00
99 ret <8 x i16> < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
103 define <2 x i32> @mvni2s_lsl0() {
104 ; CHECK-LABEL: mvni2s_lsl0:
105 ; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}
106 ret <2 x i32> < i32 4294967279, i32 4294967279 >
109 define <2 x i32> @mvni2s_lsl8() {
110 ; CHECK-LABEL: mvni2s_lsl8:
111 ; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #8
112 ret <2 x i32> < i32 4294963199, i32 4294963199 >
115 define <2 x i32> @mvni2s_lsl16() {
116 ; CHECK-LABEL: mvni2s_lsl16:
117 ; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #16
118 ret <2 x i32> < i32 4293918719, i32 4293918719 >
121 define <2 x i32> @mvni2s_lsl24() {
122 ; CHECK-LABEL: mvni2s_lsl24:
123 ; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}, lsl #24
124 ret <2 x i32> < i32 4026531839, i32 4026531839 >
127 define <4 x i32> @mvni4s_lsl0() {
128 ; CHECK-LABEL: mvni4s_lsl0:
129 ; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}
130 ret <4 x i32> < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
133 define <4 x i32> @mvni4s_lsl8() {
134 ; CHECK-LABEL: mvni4s_lsl8:
135 ; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #8
136 ret <4 x i32> < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
139 define <4 x i32> @mvni4s_lsl16() {
140 ; CHECK-LABEL: mvni4s_lsl16:
141 ; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #16
142 ret <4 x i32> < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
146 define <4 x i32> @mvni4s_lsl24() {
147 ; CHECK-LABEL: mvni4s_lsl24:
148 ; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}, lsl #24
149 ret <4 x i32> < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839 >
153 define <4 x i16> @mvni4h_lsl0() {
154 ; CHECK-LABEL: mvni4h_lsl0:
155 ; CHECK: mvni {{v[0-9]+}}.4h, #{{0x10|16}}
156 ret <4 x i16> < i16 65519, i16 65519, i16 65519, i16 65519 >
159 define <4 x i16> @mvni4h_lsl8() {
160 ; CHECK-LABEL: mvni4h_lsl8:
161 ; CHECK: mvni {{v[0-9]+}}.4h, #{{0x10|16}}, lsl #8
162 ret <4 x i16> < i16 61439, i16 61439, i16 61439, i16 61439 >
165 define <8 x i16> @mvni8h_lsl0() {
166 ; CHECK-LABEL: mvni8h_lsl0:
167 ; CHECK: mvni {{v[0-9]+}}.8h, #{{0x10|16}}
168 ret <8 x i16> < i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519, i16 65519 >
171 define <8 x i16> @mvni8h_lsl8() {
172 ; CHECK-LABEL: mvni8h_lsl8:
173 ; CHECK: mvni {{v[0-9]+}}.8h, #{{0x10|16}}, lsl #8
174 ret <8 x i16> < i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439, i16 61439 >
178 define <2 x i32> @movi2s_msl8(<2 x i32> %a) {
179 ; CHECK-LABEL: movi2s_msl8:
180 ; CHECK-AARCH64: movi {{v[0-9]+}}.2s, #0xff, msl #8
181 ; CHECK-ARM64: movi {{d[0-9]+}}, #0x00ffff0000ffff
182 ret <2 x i32> < i32 65535, i32 65535 >
185 define <2 x i32> @movi2s_msl16() {
186 ; CHECK-LABEL: movi2s_msl16:
187 ; CHECK-AARCH64: movi {{v[0-9]+}}.2s, #0xff, msl #16
188 ; CHECK-ARM64: movi d0, #0xffffff00ffffff
189 ret <2 x i32> < i32 16777215, i32 16777215 >
193 define <4 x i32> @movi4s_msl8() {
194 ; CHECK-LABEL: movi4s_msl8:
195 ; CHECK-AARCH64: movi {{v[0-9]+}}.4s, #0xff, msl #8
196 ; CHECK-ARM64: movi v0.2d, #0x00ffff0000ffff
197 ret <4 x i32> < i32 65535, i32 65535, i32 65535, i32 65535 >
200 define <4 x i32> @movi4s_msl16() {
201 ; CHECK-LABEL: movi4s_msl16:
202 ; CHECK-AARCH64: movi {{v[0-9]+}}.4s, #0xff, msl #16
203 ; CHECK-ARM64: movi v0.2d, #0xffffff00ffffff
204 ret <4 x i32> < i32 16777215, i32 16777215, i32 16777215, i32 16777215 >
207 define <2 x i32> @mvni2s_msl8() {
208 ; CHECK-LABEL: mvni2s_msl8:
209 ; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}, msl #8
210 ret <2 x i32> < i32 18446744073709547264, i32 18446744073709547264>
213 define <2 x i32> @mvni2s_msl16() {
214 ; CHECK-LABEL: mvni2s_msl16:
215 ; CHECK: mvni {{v[0-9]+}}.2s, #{{0x10|16}}, msl #16
216 ret <2 x i32> < i32 18446744073708437504, i32 18446744073708437504>
219 define <4 x i32> @mvni4s_msl8() {
220 ; CHECK-LABEL: mvni4s_msl8:
221 ; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}, msl #8
222 ret <4 x i32> < i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264, i32 18446744073709547264>
225 define <4 x i32> @mvni4s_msl16() {
226 ; CHECK-LABEL: mvni4s_msl16:
227 ; CHECK: mvni {{v[0-9]+}}.4s, #{{0x10|16}}, msl #16
228 ret <4 x i32> < i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504, i32 18446744073708437504>
231 define <2 x i64> @movi2d() {
232 ; CHECK-LABEL: movi2d:
233 ; CHECK: movi {{v[0-9]+}}.2d, #0xff0000ff0000ffff
234 ret <2 x i64> < i64 18374687574888349695, i64 18374687574888349695 >
237 define <1 x i64> @movid() {
238 ; CHECK-LABEL: movid:
239 ; CHECK: movi {{d[0-9]+}}, #0xff0000ff0000ffff
240 ret <1 x i64> < i64 18374687574888349695 >
243 define <2 x float> @fmov2s() {
244 ; CHECK-LABEL: fmov2s:
245 ; CHECK: fmov {{v[0-9]+}}.2s, #{{-12.00000000|-1.200000e\+01}}
246 ret <2 x float> < float -1.2e1, float -1.2e1>
249 define <4 x float> @fmov4s() {
250 ; CHECK-LABEL: fmov4s:
251 ; CHECK: fmov {{v[0-9]+}}.4s, #{{-12.00000000|-1.200000e\+01}}
252 ret <4 x float> < float -1.2e1, float -1.2e1, float -1.2e1, float -1.2e1>
255 define <2 x double> @fmov2d() {
256 ; CHECK-LABEL: fmov2d:
257 ; CHECK: fmov {{v[0-9]+}}.2d, #{{-12.00000000|-1.200000e\+01}}
258 ret <2 x double> < double -1.2e1, double -1.2e1>
261 define <2 x i32> @movi1d_1() {
262 ; CHECK-LABEL: movi1d_1:
263 ; CHECK: movi d0, #0x{{0*}}ffffffff0000
264 ret <2 x i32> < i32 -65536, i32 65535>
268 declare <2 x i32> @test_movi1d(<2 x i32>, <2 x i32>)
269 define <2 x i32> @movi1d() {
270 ; CHECK-LABEL: movi1d:
271 ; CHECK: adrp {{x[0-9]+}}, .{{[A-Z0-9_]+}}
272 ; CHECK: ldr {{d[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:.{{[A-Z0-9_]+}}]
273 ; CHECK-NEXT: movi d1, #0x{{0*}}ffffffff0000
274 %1 = tail call <2 x i32> @test_movi1d(<2 x i32> <i32 -2147483648, i32 2147450880>, <2 x i32> <i32 -65536, i32 65535>)