1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
4 define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) {
5 ;CHECK: ins {{v[0-31]+}}.b[15], {{w[0-31]+}}
6 %tmp3 = insertelement <16 x i8> %tmp1, i8 %tmp2, i32 15
10 define <8 x i16> @ins8hw(<8 x i16> %tmp1, i16 %tmp2) {
11 ;CHECK: ins {{v[0-31]+}}.h[6], {{w[0-31]+}}
12 %tmp3 = insertelement <8 x i16> %tmp1, i16 %tmp2, i32 6
16 define <4 x i32> @ins4sw(<4 x i32> %tmp1, i32 %tmp2) {
17 ;CHECK: ins {{v[0-31]+}}.s[2], {{w[0-31]+}}
18 %tmp3 = insertelement <4 x i32> %tmp1, i32 %tmp2, i32 2
22 define <2 x i64> @ins2dw(<2 x i64> %tmp1, i64 %tmp2) {
23 ;CHECK: ins {{v[0-31]+}}.d[1], {{x[0-31]+}}
24 %tmp3 = insertelement <2 x i64> %tmp1, i64 %tmp2, i32 1
28 define <8 x i8> @ins8bw(<8 x i8> %tmp1, i8 %tmp2) {
29 ;CHECK: ins {{v[0-31]+}}.b[5], {{w[0-31]+}}
30 %tmp3 = insertelement <8 x i8> %tmp1, i8 %tmp2, i32 5
34 define <4 x i16> @ins4hw(<4 x i16> %tmp1, i16 %tmp2) {
35 ;CHECK: ins {{v[0-31]+}}.h[3], {{w[0-31]+}}
36 %tmp3 = insertelement <4 x i16> %tmp1, i16 %tmp2, i32 3
40 define <2 x i32> @ins2sw(<2 x i32> %tmp1, i32 %tmp2) {
41 ;CHECK: ins {{v[0-31]+}}.s[1], {{w[0-31]+}}
42 %tmp3 = insertelement <2 x i32> %tmp1, i32 %tmp2, i32 1
46 define <16 x i8> @ins16b16(<16 x i8> %tmp1, <16 x i8> %tmp2) {
47 ;CHECK: ins {{v[0-31]+}}.b[15], {{v[0-31]+}}.b[2]
48 %tmp3 = extractelement <16 x i8> %tmp1, i32 2
49 %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
53 define <8 x i16> @ins8h8(<8 x i16> %tmp1, <8 x i16> %tmp2) {
54 ;CHECK: ins {{v[0-31]+}}.h[7], {{v[0-31]+}}.h[2]
55 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
56 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
60 define <4 x i32> @ins4s4(<4 x i32> %tmp1, <4 x i32> %tmp2) {
61 ;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[2]
62 %tmp3 = extractelement <4 x i32> %tmp1, i32 2
63 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
67 define <2 x i64> @ins2d2(<2 x i64> %tmp1, <2 x i64> %tmp2) {
68 ;CHECK: ins {{v[0-31]+}}.d[1], {{v[0-31]+}}.d[0]
69 %tmp3 = extractelement <2 x i64> %tmp1, i32 0
70 %tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
74 define <4 x float> @ins4f4(<4 x float> %tmp1, <4 x float> %tmp2) {
75 ;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[2]
76 %tmp3 = extractelement <4 x float> %tmp1, i32 2
77 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
81 define <2 x double> @ins2df2(<2 x double> %tmp1, <2 x double> %tmp2) {
82 ;CHECK: ins {{v[0-31]+}}.d[1], {{v[0-31]+}}.d[0]
83 %tmp3 = extractelement <2 x double> %tmp1, i32 0
84 %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
85 ret <2 x double> %tmp4
88 define <16 x i8> @ins8b16(<8 x i8> %tmp1, <16 x i8> %tmp2) {
89 ;CHECK: ins {{v[0-31]+}}.b[15], {{v[0-31]+}}.b[2]
90 %tmp3 = extractelement <8 x i8> %tmp1, i32 2
91 %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15
95 define <8 x i16> @ins4h8(<4 x i16> %tmp1, <8 x i16> %tmp2) {
96 ;CHECK: ins {{v[0-31]+}}.h[7], {{v[0-31]+}}.h[2]
97 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
98 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7
102 define <4 x i32> @ins2s4(<2 x i32> %tmp1, <4 x i32> %tmp2) {
103 ;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[1]
104 %tmp3 = extractelement <2 x i32> %tmp1, i32 1
105 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1
109 define <2 x i64> @ins1d2(<1 x i64> %tmp1, <2 x i64> %tmp2) {
110 ;CHECK: ins {{v[0-31]+}}.d[1], {{v[0-31]+}}.d[0]
111 %tmp3 = extractelement <1 x i64> %tmp1, i32 0
112 %tmp4 = insertelement <2 x i64> %tmp2, i64 %tmp3, i32 1
116 define <4 x float> @ins2f4(<2 x float> %tmp1, <4 x float> %tmp2) {
117 ;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[1]
118 %tmp3 = extractelement <2 x float> %tmp1, i32 1
119 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1
120 ret <4 x float> %tmp4
123 define <2 x double> @ins1f2(<1 x double> %tmp1, <2 x double> %tmp2) {
124 ;CHECK: ins {{v[0-31]+}}.d[1], {{v[0-31]+}}.d[0]
125 %tmp3 = extractelement <1 x double> %tmp1, i32 0
126 %tmp4 = insertelement <2 x double> %tmp2, double %tmp3, i32 1
127 ret <2 x double> %tmp4
130 define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) {
131 ;CHECK: ins {{v[0-31]+}}.b[7], {{v[0-31]+}}.b[2]
132 %tmp3 = extractelement <16 x i8> %tmp1, i32 2
133 %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 7
137 define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) {
138 ;CHECK: ins {{v[0-31]+}}.h[3], {{v[0-31]+}}.h[2]
139 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
140 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
144 define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) {
145 ;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[2]
146 %tmp3 = extractelement <4 x i32> %tmp1, i32 2
147 %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
151 define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) {
152 ;CHECK: ins {{v[0-31]+}}.d[0], {{v[0-31]+}}.d[0]
153 %tmp3 = extractelement <2 x i64> %tmp1, i32 0
154 %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
158 define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) {
159 ;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[2]
160 %tmp3 = extractelement <4 x float> %tmp1, i32 2
161 %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
162 ret <2 x float> %tmp4
165 define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) {
166 ;CHECK: ins {{v[0-31]+}}.d[0], {{v[0-31]+}}.d[0]
167 %tmp3 = extractelement <2 x double> %tmp1, i32 0
168 %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
169 ret <1 x double> %tmp4
172 define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) {
173 ;CHECK: ins {{v[0-31]+}}.b[4], {{v[0-31]+}}.b[2]
174 %tmp3 = extractelement <8 x i8> %tmp1, i32 2
175 %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 4
179 define <4 x i16> @ins4h4(<4 x i16> %tmp1, <4 x i16> %tmp2) {
180 ;CHECK: ins {{v[0-31]+}}.h[3], {{v[0-31]+}}.h[2]
181 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
182 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3
186 define <2 x i32> @ins2s2(<2 x i32> %tmp1, <2 x i32> %tmp2) {
187 ;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[0]
188 %tmp3 = extractelement <2 x i32> %tmp1, i32 0
189 %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1
193 define <1 x i64> @ins1d1(<1 x i64> %tmp1, <1 x i64> %tmp2) {
194 ;CHECK: ins {{v[0-31]+}}.d[0], {{v[0-31]+}}.d[0]
195 %tmp3 = extractelement <1 x i64> %tmp1, i32 0
196 %tmp4 = insertelement <1 x i64> %tmp2, i64 %tmp3, i32 0
200 define <2 x float> @ins2f2(<2 x float> %tmp1, <2 x float> %tmp2) {
201 ;CHECK: ins {{v[0-31]+}}.s[1], {{v[0-31]+}}.s[0]
202 %tmp3 = extractelement <2 x float> %tmp1, i32 0
203 %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1
204 ret <2 x float> %tmp4
207 define <1 x double> @ins1df1(<1 x double> %tmp1, <1 x double> %tmp2) {
208 ;CHECK: ins {{v[0-31]+}}.d[0], {{v[0-31]+}}.d[0]
209 %tmp3 = extractelement <1 x double> %tmp1, i32 0
210 %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0
211 ret <1 x double> %tmp4
214 define i32 @umovw16b(<16 x i8> %tmp1) {
215 ;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.b[8]
216 %tmp3 = extractelement <16 x i8> %tmp1, i32 8
217 %tmp4 = zext i8 %tmp3 to i32
221 define i32 @umovw8h(<8 x i16> %tmp1) {
222 ;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.h[2]
223 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
224 %tmp4 = zext i16 %tmp3 to i32
228 define i32 @umovw4s(<4 x i32> %tmp1) {
229 ;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.s[2]
230 %tmp3 = extractelement <4 x i32> %tmp1, i32 2
234 define i64 @umovx2d(<2 x i64> %tmp1) {
235 ;CHECK: umov {{x[0-31]+}}, {{v[0-31]+}}.d[0]
236 %tmp3 = extractelement <2 x i64> %tmp1, i32 0
240 define i32 @umovw8b(<8 x i8> %tmp1) {
241 ;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.b[7]
242 %tmp3 = extractelement <8 x i8> %tmp1, i32 7
243 %tmp4 = zext i8 %tmp3 to i32
247 define i32 @umovw4h(<4 x i16> %tmp1) {
248 ;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.h[2]
249 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
250 %tmp4 = zext i16 %tmp3 to i32
254 define i32 @umovw2s(<2 x i32> %tmp1) {
255 ;CHECK: umov {{w[0-31]+}}, {{v[0-31]+}}.s[1]
256 %tmp3 = extractelement <2 x i32> %tmp1, i32 1
260 define i64 @umovx1d(<1 x i64> %tmp1) {
261 ;CHECK: fmov {{x[0-31]+}}, {{d[0-31]+}}
262 %tmp3 = extractelement <1 x i64> %tmp1, i32 0
266 define i32 @smovw16b(<16 x i8> %tmp1) {
267 ;CHECK: smov {{w[0-31]+}}, {{v[0-31]+}}.b[8]
268 %tmp3 = extractelement <16 x i8> %tmp1, i32 8
269 %tmp4 = sext i8 %tmp3 to i32
270 %tmp5 = add i32 5, %tmp4
274 define i32 @smovw8h(<8 x i16> %tmp1) {
275 ;CHECK: smov {{w[0-31]+}}, {{v[0-31]+}}.h[2]
276 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
277 %tmp4 = sext i16 %tmp3 to i32
278 %tmp5 = add i32 5, %tmp4
282 define i32 @smovx16b(<16 x i8> %tmp1) {
283 ;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.b[8]
284 %tmp3 = extractelement <16 x i8> %tmp1, i32 8
285 %tmp4 = sext i8 %tmp3 to i32
289 define i32 @smovx8h(<8 x i16> %tmp1) {
290 ;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.h[2]
291 %tmp3 = extractelement <8 x i16> %tmp1, i32 2
292 %tmp4 = sext i16 %tmp3 to i32
296 define i64 @smovx4s(<4 x i32> %tmp1) {
297 ;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.s[2]
298 %tmp3 = extractelement <4 x i32> %tmp1, i32 2
299 %tmp4 = sext i32 %tmp3 to i64
303 define i32 @smovw8b(<8 x i8> %tmp1) {
304 ;CHECK: smov {{w[0-31]+}}, {{v[0-31]+}}.b[4]
305 %tmp3 = extractelement <8 x i8> %tmp1, i32 4
306 %tmp4 = sext i8 %tmp3 to i32
307 %tmp5 = add i32 5, %tmp4
311 define i32 @smovw4h(<4 x i16> %tmp1) {
312 ;CHECK: smov {{w[0-31]+}}, {{v[0-31]+}}.h[2]
313 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
314 %tmp4 = sext i16 %tmp3 to i32
315 %tmp5 = add i32 5, %tmp4
319 define i32 @smovx8b(<8 x i8> %tmp1) {
320 ;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.b[6]
321 %tmp3 = extractelement <8 x i8> %tmp1, i32 6
322 %tmp4 = sext i8 %tmp3 to i32
326 define i32 @smovx4h(<4 x i16> %tmp1) {
327 ;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.h[2]
328 %tmp3 = extractelement <4 x i16> %tmp1, i32 2
329 %tmp4 = sext i16 %tmp3 to i32
333 define i64 @smovx2s(<2 x i32> %tmp1) {
334 ;CHECK: smov {{x[0-31]+}}, {{v[0-31]+}}.s[1]
335 %tmp3 = extractelement <2 x i32> %tmp1, i32 1
336 %tmp4 = sext i32 %tmp3 to i64
340 define <8 x i8> @test_vcopy_lane_s8(<8 x i8> %v1, <8 x i8> %v2) {
341 ;CHECK: ins {{v[0-9]+}}.b[5], {{v[0-9]+}}.b[3]
342 %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 11, i32 6, i32 7>
343 ret <8 x i8> %vset_lane
346 define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> %v1, <16 x i8> %v2) {
347 ;CHECK: ins {{v[0-9]+}}.b[14], {{v[0-9]+}}.b[6]
348 %vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 22, i32 15>
349 ret <16 x i8> %vset_lane
352 define <8 x i8> @test_vcopy_lane_swap_s8(<8 x i8> %v1, <8 x i8> %v2) {
353 ;CHECK: ins {{v[0-9]+}}.b[7], {{v[0-9]+}}.b[0]
354 %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 0>
355 ret <8 x i8> %vset_lane
358 define <16 x i8> @test_vcopyq_laneq_swap_s8(<16 x i8> %v1, <16 x i8> %v2) {
359 ;CHECK: ins {{v[0-9]+}}.b[0], {{v[0-9]+}}.b[15]
360 %vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> <i32 15, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31>
361 ret <16 x i8> %vset_lane
364 define <8 x i8> @test_vdup_n_u8(i8 %v1) #0 {
365 ;CHECK: dup {{v[0-9]+}}.8b, {{w[0-9]+}}
366 %vecinit.i = insertelement <8 x i8> undef, i8 %v1, i32 0
367 %vecinit1.i = insertelement <8 x i8> %vecinit.i, i8 %v1, i32 1
368 %vecinit2.i = insertelement <8 x i8> %vecinit1.i, i8 %v1, i32 2
369 %vecinit3.i = insertelement <8 x i8> %vecinit2.i, i8 %v1, i32 3
370 %vecinit4.i = insertelement <8 x i8> %vecinit3.i, i8 %v1, i32 4
371 %vecinit5.i = insertelement <8 x i8> %vecinit4.i, i8 %v1, i32 5
372 %vecinit6.i = insertelement <8 x i8> %vecinit5.i, i8 %v1, i32 6
373 %vecinit7.i = insertelement <8 x i8> %vecinit6.i, i8 %v1, i32 7
374 ret <8 x i8> %vecinit7.i
377 define <4 x i16> @test_vdup_n_u16(i16 %v1) #0 {
378 ;CHECK: dup {{v[0-9]+}}.4h, {{w[0-9]+}}
379 %vecinit.i = insertelement <4 x i16> undef, i16 %v1, i32 0
380 %vecinit1.i = insertelement <4 x i16> %vecinit.i, i16 %v1, i32 1
381 %vecinit2.i = insertelement <4 x i16> %vecinit1.i, i16 %v1, i32 2
382 %vecinit3.i = insertelement <4 x i16> %vecinit2.i, i16 %v1, i32 3
383 ret <4 x i16> %vecinit3.i
386 define <2 x i32> @test_vdup_n_u32(i32 %v1) #0 {
387 ;CHECK: dup {{v[0-9]+}}.2s, {{w[0-9]+}}
388 %vecinit.i = insertelement <2 x i32> undef, i32 %v1, i32 0
389 %vecinit1.i = insertelement <2 x i32> %vecinit.i, i32 %v1, i32 1
390 ret <2 x i32> %vecinit1.i
393 define <1 x i64> @test_vdup_n_u64(i64 %v1) #0 {
394 ;CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
395 %vecinit.i = insertelement <1 x i64> undef, i64 %v1, i32 0
396 ret <1 x i64> %vecinit.i
399 define <16 x i8> @test_vdupq_n_u8(i8 %v1) #0 {
400 ;CHECK: dup {{v[0-9]+}}.16b, {{w[0-9]+}}
401 %vecinit.i = insertelement <16 x i8> undef, i8 %v1, i32 0
402 %vecinit1.i = insertelement <16 x i8> %vecinit.i, i8 %v1, i32 1
403 %vecinit2.i = insertelement <16 x i8> %vecinit1.i, i8 %v1, i32 2
404 %vecinit3.i = insertelement <16 x i8> %vecinit2.i, i8 %v1, i32 3
405 %vecinit4.i = insertelement <16 x i8> %vecinit3.i, i8 %v1, i32 4
406 %vecinit5.i = insertelement <16 x i8> %vecinit4.i, i8 %v1, i32 5
407 %vecinit6.i = insertelement <16 x i8> %vecinit5.i, i8 %v1, i32 6
408 %vecinit7.i = insertelement <16 x i8> %vecinit6.i, i8 %v1, i32 7
409 %vecinit8.i = insertelement <16 x i8> %vecinit7.i, i8 %v1, i32 8
410 %vecinit9.i = insertelement <16 x i8> %vecinit8.i, i8 %v1, i32 9
411 %vecinit10.i = insertelement <16 x i8> %vecinit9.i, i8 %v1, i32 10
412 %vecinit11.i = insertelement <16 x i8> %vecinit10.i, i8 %v1, i32 11
413 %vecinit12.i = insertelement <16 x i8> %vecinit11.i, i8 %v1, i32 12
414 %vecinit13.i = insertelement <16 x i8> %vecinit12.i, i8 %v1, i32 13
415 %vecinit14.i = insertelement <16 x i8> %vecinit13.i, i8 %v1, i32 14
416 %vecinit15.i = insertelement <16 x i8> %vecinit14.i, i8 %v1, i32 15
417 ret <16 x i8> %vecinit15.i
420 define <8 x i16> @test_vdupq_n_u16(i16 %v1) #0 {
421 ;CHECK: dup {{v[0-9]+}}.8h, {{w[0-9]+}}
422 %vecinit.i = insertelement <8 x i16> undef, i16 %v1, i32 0
423 %vecinit1.i = insertelement <8 x i16> %vecinit.i, i16 %v1, i32 1
424 %vecinit2.i = insertelement <8 x i16> %vecinit1.i, i16 %v1, i32 2
425 %vecinit3.i = insertelement <8 x i16> %vecinit2.i, i16 %v1, i32 3
426 %vecinit4.i = insertelement <8 x i16> %vecinit3.i, i16 %v1, i32 4
427 %vecinit5.i = insertelement <8 x i16> %vecinit4.i, i16 %v1, i32 5
428 %vecinit6.i = insertelement <8 x i16> %vecinit5.i, i16 %v1, i32 6
429 %vecinit7.i = insertelement <8 x i16> %vecinit6.i, i16 %v1, i32 7
430 ret <8 x i16> %vecinit7.i
433 define <4 x i32> @test_vdupq_n_u32(i32 %v1) #0 {
434 ;CHECK: dup {{v[0-9]+}}.4s, {{w[0-9]+}}
435 %vecinit.i = insertelement <4 x i32> undef, i32 %v1, i32 0
436 %vecinit1.i = insertelement <4 x i32> %vecinit.i, i32 %v1, i32 1
437 %vecinit2.i = insertelement <4 x i32> %vecinit1.i, i32 %v1, i32 2
438 %vecinit3.i = insertelement <4 x i32> %vecinit2.i, i32 %v1, i32 3
439 ret <4 x i32> %vecinit3.i
442 define <2 x i64> @test_vdupq_n_u64(i64 %v1) #0 {
443 ;CHECK: dup {{v[0-9]+}}.2d, {{x[0-9]+}}
444 %vecinit.i = insertelement <2 x i64> undef, i64 %v1, i32 0
445 %vecinit1.i = insertelement <2 x i64> %vecinit.i, i64 %v1, i32 1
446 ret <2 x i64> %vecinit1.i
449 define <8 x i8> @test_vdup_lane_s8(<8 x i8> %v1) #0 {
450 ;CHECK: dup {{v[0-9]+}}.8b, {{v[0-9]+}}.b[5]
451 %shuffle = shufflevector <8 x i8> %v1, <8 x i8> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
452 ret <8 x i8> %shuffle
455 define <4 x i16> @test_vdup_lane_s16(<4 x i16> %v1) #0 {
456 ;CHECK: dup {{v[0-9]+}}.4h, {{v[0-9]+}}.h[2]
457 %shuffle = shufflevector <4 x i16> %v1, <4 x i16> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
458 ret <4 x i16> %shuffle
461 define <2 x i32> @test_vdup_lane_s32(<2 x i32> %v1) #0 {
462 ;CHECK: dup {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
463 %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <2 x i32> <i32 1, i32 1>
464 ret <2 x i32> %shuffle
467 define <16 x i8> @test_vdupq_lane_s8(<8 x i8> %v1) #0 {
468 ;CHECK: {{v[0-9]+}}.16b, {{v[0-9]+}}.b[5]
469 %shuffle = shufflevector <8 x i8> %v1, <8 x i8> undef, <16 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
470 ret <16 x i8> %shuffle
473 define <8 x i16> @test_vdupq_lane_s16(<4 x i16> %v1) #0 {
474 ;CHECK: {{v[0-9]+}}.8h, {{v[0-9]+}}.h[2]
475 %shuffle = shufflevector <4 x i16> %v1, <4 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
476 ret <8 x i16> %shuffle
479 define <4 x i32> @test_vdupq_lane_s32(<2 x i32> %v1) #0 {
480 ;CHECK: {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
481 %shuffle = shufflevector <2 x i32> %v1, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
482 ret <4 x i32> %shuffle
485 define <2 x i64> @test_vdupq_lane_s64(<1 x i64> %v1) #0 {
486 ;CHECK: {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
487 %shuffle = shufflevector <1 x i64> %v1, <1 x i64> undef, <2 x i32> zeroinitializer
488 ret <2 x i64> %shuffle
491 define <8 x i8> @test_vdup_laneq_s8(<16 x i8> %v1) #0 {
492 ;CHECK: dup {{v[0-9]+}}.8b, {{v[0-9]+}}.b[5]
493 %shuffle = shufflevector <16 x i8> %v1, <16 x i8> undef, <8 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
494 ret <8 x i8> %shuffle
497 define <4 x i16> @test_vdup_laneq_s16(<8 x i16> %v1) #0 {
498 ;CHECK: dup {{v[0-9]+}}.4h, {{v[0-9]+}}.h[2]
499 %shuffle = shufflevector <8 x i16> %v1, <8 x i16> undef, <4 x i32> <i32 2, i32 2, i32 2, i32 2>
500 ret <4 x i16> %shuffle
503 define <2 x i32> @test_vdup_laneq_s32(<4 x i32> %v1) #0 {
504 ;CHECK: dup {{v[0-9]+}}.2s, {{v[0-9]+}}.s[1]
505 %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <2 x i32> <i32 1, i32 1>
506 ret <2 x i32> %shuffle
509 define <16 x i8> @test_vdupq_laneq_s8(<16 x i8> %v1) #0 {
510 ;CHECK: dup {{v[0-9]+}}.16b, {{v[0-9]+}}.b[5]
511 %shuffle = shufflevector <16 x i8> %v1, <16 x i8> undef, <16 x i32> <i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5, i32 5>
512 ret <16 x i8> %shuffle
515 define <8 x i16> @test_vdupq_laneq_s16(<8 x i16> %v1) #0 {
516 ;CHECK: {{v[0-9]+}}.8h, {{v[0-9]+}}.h[2]
517 %shuffle = shufflevector <8 x i16> %v1, <8 x i16> undef, <8 x i32> <i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2>
518 ret <8 x i16> %shuffle
521 define <4 x i32> @test_vdupq_laneq_s32(<4 x i32> %v1) #0 {
522 ;CHECK: dup {{v[0-9]+}}.4s, {{v[0-9]+}}.s[1]
523 %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1>
524 ret <4 x i32> %shuffle
527 define <2 x i64> @test_vdupq_laneq_s64(<2 x i64> %v1) #0 {
528 ;CHECK: dup {{v[0-9]+}}.2d, {{v[0-9]+}}.d[0]
529 %shuffle = shufflevector <2 x i64> %v1, <2 x i64> undef, <2 x i32> zeroinitializer
530 ret <2 x i64> %shuffle
533 define i64 @test_bitcastv8i8toi64(<8 x i8> %in) {
534 ; CHECK-LABEL: test_bitcastv8i8toi64:
535 %res = bitcast <8 x i8> %in to i64
536 ; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
540 define i64 @test_bitcastv4i16toi64(<4 x i16> %in) {
541 ; CHECK-LABEL: test_bitcastv4i16toi64:
542 %res = bitcast <4 x i16> %in to i64
543 ; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
547 define i64 @test_bitcastv2i32toi64(<2 x i32> %in) {
548 ; CHECK-LABEL: test_bitcastv2i32toi64:
549 %res = bitcast <2 x i32> %in to i64
550 ; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
554 define i64 @test_bitcastv2f32toi64(<2 x float> %in) {
555 ; CHECK-LABEL: test_bitcastv2f32toi64:
556 %res = bitcast <2 x float> %in to i64
557 ; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
561 define i64 @test_bitcastv1i64toi64(<1 x i64> %in) {
562 ; CHECK-LABEL: test_bitcastv1i64toi64:
563 %res = bitcast <1 x i64> %in to i64
564 ; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
568 define i64 @test_bitcastv1f64toi64(<1 x double> %in) {
569 ; CHECK-LABEL: test_bitcastv1f64toi64:
570 %res = bitcast <1 x double> %in to i64
571 ; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
575 define <8 x i8> @test_bitcasti64tov8i8(i64 %in) {
576 ; CHECK-LABEL: test_bitcasti64tov8i8:
577 %res = bitcast i64 %in to <8 x i8>
578 ; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
582 define <4 x i16> @test_bitcasti64tov4i16(i64 %in) {
583 ; CHECK-LABEL: test_bitcasti64tov4i16:
584 %res = bitcast i64 %in to <4 x i16>
585 ; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
589 define <2 x i32> @test_bitcasti64tov2i32(i64 %in) {
590 ; CHECK-LABEL: test_bitcasti64tov2i32:
591 %res = bitcast i64 %in to <2 x i32>
592 ; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
596 define <2 x float> @test_bitcasti64tov2f32(i64 %in) {
597 ; CHECK-LABEL: test_bitcasti64tov2f32:
598 %res = bitcast i64 %in to <2 x float>
599 ; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
603 define <1 x i64> @test_bitcasti64tov1i64(i64 %in) {
604 ; CHECK-LABEL: test_bitcasti64tov1i64:
605 %res = bitcast i64 %in to <1 x i64>
606 ; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
610 define <1 x double> @test_bitcasti64tov1f64(i64 %in) {
611 ; CHECK-LABEL: test_bitcasti64tov1f64:
612 %res = bitcast i64 %in to <1 x double>
613 ; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
614 ret <1 x double> %res