1 ; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
3 define <8 x i8> @and8xi8(<8 x i8> %a, <8 x i8> %b) {
4 ;CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
5 %tmp1 = and <8 x i8> %a, %b;
9 define <16 x i8> @and16xi8(<16 x i8> %a, <16 x i8> %b) {
10 ;CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
11 %tmp1 = and <16 x i8> %a, %b;
16 define <8 x i8> @orr8xi8(<8 x i8> %a, <8 x i8> %b) {
17 ;CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
18 %tmp1 = or <8 x i8> %a, %b;
22 define <16 x i8> @orr16xi8(<16 x i8> %a, <16 x i8> %b) {
23 ;CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
24 %tmp1 = or <16 x i8> %a, %b;
29 define <8 x i8> @xor8xi8(<8 x i8> %a, <8 x i8> %b) {
30 ;CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
31 %tmp1 = xor <8 x i8> %a, %b;
35 define <16 x i8> @xor16xi8(<16 x i8> %a, <16 x i8> %b) {
36 ;CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
37 %tmp1 = xor <16 x i8> %a, %b;
41 define <8 x i8> @bsl8xi8_const(<8 x i8> %a, <8 x i8> %b) {
42 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
43 %tmp1 = and <8 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
44 %tmp2 = and <8 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0 >
45 %tmp3 = or <8 x i8> %tmp1, %tmp2
49 define <16 x i8> @bsl16xi8_const(<16 x i8> %a, <16 x i8> %b) {
50 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
51 %tmp1 = and <16 x i8> %a, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
52 %tmp2 = and <16 x i8> %b, < i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0 >
53 %tmp3 = or <16 x i8> %tmp1, %tmp2
57 define <8 x i8> @orn8xi8(<8 x i8> %a, <8 x i8> %b) {
58 ;CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
59 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
60 %tmp2 = or <8 x i8> %a, %tmp1
64 define <16 x i8> @orn16xi8(<16 x i8> %a, <16 x i8> %b) {
65 ;CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
66 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
67 %tmp2 = or <16 x i8> %a, %tmp1
71 define <8 x i8> @bic8xi8(<8 x i8> %a, <8 x i8> %b) {
72 ;CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
73 %tmp1 = xor <8 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
74 %tmp2 = and <8 x i8> %a, %tmp1
78 define <16 x i8> @bic16xi8(<16 x i8> %a, <16 x i8> %b) {
79 ;CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
80 %tmp1 = xor <16 x i8> %b, < i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1 >
81 %tmp2 = and <16 x i8> %a, %tmp1
85 define <2 x i32> @orrimm2s_lsl0(<2 x i32> %a) {
86 ;CHECK: orr {{v[0-9]+}}.2s, #0xff
87 %tmp1 = or <2 x i32> %a, < i32 255, i32 255>
91 define <2 x i32> @orrimm2s_lsl8(<2 x i32> %a) {
92 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #8
93 %tmp1 = or <2 x i32> %a, < i32 65280, i32 65280>
97 define <2 x i32> @orrimm2s_lsl16(<2 x i32> %a) {
98 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #16
99 %tmp1 = or <2 x i32> %a, < i32 16711680, i32 16711680>
103 define <2 x i32> @orrimm2s_lsl24(<2 x i32> %a) {
104 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #24
105 %tmp1 = or <2 x i32> %a, < i32 4278190080, i32 4278190080>
109 define <4 x i32> @orrimm4s_lsl0(<4 x i32> %a) {
110 ;CHECK: orr {{v[0-9]+}}.4s, #0xff
111 %tmp1 = or <4 x i32> %a, < i32 255, i32 255, i32 255, i32 255>
115 define <4 x i32> @orrimm4s_lsl8(<4 x i32> %a) {
116 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #8
117 %tmp1 = or <4 x i32> %a, < i32 65280, i32 65280, i32 65280, i32 65280>
121 define <4 x i32> @orrimm4s_lsl16(<4 x i32> %a) {
122 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #16
123 %tmp1 = or <4 x i32> %a, < i32 16711680, i32 16711680, i32 16711680, i32 16711680>
127 define <4 x i32> @orrimm4s_lsl24(<4 x i32> %a) {
128 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #24
129 %tmp1 = or <4 x i32> %a, < i32 4278190080, i32 4278190080, i32 4278190080, i32 4278190080>
133 define <4 x i16> @orrimm4h_lsl0(<4 x i16> %a) {
134 ;CHECK: orr {{v[0-9]+}}.4h, #0xff
135 %tmp1 = or <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255 >
139 define <4 x i16> @orrimm4h_lsl8(<4 x i16> %a) {
140 ;CHECK: orr {{v[0-9]+}}.4h, #0xff, lsl #8
141 %tmp1 = or <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
145 define <8 x i16> @orrimm8h_lsl0(<8 x i16> %a) {
146 ;CHECK: orr {{v[0-9]+}}.8h, #0xff
147 %tmp1 = or <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255 >
151 define <8 x i16> @orrimm8h_lsl8(<8 x i16> %a) {
152 ;CHECK: orr {{v[0-9]+}}.8h, #0xff, lsl #8
153 %tmp1 = or <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
157 define <2 x i32> @bicimm2s_lsl0(<2 x i32> %a) {
158 ;CHECK: bic {{v[0-9]+}}.2s, #0x10
159 %tmp1 = and <2 x i32> %a, < i32 4294967279, i32 4294967279 >
163 define <2 x i32> @bicimm2s_lsl8(<2 x i32> %a) {
164 ;CHECK: bic {{v[0-9]+}}.2s, #0x10, lsl #8
165 %tmp1 = and <2 x i32> %a, < i32 4294963199, i32 4294963199 >
169 define <2 x i32> @bicimm2s_lsl16(<2 x i32> %a) {
170 ;CHECK: bic {{v[0-9]+}}.2s, #0x10, lsl #16
171 %tmp1 = and <2 x i32> %a, < i32 4293918719, i32 4293918719 >
175 define <2 x i32> @bicimm2s_lsl124(<2 x i32> %a) {
176 ;CHECK: bic {{v[0-9]+}}.2s, #0x10, lsl #24
177 %tmp1 = and <2 x i32> %a, < i32 4026531839, i32 4026531839>
181 define <4 x i32> @bicimm4s_lsl0(<4 x i32> %a) {
182 ;CHECK: bic {{v[0-9]+}}.4s, #0x10
183 %tmp1 = and <4 x i32> %a, < i32 4294967279, i32 4294967279, i32 4294967279, i32 4294967279 >
187 define <4 x i32> @bicimm4s_lsl8(<4 x i32> %a) {
188 ;CHECK: bic {{v[0-9]+}}.4s, #0x10, lsl #8
189 %tmp1 = and <4 x i32> %a, < i32 4294963199, i32 4294963199, i32 4294963199, i32 4294963199 >
193 define <4 x i32> @bicimm4s_lsl16(<4 x i32> %a) {
194 ;CHECK: bic {{v[0-9]+}}.4s, #0x10, lsl #16
195 %tmp1 = and <4 x i32> %a, < i32 4293918719, i32 4293918719, i32 4293918719, i32 4293918719 >
199 define <4 x i32> @bicimm4s_lsl124(<4 x i32> %a) {
200 ;CHECK: bic {{v[0-9]+}}.4s, #0x10, lsl #24
201 %tmp1 = and <4 x i32> %a, < i32 4026531839, i32 4026531839, i32 4026531839, i32 4026531839>
205 define <4 x i16> @bicimm4h_lsl0_a(<4 x i16> %a) {
206 ;CHECK: bic {{v[0-9]+}}.4h, #0x10
207 %tmp1 = and <4 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >
211 define <4 x i16> @bicimm4h_lsl0_b(<4 x i16> %a) {
212 ;CHECK: bic {{v[0-9]+}}.4h, #0xff
213 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280 >
217 define <4 x i16> @bicimm4h_lsl8_a(<4 x i16> %a) {
218 ;CHECK: bic {{v[0-9]+}}.4h, #0x10, lsl #8
219 %tmp1 = and <4 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>
223 define <4 x i16> @bicimm4h_lsl8_b(<4 x i16> %a) {
224 ;CHECK: bic {{v[0-9]+}}.4h, #0xff, lsl #8
225 %tmp1 = and <4 x i16> %a, < i16 255, i16 255, i16 255, i16 255>
229 define <8 x i16> @bicimm8h_lsl0_a(<8 x i16> %a) {
230 ;CHECK: bic {{v[0-9]+}}.8h, #0x10
231 %tmp1 = and <8 x i16> %a, < i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279,
232 i16 4294967279, i16 4294967279, i16 4294967279, i16 4294967279 >
236 define <8 x i16> @bicimm8h_lsl0_b(<8 x i16> %a) {
237 ;CHECK: bic {{v[0-9]+}}.8h, #0xff
238 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280, i16 65280 >
242 define <8 x i16> @bicimm8h_lsl8_a(<8 x i16> %a) {
243 ;CHECK: bic {{v[0-9]+}}.8h, #0x10, lsl #8
244 %tmp1 = and <8 x i16> %a, < i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199,
245 i16 4294963199, i16 4294963199, i16 4294963199, i16 4294963199>
249 define <8 x i16> @bicimm8h_lsl8_b(<8 x i16> %a) {
250 ;CHECK: bic {{v[0-9]+}}.8h, #0xff, lsl #8
251 %tmp1 = and <8 x i16> %a, < i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
255 define <2 x i32> @and2xi32(<2 x i32> %a, <2 x i32> %b) {
256 ;CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
257 %tmp1 = and <2 x i32> %a, %b;
261 define <4 x i16> @and4xi16(<4 x i16> %a, <4 x i16> %b) {
262 ;CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
263 %tmp1 = and <4 x i16> %a, %b;
267 define <1 x i64> @and1xi64(<1 x i64> %a, <1 x i64> %b) {
268 ;CHECK: and {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
269 %tmp1 = and <1 x i64> %a, %b;
273 define <4 x i32> @and4xi32(<4 x i32> %a, <4 x i32> %b) {
274 ;CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
275 %tmp1 = and <4 x i32> %a, %b;
279 define <8 x i16> @and8xi16(<8 x i16> %a, <8 x i16> %b) {
280 ;CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
281 %tmp1 = and <8 x i16> %a, %b;
285 define <2 x i64> @and2xi64(<2 x i64> %a, <2 x i64> %b) {
286 ;CHECK: and {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
287 %tmp1 = and <2 x i64> %a, %b;
291 define <2 x i32> @orr2xi32(<2 x i32> %a, <2 x i32> %b) {
292 ;CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
293 %tmp1 = or <2 x i32> %a, %b;
297 define <4 x i16> @orr4xi16(<4 x i16> %a, <4 x i16> %b) {
298 ;CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
299 %tmp1 = or <4 x i16> %a, %b;
303 define <1 x i64> @orr1xi64(<1 x i64> %a, <1 x i64> %b) {
304 ;CHECK: orr {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
305 %tmp1 = or <1 x i64> %a, %b;
309 define <4 x i32> @orr4xi32(<4 x i32> %a, <4 x i32> %b) {
310 ;CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
311 %tmp1 = or <4 x i32> %a, %b;
315 define <8 x i16> @orr8xi16(<8 x i16> %a, <8 x i16> %b) {
316 ;CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
317 %tmp1 = or <8 x i16> %a, %b;
321 define <2 x i64> @orr2xi64(<2 x i64> %a, <2 x i64> %b) {
322 ;CHECK: orr {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
323 %tmp1 = or <2 x i64> %a, %b;
327 define <2 x i32> @eor2xi32(<2 x i32> %a, <2 x i32> %b) {
328 ;CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
329 %tmp1 = xor <2 x i32> %a, %b;
333 define <4 x i16> @eor4xi16(<4 x i16> %a, <4 x i16> %b) {
334 ;CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
335 %tmp1 = xor <4 x i16> %a, %b;
339 define <1 x i64> @eor1xi64(<1 x i64> %a, <1 x i64> %b) {
340 ;CHECK: eor {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
341 %tmp1 = xor <1 x i64> %a, %b;
345 define <4 x i32> @eor4xi32(<4 x i32> %a, <4 x i32> %b) {
346 ;CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
347 %tmp1 = xor <4 x i32> %a, %b;
351 define <8 x i16> @eor8xi16(<8 x i16> %a, <8 x i16> %b) {
352 ;CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
353 %tmp1 = xor <8 x i16> %a, %b;
357 define <2 x i64> @eor2xi64(<2 x i64> %a, <2 x i64> %b) {
358 ;CHECK: eor {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
359 %tmp1 = xor <2 x i64> %a, %b;
364 define <2 x i32> @bic2xi32(<2 x i32> %a, <2 x i32> %b) {
365 ;CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
366 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
367 %tmp2 = and <2 x i32> %a, %tmp1
371 define <4 x i16> @bic4xi16(<4 x i16> %a, <4 x i16> %b) {
372 ;CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
373 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
374 %tmp2 = and <4 x i16> %a, %tmp1
378 define <1 x i64> @bic1xi64(<1 x i64> %a, <1 x i64> %b) {
379 ;CHECK: bic {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
380 %tmp1 = xor <1 x i64> %b, < i64 -1>
381 %tmp2 = and <1 x i64> %a, %tmp1
385 define <4 x i32> @bic4xi32(<4 x i32> %a, <4 x i32> %b) {
386 ;CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
387 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
388 %tmp2 = and <4 x i32> %a, %tmp1
392 define <8 x i16> @bic8xi16(<8 x i16> %a, <8 x i16> %b) {
393 ;CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
394 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
395 %tmp2 = and <8 x i16> %a, %tmp1
399 define <2 x i64> @bic2xi64(<2 x i64> %a, <2 x i64> %b) {
400 ;CHECK: bic {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
401 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
402 %tmp2 = and <2 x i64> %a, %tmp1
406 define <2 x i32> @orn2xi32(<2 x i32> %a, <2 x i32> %b) {
407 ;CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
408 %tmp1 = xor <2 x i32> %b, < i32 -1, i32 -1 >
409 %tmp2 = or <2 x i32> %a, %tmp1
413 define <4 x i16> @orn4xi16(<4 x i16> %a, <4 x i16> %b) {
414 ;CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
415 %tmp1 = xor <4 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1 >
416 %tmp2 = or <4 x i16> %a, %tmp1
420 define <1 x i64> @orn1xi64(<1 x i64> %a, <1 x i64> %b) {
421 ;CHECK: orn {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
422 %tmp1 = xor <1 x i64> %b, < i64 -1>
423 %tmp2 = or <1 x i64> %a, %tmp1
427 define <4 x i32> @orn4xi32(<4 x i32> %a, <4 x i32> %b) {
428 ;CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
429 %tmp1 = xor <4 x i32> %b, < i32 -1, i32 -1, i32 -1, i32 -1>
430 %tmp2 = or <4 x i32> %a, %tmp1
434 define <8 x i16> @orn8xi16(<8 x i16> %a, <8 x i16> %b) {
435 ;CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
436 %tmp1 = xor <8 x i16> %b, < i16 -1, i16 -1, i16 -1, i16-1, i16 -1, i16 -1, i16 -1, i16 -1 >
437 %tmp2 = or <8 x i16> %a, %tmp1
441 define <2 x i64> @orn2xi64(<2 x i64> %a, <2 x i64> %b) {
442 ;CHECK: orn {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
443 %tmp1 = xor <2 x i64> %b, < i64 -1, i64 -1>
444 %tmp2 = or <2 x i64> %a, %tmp1
447 define <2 x i32> @bsl2xi32_const(<2 x i32> %a, <2 x i32> %b) {
448 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
449 %tmp1 = and <2 x i32> %a, < i32 -1, i32 -1 >
450 %tmp2 = and <2 x i32> %b, < i32 0, i32 0 >
451 %tmp3 = or <2 x i32> %tmp1, %tmp2
456 define <4 x i16> @bsl4xi16_const(<4 x i16> %a, <4 x i16> %b) {
457 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
458 %tmp1 = and <4 x i16> %a, < i16 -1, i16 -1, i16 -1,i16 -1 >
459 %tmp2 = and <4 x i16> %b, < i16 0, i16 0,i16 0, i16 0 >
460 %tmp3 = or <4 x i16> %tmp1, %tmp2
464 define <1 x i64> @bsl1xi64_const(<1 x i64> %a, <1 x i64> %b) {
465 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
466 %tmp1 = and <1 x i64> %a, < i64 -1 >
467 %tmp2 = and <1 x i64> %b, < i64 0 >
468 %tmp3 = or <1 x i64> %tmp1, %tmp2
472 define <4 x i32> @bsl4xi32_const(<4 x i32> %a, <4 x i32> %b) {
473 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
474 %tmp1 = and <4 x i32> %a, < i32 -1, i32 -1, i32 -1, i32 -1 >
475 %tmp2 = and <4 x i32> %b, < i32 0, i32 0, i32 0, i32 0 >
476 %tmp3 = or <4 x i32> %tmp1, %tmp2
480 define <8 x i16> @bsl8xi16_const(<8 x i16> %a, <8 x i16> %b) {
481 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
482 %tmp1 = and <8 x i16> %a, < i16 -1, i16 -1, i16 -1,i16 -1, i16 -1, i16 -1, i16 -1,i16 -1 >
483 %tmp2 = and <8 x i16> %b, < i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0 >
484 %tmp3 = or <8 x i16> %tmp1, %tmp2
488 define <2 x i64> @bsl2xi64_const(<2 x i64> %a, <2 x i64> %b) {
489 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
490 %tmp1 = and <2 x i64> %a, < i64 -1, i64 -1 >
491 %tmp2 = and <2 x i64> %b, < i64 0, i64 0 >
492 %tmp3 = or <2 x i64> %tmp1, %tmp2
497 define <8 x i8> @bsl8xi8(<8 x i8> %v1, <8 x i8> %v2, <8 x i8> %v3) {
498 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
499 %1 = and <8 x i8> %v1, %v2
500 %2 = xor <8 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
501 %3 = and <8 x i8> %2, %v3
502 %4 = or <8 x i8> %1, %3
506 define <4 x i16> @bsl4xi16(<4 x i16> %v1, <4 x i16> %v2, <4 x i16> %v3) {
507 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
508 %1 = and <4 x i16> %v1, %v2
509 %2 = xor <4 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1>
510 %3 = and <4 x i16> %2, %v3
511 %4 = or <4 x i16> %1, %3
515 define <2 x i32> @bsl2xi32(<2 x i32> %v1, <2 x i32> %v2, <2 x i32> %v3) {
516 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
517 %1 = and <2 x i32> %v1, %v2
518 %2 = xor <2 x i32> %v1, <i32 -1, i32 -1>
519 %3 = and <2 x i32> %2, %v3
520 %4 = or <2 x i32> %1, %3
524 define <1 x i64> @bsl1xi64(<1 x i64> %v1, <1 x i64> %v2, <1 x i64> %v3) {
525 ;CHECK: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
526 %1 = and <1 x i64> %v1, %v2
527 %2 = xor <1 x i64> %v1, <i64 -1>
528 %3 = and <1 x i64> %2, %v3
529 %4 = or <1 x i64> %1, %3
533 define <16 x i8> @bsl16xi8(<16 x i8> %v1, <16 x i8> %v2, <16 x i8> %v3) {
534 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
535 %1 = and <16 x i8> %v1, %v2
536 %2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
537 %3 = and <16 x i8> %2, %v3
538 %4 = or <16 x i8> %1, %3
542 define <8 x i16> @bsl8xi16(<8 x i16> %v1, <8 x i16> %v2, <8 x i16> %v3) {
543 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
544 %1 = and <8 x i16> %v1, %v2
545 %2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
546 %3 = and <8 x i16> %2, %v3
547 %4 = or <8 x i16> %1, %3
551 define <4 x i32> @bsl4xi32(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3) {
552 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
553 %1 = and <4 x i32> %v1, %v2
554 %2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
555 %3 = and <4 x i32> %2, %v3
556 %4 = or <4 x i32> %1, %3
560 define <8 x i8> @vselect_v8i8(<8 x i8> %a) {
561 ;CHECK: movi {{d[0-9]+}}, #0xffff
562 ;CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
563 %b = select <8 x i1> <i1 true, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false, i1 false>, <8 x i8> %a, <8 x i8> <i8 undef, i8 undef, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>
567 define <4 x i16> @vselect_v4i16(<4 x i16> %a) {
568 ;CHECK: movi {{d[0-9]+}}, #0xffff
569 ;CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
570 %b = select <4 x i1> <i1 true, i1 false, i1 false, i1 false>, <4 x i16> %a, <4 x i16> <i16 undef, i16 0, i16 0, i16 0>
574 define <8 x i8> @vselect_cmp_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
575 ;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
576 ;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
577 ;CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
578 %cmp = icmp ne <8 x i8> %a, %b
579 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
583 define <8 x i8> @vselect_cmp_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
584 ;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
585 ;CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
586 %cmp = icmp eq <8 x i8> %a, %b
587 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
591 define <8 x i8> @vselect_cmpz_ne(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
592 ;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
593 ;CHECK-NEXT: not {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
594 ;CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
595 %cmp = icmp ne <8 x i8> %a, zeroinitializer
596 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
600 define <8 x i8> @vselect_cmpz_eq(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
601 ;CHECK: cmeq {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, #0
602 ;CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
603 %cmp = icmp eq <8 x i8> %a, zeroinitializer
604 %d = select <8 x i1> %cmp, <8 x i8> %b, <8 x i8> %c
608 define <8 x i8> @vselect_tst(<8 x i8> %a, <8 x i8> %b, <8 x i8> %c) {
609 ;CHECK: cmtst {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
610 ;CHECK-NEXT: bsl {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b
611 %tmp3 = and <8 x i8> %a, %b
612 %tmp4 = icmp ne <8 x i8> %tmp3, zeroinitializer
613 %d = select <8 x i1> %tmp4, <8 x i8> %b, <8 x i8> %c
617 define <2 x i64> @bsl2xi64(<2 x i64> %v1, <2 x i64> %v2, <2 x i64> %v3) {
618 ;CHECK: bsl {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
619 %1 = and <2 x i64> %v1, %v2
620 %2 = xor <2 x i64> %v1, <i64 -1, i64 -1>
621 %3 = and <2 x i64> %2, %v3
622 %4 = or <2 x i64> %1, %3
626 define <8 x i8> @orrimm8b_as_orrimm4h_lsl0(<8 x i8> %a) {
627 ;CHECK: orr {{v[0-9]+}}.4h, #0xff
628 %val = or <8 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
632 define <8 x i8> @orrimm8b_as_orimm4h_lsl8(<8 x i8> %a) {
633 ;CHECK: orr {{v[0-9]+}}.4h, #0xff, lsl #8
634 %val = or <8 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
638 define <16 x i8> @orimm16b_as_orrimm8h_lsl0(<16 x i8> %a) {
639 ;CHECK: orr {{v[0-9]+}}.8h, #0xff
640 %val = or <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
644 define <16 x i8> @orimm16b_as_orrimm8h_lsl8(<16 x i8> %a) {
645 ;CHECK: orr {{v[0-9]+}}.8h, #0xff, lsl #8
646 %val = or <16 x i8> %a, <i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
650 define <8 x i8> @and8imm2s_lsl0(<8 x i8> %a) {
651 ;CHECK: bic {{v[0-9]+}}.2s, #0xff
652 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
656 define <8 x i8> @and8imm2s_lsl8(<8 x i8> %a) {
657 ;CHECK: bic {{v[0-9]+}}.2s, #0xff, lsl #8
658 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
662 define <8 x i8> @and8imm2s_lsl16(<8 x i8> %a) {
663 ;CHECK: bic {{v[0-9]+}}.2s, #0xff, lsl #16
664 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
668 define <8 x i8> @and8imm2s_lsl24(<8 x i8> %a) {
669 ;CHECK: bic {{v[0-9]+}}.2s, #0xfe, lsl #24
670 %tmp1 = and <8 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
674 define <4 x i16> @and16imm2s_lsl0(<4 x i16> %a) {
675 ;CHECK: bic {{v[0-9]+}}.2s, #0xff
676 %tmp1 = and <4 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535>
680 define <4 x i16> @and16imm2s_lsl8(<4 x i16> %a) {
681 ;CHECK: bic {{v[0-9]+}}.2s, #0xff, lsl #8
682 %tmp1 = and <4 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535>
686 define <4 x i16> @and16imm2s_lsl16(<4 x i16> %a) {
687 ;CHECK: bic {{v[0-9]+}}.2s, #0xff, lsl #16
688 %tmp1 = and <4 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280>
692 define <4 x i16> @and16imm2s_lsl24(<4 x i16> %a) {
693 ;CHECK: bic {{v[0-9]+}}.2s, #0xfe, lsl #24
694 %tmp1 = and <4 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511>
699 define <1 x i64> @and64imm2s_lsl0(<1 x i64> %a) {
700 ;CHECK: bic {{v[0-9]+}}.2s, #0xff
701 %tmp1 = and <1 x i64> %a, < i64 -1095216660736>
705 define <1 x i64> @and64imm2s_lsl8(<1 x i64> %a) {
706 ;CHECK: bic {{v[0-9]+}}.2s, #0xff, lsl #8
707 %tmp1 = and <1 x i64> %a, < i64 -280375465148161>
711 define <1 x i64> @and64imm2s_lsl16(<1 x i64> %a) {
712 ;CHECK: bic {{v[0-9]+}}.2s, #0xff, lsl #16
713 %tmp1 = and <1 x i64> %a, < i64 -71776119077928961>
717 define <1 x i64> @and64imm2s_lsl24(<1 x i64> %a) {
718 ;CHECK: bic {{v[0-9]+}}.2s, #0xfe, lsl #24
719 %tmp1 = and <1 x i64> %a, < i64 144115183814443007>
723 define <16 x i8> @and8imm4s_lsl0(<16 x i8> %a) {
724 ;CHECK: bic {{v[0-9]+}}.4s, #0xff
725 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255>
729 define <16 x i8> @and8imm4s_lsl8(<16 x i8> %a) {
730 ;CHECK: bic {{v[0-9]+}}.4s, #0xff, lsl #8
731 %tmp1 = and <16 x i8> %a, < i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255>
735 define <16 x i8> @and8imm4s_lsl16(<16 x i8> %a) {
736 ;CHECK: bic {{v[0-9]+}}.4s, #0xff, lsl #16
737 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255, i8 255, i8 255, i8 0, i8 255>
741 define <16 x i8> @and8imm4s_lsl24(<16 x i8> %a) {
742 ;CHECK: bic {{v[0-9]+}}.4s, #0xfe, lsl #24
743 %tmp1 = and <16 x i8> %a, < i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1, i8 255, i8 255, i8 255, i8 1>
747 define <8 x i16> @and16imm4s_lsl0(<8 x i16> %a) {
748 ;CHECK: bic {{v[0-9]+}}.4s, #0xff
749 %tmp1 = and <8 x i16> %a, < i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535>
753 define <8 x i16> @and16imm4s_lsl8(<8 x i16> %a) {
754 ;CHECK: bic {{v[0-9]+}}.4s, #0xff, lsl #8
755 %tmp1 = and <8 x i16> %a, < i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535, i16 255, i16 65535>
759 define <8 x i16> @and16imm4s_lsl16(<8 x i16> %a) {
760 ;CHECK: bic {{v[0-9]+}}.4s, #0xff, lsl #16
761 %tmp1 = and <8 x i16> %a, < i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280, i16 65535, i16 65280>
765 define <8 x i16> @and16imm4s_lsl24(<8 x i16> %a) {
766 ;CHECK: bic {{v[0-9]+}}.4s, #0xfe, lsl #24
767 %tmp1 = and <8 x i16> %a, < i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511, i16 65535, i16 511>
771 define <2 x i64> @and64imm4s_lsl0(<2 x i64> %a) {
772 ;CHECK: bic {{v[0-9]+}}.4s, #0xff
773 %tmp1 = and <2 x i64> %a, < i64 -1095216660736, i64 -1095216660736>
777 define <2 x i64> @and64imm4s_lsl8(<2 x i64> %a) {
778 ;CHECK: bic {{v[0-9]+}}.4s, #0xff, lsl #8
779 %tmp1 = and <2 x i64> %a, < i64 -280375465148161, i64 -280375465148161>
783 define <2 x i64> @and64imm4s_lsl16(<2 x i64> %a) {
784 ;CHECK: bic {{v[0-9]+}}.4s, #0xff, lsl #16
785 %tmp1 = and <2 x i64> %a, < i64 -71776119077928961, i64 -71776119077928961>
789 define <2 x i64> @and64imm4s_lsl24(<2 x i64> %a) {
790 ;CHECK: bic {{v[0-9]+}}.4s, #0xfe, lsl #24
791 %tmp1 = and <2 x i64> %a, < i64 144115183814443007, i64 144115183814443007>
795 define <8 x i8> @and8imm4h_lsl0(<8 x i8> %a) {
796 ;CHECK: bic {{v[0-9]+}}.4h, #0xff
797 %tmp1 = and <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
801 define <8 x i8> @and8imm4h_lsl8(<8 x i8> %a) {
802 ;CHECK: bic {{v[0-9]+}}.4h, #0xff, lsl #8
803 %tmp1 = and <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
807 define <2 x i32> @and16imm4h_lsl0(<2 x i32> %a) {
808 ;CHECK: bic {{v[0-9]+}}.4h, #0xff
809 %tmp1 = and <2 x i32> %a, < i32 4278255360, i32 4278255360>
813 define <2 x i32> @and16imm4h_lsl8(<2 x i32> %a) {
814 ;CHECK: bic {{v[0-9]+}}.4h, #0xff, lsl #8
815 %tmp1 = and <2 x i32> %a, < i32 16711935, i32 16711935>
819 define <1 x i64> @and64imm4h_lsl0(<1 x i64> %a) {
820 ;CHECK: bic {{v[0-9]+}}.4h, #0xff
821 %tmp1 = and <1 x i64> %a, < i64 -71777214294589696>
825 define <1 x i64> @and64imm4h_lsl8(<1 x i64> %a) {
826 ;CHECK: bic {{v[0-9]+}}.4h, #0xff, lsl #8
827 %tmp1 = and <1 x i64> %a, < i64 71777214294589695>
831 define <16 x i8> @and8imm8h_lsl0(<16 x i8> %a) {
832 ;CHECK: bic {{v[0-9]+}}.8h, #0xff
833 %tmp1 = and <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255 >
837 define <16 x i8> @and8imm8h_lsl8(<16 x i8> %a) {
838 ;CHECK: bic {{v[0-9]+}}.8h, #0xff, lsl #8
839 %tmp1 = and <16 x i8> %a, <i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0 >
843 define <4 x i32> @and16imm8h_lsl0(<4 x i32> %a) {
844 ;CHECK: bic {{v[0-9]+}}.8h, #0xff
845 %tmp1 = and <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
849 define <4 x i32> @and16imm8h_lsl8(<4 x i32> %a) {
850 ;CHECK: bic {{v[0-9]+}}.8h, #0xff, lsl #8
851 %tmp1 = and <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
855 define <2 x i64> @and64imm8h_lsl0(<2 x i64> %a) {
856 ;CHECK: bic {{v[0-9]+}}.8h, #0xff
857 %tmp1 = and <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>
861 define <2 x i64> @and64imm8h_lsl8(<2 x i64> %a) {
862 ;CHECK: bic {{v[0-9]+}}.8h, #0xff, lsl #8
863 %tmp1 = and <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
867 define <8 x i8> @orr8imm2s_lsl0(<8 x i8> %a) {
868 ;CHECK: orr {{v[0-9]+}}.2s, #0xff
869 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
873 define <8 x i8> @orr8imm2s_lsl8(<8 x i8> %a) {
874 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #8
875 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
879 define <8 x i8> @orr8imm2s_lsl16(<8 x i8> %a) {
880 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #16
881 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
885 define <8 x i8> @orr8imm2s_lsl24(<8 x i8> %a) {
886 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #24
887 %tmp1 = or <8 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
891 define <4 x i16> @orr16imm2s_lsl0(<4 x i16> %a) {
892 ;CHECK: orr {{v[0-9]+}}.2s, #0xff
893 %tmp1 = or <4 x i16> %a, < i16 255, i16 0, i16 255, i16 0>
897 define <4 x i16> @orr16imm2s_lsl8(<4 x i16> %a) {
898 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #8
899 %tmp1 = or <4 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0>
903 define <4 x i16> @orr16imm2s_lsl16(<4 x i16> %a) {
904 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #16
905 %tmp1 = or <4 x i16> %a, < i16 0, i16 255, i16 0, i16 255>
909 define <4 x i16> @orr16imm2s_lsl24(<4 x i16> %a) {
910 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #24
911 %tmp1 = or <4 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280>
915 define <1 x i64> @orr64imm2s_lsl0(<1 x i64> %a) {
916 ;CHECK: orr {{v[0-9]+}}.2s, #0xff
917 %tmp1 = or <1 x i64> %a, < i64 1095216660735>
921 define <1 x i64> @orr64imm2s_lsl8(<1 x i64> %a) {
922 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #8
923 %tmp1 = or <1 x i64> %a, < i64 280375465148160>
927 define <1 x i64> @orr64imm2s_lsl16(<1 x i64> %a) {
928 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #16
929 %tmp1 = or <1 x i64> %a, < i64 71776119077928960>
933 define <1 x i64> @orr64imm2s_lsl24(<1 x i64> %a) {
934 ;CHECK: orr {{v[0-9]+}}.2s, #0xff, lsl #24
935 %tmp1 = or <1 x i64> %a, < i64 -72057589759737856>
939 define <16 x i8> @orr8imm4s_lsl0(<16 x i8> %a) {
940 ;CHECK: orr {{v[0-9]+}}.4s, #0xff
941 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0>
945 define <16 x i8> @orr8imm4s_lsl8(<16 x i8> %a) {
946 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #8
947 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0>
951 define <16 x i8> @orr8imm4s_lsl16(<16 x i8> %a) {
952 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #16
953 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0>
957 define <16 x i8> @orr8imm4s_lsl24(<16 x i8> %a) {
958 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #24
959 %tmp1 = or <16 x i8> %a, < i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255, i8 0, i8 0, i8 0, i8 255>
963 define <8 x i16> @orr16imm4s_lsl0(<8 x i16> %a) {
964 ;CHECK: orr {{v[0-9]+}}.4s, #0xff
965 %tmp1 = or <8 x i16> %a, < i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0>
969 define <8 x i16> @orr16imm4s_lsl8(<8 x i16> %a) {
970 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #8
971 %tmp1 = or <8 x i16> %a, < i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0>
975 define <8 x i16> @orr16imm4s_lsl16(<8 x i16> %a) {
976 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #16
977 %tmp1 = or <8 x i16> %a, < i16 0, i16 255, i16 0, i16 255, i16 0, i16 255, i16 0, i16 255>
981 define <8 x i16> @orr16imm4s_lsl24(<8 x i16> %a) {
982 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #24
983 %tmp1 = or <8 x i16> %a, < i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280, i16 0, i16 65280>
987 define <2 x i64> @orr64imm4s_lsl0(<2 x i64> %a) {
988 ;CHECK: orr {{v[0-9]+}}.4s, #0xff
989 %tmp1 = or <2 x i64> %a, < i64 1095216660735, i64 1095216660735>
993 define <2 x i64> @orr64imm4s_lsl8(<2 x i64> %a) {
994 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #8
995 %tmp1 = or <2 x i64> %a, < i64 280375465148160, i64 280375465148160>
999 define <2 x i64> @orr64imm4s_lsl16(<2 x i64> %a) {
1000 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #16
1001 %tmp1 = or <2 x i64> %a, < i64 71776119077928960, i64 71776119077928960>
1005 define <2 x i64> @orr64imm4s_lsl24(<2 x i64> %a) {
1006 ;CHECK: orr {{v[0-9]+}}.4s, #0xff, lsl #24
1007 %tmp1 = or <2 x i64> %a, < i64 -72057589759737856, i64 -72057589759737856>
1011 define <8 x i8> @orr8imm4h_lsl0(<8 x i8> %a) {
1012 ;CHECK: orr {{v[0-9]+}}.4h, #0xff
1013 %tmp1 = or <8 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
1017 define <8 x i8> @orr8imm4h_lsl8(<8 x i8> %a) {
1018 ;CHECK: orr {{v[0-9]+}}.4h, #0xff, lsl #8
1019 %tmp1 = or <8 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
1023 define <2 x i32> @orr16imm4h_lsl0(<2 x i32> %a) {
1024 ;CHECK: orr {{v[0-9]+}}.4h, #0xff
1025 %tmp1 = or <2 x i32> %a, < i32 16711935, i32 16711935>
1029 define <2 x i32> @orr16imm4h_lsl8(<2 x i32> %a) {
1030 ;CHECK: orr {{v[0-9]+}}.4h, #0xff, lsl #8
1031 %tmp1 = or <2 x i32> %a, < i32 4278255360, i32 4278255360>
1035 define <1 x i64> @orr64imm4h_lsl0(<1 x i64> %a) {
1036 ;CHECK: orr {{v[0-9]+}}.4h, #0xff
1037 %tmp1 = or <1 x i64> %a, < i64 71777214294589695>
1041 define <1 x i64> @orr64imm4h_lsl8(<1 x i64> %a) {
1042 ;CHECK: orr {{v[0-9]+}}.4h, #0xff, lsl #8
1043 %tmp1 = or <1 x i64> %a, < i64 -71777214294589696>
1047 define <16 x i8> @orr8imm8h_lsl0(<16 x i8> %a) {
1048 ;CHECK: orr {{v[0-9]+}}.8h, #0xff
1049 %tmp1 = or <16 x i8> %a, < i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0>
1053 define <16 x i8> @orr8imm8h_lsl8(<16 x i8> %a) {
1054 ;CHECK: orr {{v[0-9]+}}.8h, #0xff, lsl #8
1055 %tmp1 = or <16 x i8> %a, < i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255, i8 0, i8 255>
1059 define <4 x i32> @orr16imm8h_lsl0(<4 x i32> %a) {
1060 ;CHECK: orr {{v[0-9]+}}.8h, #0xff
1061 %tmp1 = or <4 x i32> %a, < i32 16711935, i32 16711935, i32 16711935, i32 16711935>
1065 define <4 x i32> @orr16imm8h_lsl8(<4 x i32> %a) {
1066 ;CHECK: orr {{v[0-9]+}}.8h, #0xff, lsl #8
1067 %tmp1 = or <4 x i32> %a, < i32 4278255360, i32 4278255360, i32 4278255360, i32 4278255360>
1071 define <2 x i64> @orr64imm8h_lsl0(<2 x i64> %a) {
1072 ;CHECK: orr {{v[0-9]+}}.8h, #0xff
1073 %tmp1 = or <2 x i64> %a, < i64 71777214294589695, i64 71777214294589695>
1077 define <2 x i64> @orr64imm8h_lsl8(<2 x i64> %a) {
1078 ;CHECK: orr {{v[0-9]+}}.8h, #0xff, lsl #8
1079 %tmp1 = or <2 x i64> %a, < i64 -71777214294589696, i64 -71777214294589696>