test/CodeGen/AArch64/literal_pools_int.ll

   1 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
   2 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -code-model=large | FileCheck --check-prefix=CHECK-LARGE %s
   3 ; arm64 does not use literal pools for integers so there is nothing to check.
   4
   5 @var32 = global i32 0
   6 @var64 = global i64 0
   7
   8 define void @foo() {
   9 ; CHECK-LABEL: foo:
  10     %val32 = load i32* @var32
  11     %val64 = load i64* @var64
  12
  13     %val32_lit32 = and i32 %val32, 123456785
  14     store volatile i32 %val32_lit32, i32* @var32
  15 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]]
  16 ; CHECK: ldr {{w[0-9]+}}, [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
  17
  18 ; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI0_[0-9]+]]
  19 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
  20 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]]
  21 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]]
  22 ; CHECK-LARGE: ldr {{w[0-9]+}}, [x[[LITADDR]]]
  23
  24     %val64_lit32 = and i64 %val64, 305402420
  25     store volatile i64 %val64_lit32, i64* @var64
  26 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]]
  27 ; CHECK: ldr {{w[0-9]+}}, [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
  28
  29 ; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI0_[0-9]+]]
  30 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
  31 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]]
  32 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]]
  33 ; CHECK-LARGE: ldr {{w[0-9]+}}, [x[[LITADDR]]]
  34
  35     %val64_lit32signed = and i64 %val64, -12345678
  36     store volatile i64 %val64_lit32signed, i64* @var64
  37 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]]
  38 ; CHECK: ldrsw {{x[0-9]+}}, [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
  39
  40 ; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI0_[0-9]+]]
  41 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
  42 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]]
  43 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]]
  44 ; CHECK-LARGE: ldrsw {{x[0-9]+}}, [x[[LITADDR]]]
  45
  46     %val64_lit64 = and i64 %val64, 1234567898765432
  47     store volatile i64 %val64_lit64, i64* @var64
  48 ; CHECK: adrp x[[LITBASE:[0-9]+]], [[CURLIT:.LCPI0_[0-9]+]]
  49 ; CHECK: ldr {{x[0-9]+}}, [x[[LITBASE]], {{#?}}:lo12:[[CURLIT]]]
  50
  51 ; CHECK-LARGE: movz x[[LITADDR:[0-9]+]], #:abs_g3:[[CURLIT:.LCPI0_[0-9]+]]
  52 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g2_nc:[[CURLIT]]
  53 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g1_nc:[[CURLIT]]
  54 ; CHECK-LARGE: movk x[[LITADDR]], #:abs_g0_nc:[[CURLIT]]
  55 ; CHECK-LARGE: ldr {{x[0-9]+}}, [x[[LITADDR]]]
  56
  57     ret void
  58 }