1 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
2 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu -mattr=-fp-armv8 | FileCheck --check-prefix=CHECK-NOFP %s
3 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-linux-gnu | FileCheck %s
5 @var_8bit = global i8 0
6 @var_16bit = global i16 0
7 @var_32bit = global i32 0
8 @var_64bit = global i64 0
10 @var_float = global float 0.0
11 @var_double = global double 0.0
13 @varptr = global i8* null
15 define void @ldst_8bit() {
16 ; CHECK-LABEL: ldst_8bit:
18 ; No architectural support for loads to 16-bit or 8-bit since we
19 ; promote i8 during lowering.
20 %addr_8bit = load i8** @varptr
22 ; match a sign-extending load 8-bit -> 32-bit
23 %addr_sext32 = getelementptr i8* %addr_8bit, i64 -256
24 %val8_sext32 = load volatile i8* %addr_sext32
25 %val32_signed = sext i8 %val8_sext32 to i32
26 store volatile i32 %val32_signed, i32* @var_32bit
27 ; CHECK: ldursb {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
29 ; match a zero-extending load volatile 8-bit -> 32-bit
30 %addr_zext32 = getelementptr i8* %addr_8bit, i64 -12
31 %val8_zext32 = load volatile i8* %addr_zext32
32 %val32_unsigned = zext i8 %val8_zext32 to i32
33 store volatile i32 %val32_unsigned, i32* @var_32bit
34 ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-12]
36 ; match an any-extending load volatile 8-bit -> 32-bit
37 %addr_anyext = getelementptr i8* %addr_8bit, i64 -1
38 %val8_anyext = load volatile i8* %addr_anyext
39 %newval8 = add i8 %val8_anyext, 1
40 store volatile i8 %newval8, i8* @var_8bit
41 ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-1]
43 ; match a sign-extending load volatile 8-bit -> 64-bit
44 %addr_sext64 = getelementptr i8* %addr_8bit, i64 -5
45 %val8_sext64 = load volatile i8* %addr_sext64
46 %val64_signed = sext i8 %val8_sext64 to i64
47 store volatile i64 %val64_signed, i64* @var_64bit
48 ; CHECK: ldursb {{x[0-9]+}}, [{{x[0-9]+}}, #-5]
50 ; match a zero-extending load volatile 8-bit -> 64-bit.
51 ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits
52 ; of x0 so it's identical to load volatileing to 32-bits.
53 %addr_zext64 = getelementptr i8* %addr_8bit, i64 -9
54 %val8_zext64 = load volatile i8* %addr_zext64
55 %val64_unsigned = zext i8 %val8_zext64 to i64
56 store volatile i64 %val64_unsigned, i64* @var_64bit
57 ; CHECK: ldurb {{w[0-9]+}}, [{{x[0-9]+}}, #-9]
59 ; truncating store volatile 32-bits to 8-bits
60 %addr_trunc32 = getelementptr i8* %addr_8bit, i64 -256
61 %val32 = load volatile i32* @var_32bit
62 %val8_trunc32 = trunc i32 %val32 to i8
63 store volatile i8 %val8_trunc32, i8* %addr_trunc32
64 ; CHECK: sturb {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
66 ; truncating store volatile 64-bits to 8-bits
67 %addr_trunc64 = getelementptr i8* %addr_8bit, i64 -1
68 %val64 = load volatile i64* @var_64bit
69 %val8_trunc64 = trunc i64 %val64 to i8
70 store volatile i8 %val8_trunc64, i8* %addr_trunc64
71 ; CHECK: sturb {{w[0-9]+}}, [{{x[0-9]+}}, #-1]
76 define void @ldst_16bit() {
77 ; CHECK-LABEL: ldst_16bit:
79 ; No architectural support for loads to 16-bit or 16-bit since we
80 ; promote i16 during lowering.
81 %addr_8bit = load i8** @varptr
83 ; match a sign-extending load 16-bit -> 32-bit
84 %addr8_sext32 = getelementptr i8* %addr_8bit, i64 -256
85 %addr_sext32 = bitcast i8* %addr8_sext32 to i16*
86 %val16_sext32 = load volatile i16* %addr_sext32
87 %val32_signed = sext i16 %val16_sext32 to i32
88 store volatile i32 %val32_signed, i32* @var_32bit
89 ; CHECK: ldursh {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
91 ; match a zero-extending load volatile 16-bit -> 32-bit. With offset that would be unaligned.
92 %addr8_zext32 = getelementptr i8* %addr_8bit, i64 15
93 %addr_zext32 = bitcast i8* %addr8_zext32 to i16*
94 %val16_zext32 = load volatile i16* %addr_zext32
95 %val32_unsigned = zext i16 %val16_zext32 to i32
96 store volatile i32 %val32_unsigned, i32* @var_32bit
97 ; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #15]
99 ; match an any-extending load volatile 16-bit -> 32-bit
100 %addr8_anyext = getelementptr i8* %addr_8bit, i64 -1
101 %addr_anyext = bitcast i8* %addr8_anyext to i16*
102 %val16_anyext = load volatile i16* %addr_anyext
103 %newval16 = add i16 %val16_anyext, 1
104 store volatile i16 %newval16, i16* @var_16bit
105 ; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #-1]
107 ; match a sign-extending load volatile 16-bit -> 64-bit
108 %addr8_sext64 = getelementptr i8* %addr_8bit, i64 -5
109 %addr_sext64 = bitcast i8* %addr8_sext64 to i16*
110 %val16_sext64 = load volatile i16* %addr_sext64
111 %val64_signed = sext i16 %val16_sext64 to i64
112 store volatile i64 %val64_signed, i64* @var_64bit
113 ; CHECK: ldursh {{x[0-9]+}}, [{{x[0-9]+}}, #-5]
115 ; match a zero-extending load volatile 16-bit -> 64-bit.
116 ; This uses the fact that ldrb w0, [x0] will zero out the high 32-bits
117 ; of x0 so it's identical to load volatileing to 32-bits.
118 %addr8_zext64 = getelementptr i8* %addr_8bit, i64 9
119 %addr_zext64 = bitcast i8* %addr8_zext64 to i16*
120 %val16_zext64 = load volatile i16* %addr_zext64
121 %val64_unsigned = zext i16 %val16_zext64 to i64
122 store volatile i64 %val64_unsigned, i64* @var_64bit
123 ; CHECK: ldurh {{w[0-9]+}}, [{{x[0-9]+}}, #9]
125 ; truncating store volatile 32-bits to 16-bits
126 %addr8_trunc32 = getelementptr i8* %addr_8bit, i64 -256
127 %addr_trunc32 = bitcast i8* %addr8_trunc32 to i16*
128 %val32 = load volatile i32* @var_32bit
129 %val16_trunc32 = trunc i32 %val32 to i16
130 store volatile i16 %val16_trunc32, i16* %addr_trunc32
131 ; CHECK: sturh {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
133 ; truncating store volatile 64-bits to 16-bits
134 %addr8_trunc64 = getelementptr i8* %addr_8bit, i64 -1
135 %addr_trunc64 = bitcast i8* %addr8_trunc64 to i16*
136 %val64 = load volatile i64* @var_64bit
137 %val16_trunc64 = trunc i64 %val64 to i16
138 store volatile i16 %val16_trunc64, i16* %addr_trunc64
139 ; CHECK: sturh {{w[0-9]+}}, [{{x[0-9]+}}, #-1]
144 define void @ldst_32bit() {
145 ; CHECK-LABEL: ldst_32bit:
147 %addr_8bit = load i8** @varptr
149 ; Straight 32-bit load/store
150 %addr32_8_noext = getelementptr i8* %addr_8bit, i64 1
151 %addr32_noext = bitcast i8* %addr32_8_noext to i32*
152 %val32_noext = load volatile i32* %addr32_noext
153 store volatile i32 %val32_noext, i32* %addr32_noext
154 ; CHECK: ldur {{w[0-9]+}}, [{{x[0-9]+}}, #1]
155 ; CHECK: stur {{w[0-9]+}}, [{{x[0-9]+}}, #1]
157 ; Zero-extension to 64-bits
158 %addr32_8_zext = getelementptr i8* %addr_8bit, i64 -256
159 %addr32_zext = bitcast i8* %addr32_8_zext to i32*
160 %val32_zext = load volatile i32* %addr32_zext
161 %val64_unsigned = zext i32 %val32_zext to i64
162 store volatile i64 %val64_unsigned, i64* @var_64bit
163 ; CHECK: ldur {{w[0-9]+}}, [{{x[0-9]+}}, #-256]
164 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
166 ; Sign-extension to 64-bits
167 %addr32_8_sext = getelementptr i8* %addr_8bit, i64 -12
168 %addr32_sext = bitcast i8* %addr32_8_sext to i32*
169 %val32_sext = load volatile i32* %addr32_sext
170 %val64_signed = sext i32 %val32_sext to i64
171 store volatile i64 %val64_signed, i64* @var_64bit
172 ; CHECK: ldursw {{x[0-9]+}}, [{{x[0-9]+}}, #-12]
173 ; CHECK: str {{x[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var_64bit]
175 ; Truncation from 64-bits
176 %addr64_8_trunc = getelementptr i8* %addr_8bit, i64 255
177 %addr64_trunc = bitcast i8* %addr64_8_trunc to i64*
178 %addr32_8_trunc = getelementptr i8* %addr_8bit, i64 -20
179 %addr32_trunc = bitcast i8* %addr32_8_trunc to i32*
181 %val64_trunc = load volatile i64* %addr64_trunc
182 %val32_trunc = trunc i64 %val64_trunc to i32
183 store volatile i32 %val32_trunc, i32* %addr32_trunc
184 ; CHECK: ldur {{x[0-9]+}}, [{{x[0-9]+}}, #255]
185 ; CHECK: stur {{w[0-9]+}}, [{{x[0-9]+}}, #-20]
190 define void @ldst_float() {
191 ; CHECK-LABEL: ldst_float:
193 %addr_8bit = load i8** @varptr
194 %addrfp_8 = getelementptr i8* %addr_8bit, i64 -5
195 %addrfp = bitcast i8* %addrfp_8 to float*
197 %valfp = load volatile float* %addrfp
198 ; CHECK: ldur {{s[0-9]+}}, [{{x[0-9]+}}, #-5]
199 ; CHECK-NOFP-NOT: ldur {{s[0-9]+}},
201 store volatile float %valfp, float* %addrfp
202 ; CHECK: stur {{s[0-9]+}}, [{{x[0-9]+}}, #-5]
203 ; CHECK-NOFP-NOT: stur {{s[0-9]+}},
208 define void @ldst_double() {
209 ; CHECK-LABEL: ldst_double:
211 %addr_8bit = load i8** @varptr
212 %addrfp_8 = getelementptr i8* %addr_8bit, i64 4
213 %addrfp = bitcast i8* %addrfp_8 to double*
215 %valfp = load volatile double* %addrfp
216 ; CHECK: ldur {{d[0-9]+}}, [{{x[0-9]+}}, #4]
217 ; CHECK-NOFP-NOT: ldur {{d[0-9]+}},
219 store volatile double %valfp, double* %addrfp
220 ; CHECK: stur {{d[0-9]+}}, [{{x[0-9]+}}, #4]
221 ; CHECK-NOFP-NOT: stur {{d[0-9]+}},