1 ; RUN: llc -verify-machineinstrs -march=aarch64 < %s | FileCheck %s
2 declare void @use_addr(i8*)
4 @addr = global i8* null
6 define void @test_bigframe() {
7 ; CHECK: test_bigframe:
9 %var1 = alloca i8, i32 20000000
10 %var2 = alloca i8, i32 16
11 %var3 = alloca i8, i32 20000000
12 ; CHECK: sub sp, sp, #496
13 ; CHECK: str x30, [sp, #488]
14 ; CHECK: ldr [[FRAMEOFFSET:x[0-9]+]], [[FRAMEOFFSET_CPI:.LCPI0_[0-9]+]]
15 ; CHECK: sub sp, sp, [[FRAMEOFFSET]]
17 ; CHECK: ldr [[VAR1OFFSET:x[0-9]+]], [[VAR1LOC_CPI:.LCPI0_[0-9]+]]
18 ; CHECK: add {{x[0-9]+}}, sp, [[VAR1OFFSET]]
19 store volatile i8* %var1, i8** @addr
21 %var1plus2 = getelementptr i8* %var1, i32 2
22 store volatile i8* %var1plus2, i8** @addr
24 ; CHECK: ldr [[VAR2OFFSET:x[0-9]+]], [[VAR2LOC_CPI:.LCPI0_[0-9]+]]
25 ; CHECK: add {{x[0-9]+}}, sp, [[VAR2OFFSET]]
26 store volatile i8* %var2, i8** @addr
28 %var2plus2 = getelementptr i8* %var2, i32 2
29 store volatile i8* %var2plus2, i8** @addr
31 store volatile i8* %var3, i8** @addr
33 %var3plus2 = getelementptr i8* %var3, i32 2
34 store volatile i8* %var3plus2, i8** @addr
36 ; CHECK: ldr [[FRAMEOFFSET:x[0-9]+]], [[FRAMEOFFSET_CPI]]
37 ; CHECK: add sp, sp, [[FRAMEOFFSET]]
40 ; CHECK: [[FRAMEOFFSET_CPI]]:
41 ; CHECK-NEXT: 39999536
43 ; CHECK: [[VAR1LOC_CPI]]:
44 ; CHECK-NEXT: 20000024
46 ; CHECK: [[VAR2LOC_CPI]]:
47 ; CHECK-NEXT: 20000008
50 define void @test_mediumframe() {
51 ; CHECK: test_mediumframe:
52 %var1 = alloca i8, i32 1000000
53 %var2 = alloca i8, i32 16
54 %var3 = alloca i8, i32 1000000
55 ; CHECK: sub sp, sp, #496
56 ; CHECK: str x30, [sp, #488]
57 ; CHECK: sub sp, sp, #688
58 ; CHECK-NEXT: sub sp, sp, #488, lsl #12
60 store volatile i8* %var1, i8** @addr
61 ; CHECK: add [[VAR1ADDR:x[0-9]+]], sp, #600
62 ; CHECK: add [[VAR1ADDR]], [[VAR1ADDR]], #244, lsl #12
64 %var1plus2 = getelementptr i8* %var1, i32 2
65 store volatile i8* %var1plus2, i8** @addr
66 ; CHECK: add [[VAR1PLUS2:x[0-9]+]], {{x[0-9]+}}, #2
68 store volatile i8* %var2, i8** @addr
69 ; CHECK: add [[VAR2ADDR:x[0-9]+]], sp, #584
70 ; CHECK: add [[VAR2ADDR]], [[VAR2ADDR]], #244, lsl #12
72 %var2plus2 = getelementptr i8* %var2, i32 2
73 store volatile i8* %var2plus2, i8** @addr
74 ; CHECK: add [[VAR2PLUS2:x[0-9]+]], {{x[0-9]+}}, #2
76 store volatile i8* %var3, i8** @addr
78 %var3plus2 = getelementptr i8* %var3, i32 2
79 store volatile i8* %var3plus2, i8** @addr
81 ; CHECK: add sp, sp, #688
82 ; CHECK: add sp, sp, #488, lsl #12
83 ; CHECK: ldr x30, [sp, #488]
84 ; CHECK: add sp, sp, #496
89 @bigspace = global [8 x i64] zeroinitializer
91 ; If temporary registers are allocated for adjustment, they should *not* clobber
93 define void @test_tempallocation([8 x i64] %val) nounwind {
94 ; CHECK: test_tempallocation:
95 %var = alloca i8, i32 1000000
98 ; Make sure the prologue is reasonably efficient
99 ; CHECK-NEXT: stp x29, x30, [sp,
100 ; CHECK-NEXT: stp x25, x26, [sp,
101 ; CHECK-NEXT: stp x23, x24, [sp,
102 ; CHECK-NEXT: stp x21, x22, [sp,
103 ; CHECK-NEXT: stp x19, x20, [sp,
105 ; Make sure we don't trash an argument register
106 ; CHECK-NOT: ldr {{x[0-7]}}, .LCPI1
109 ; CHECK-NOT: ldr {{x[0-7]}}, .LCPI1
112 call void @use_addr(i8* %var)
114 store [8 x i64] %val, [8 x i64]* @bigspace