1 ; RUN: llc < %s -asm-verbose=false -mtriple=aarch64-none-eabi | FileCheck %s
3 define <4 x half> @add_h(<4 x half> %a, <4 x half> %b) {
6 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
7 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
8 ; CHECK: fadd [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
9 ; CHECK: fcvtn v0.4h, [[RES]]
10 %0 = fadd <4 x half> %a, %b
15 define <4 x half> @build_h4(<4 x half> %a) {
17 ; CHECK-LABEL: build_h4:
18 ; CHECK: movz [[GPR:w[0-9]+]], #0x3ccd
19 ; CHECK: dup v0.4h, [[GPR]]
20 ret <4 x half> <half 0xH3CCD, half 0xH3CCD, half 0xH3CCD, half 0xH3CCD>
24 define <4 x half> @sub_h(<4 x half> %a, <4 x half> %b) {
27 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
28 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
29 ; CHECK: fsub [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
30 ; CHECK: fcvtn v0.4h, [[RES]]
31 %0 = fsub <4 x half> %a, %b
36 define <4 x half> @mul_h(<4 x half> %a, <4 x half> %b) {
39 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
40 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
41 ; CHECK: fmul [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
42 ; CHECK: fcvtn v0.4h, [[RES]]
43 %0 = fmul <4 x half> %a, %b
48 define <4 x half> @div_h(<4 x half> %a, <4 x half> %b) {
51 ; CHECK-DAG: fcvtl [[OP1:v[0-9]+\.4s]], v0.4h
52 ; CHECK-DAG: fcvtl [[OP2:v[0-9]+\.4s]], v1.4h
53 ; CHECK: fdiv [[RES:v[0-9]+.4s]], [[OP1]], [[OP2]]
54 ; CHECK: fcvtn v0.4h, [[RES]]
55 %0 = fdiv <4 x half> %a, %b
60 define <4 x half> @load_h(<4 x half>* %a) {
62 ; CHECK-LABEL: load_h:
64 %0 = load <4 x half>, <4 x half>* %a, align 4
69 define void @store_h(<4 x half>* %a, <4 x half> %b) {
71 ; CHECK-LABEL: store_h:
73 store <4 x half> %b, <4 x half>* %a, align 4
77 define <4 x half> @s_to_h(<4 x float> %a) {
78 ; CHECK-LABEL: s_to_h:
79 ; CHECK: fcvtn v0.4h, v0.4s
80 %1 = fptrunc <4 x float> %a to <4 x half>
84 define <4 x half> @d_to_h(<4 x double> %a) {
85 ; CHECK-LABEL: d_to_h:
94 %1 = fptrunc <4 x double> %a to <4 x half>
98 define <4 x float> @h_to_s(<4 x half> %a) {
99 ; CHECK-LABEL: h_to_s:
100 ; CHECK: fcvtl v0.4s, v0.4h
101 %1 = fpext <4 x half> %a to <4 x float>
105 define <4 x double> @h_to_d(<4 x half> %a) {
106 ; CHECK-LABEL: h_to_d:
115 %1 = fpext <4 x half> %a to <4 x double>
119 define <4 x half> @bitcast_i_to_h(float, <4 x i16> %a) {
120 ; CHECK-LABEL: bitcast_i_to_h:
121 ; CHECK: mov v0.16b, v1.16b
122 %2 = bitcast <4 x i16> %a to <4 x half>
126 define <4 x i16> @bitcast_h_to_i(float, <4 x half> %a) {
127 ; CHECK-LABEL: bitcast_h_to_i:
128 ; CHECK: mov v0.16b, v1.16b
129 %2 = bitcast <4 x half> %a to <4 x i16>
133 define <4 x half> @sitofp_i8(<4 x i8> %a) #0 {
134 ; CHECK-LABEL: sitofp_i8:
135 ; CHECK-NEXT: shl [[OP1:v[0-9]+\.4h]], v0.4h, #8
136 ; CHECK-NEXT: sshr [[OP2:v[0-9]+\.4h]], [[OP1]], #8
137 ; CHECK-NEXT: sshll [[OP3:v[0-9]+\.4s]], [[OP2]], #0
138 ; CHECK-NEXT: scvtf [[OP4:v[0-9]+\.4s]], [[OP3]]
139 ; CHECK-NEXT: fcvtn v0.4h, [[OP4]]
141 %1 = sitofp <4 x i8> %a to <4 x half>
146 define <4 x half> @sitofp_i16(<4 x i16> %a) #0 {
147 ; CHECK-LABEL: sitofp_i16:
148 ; CHECK-NEXT: sshll [[OP1:v[0-9]+\.4s]], v0.4h, #0
149 ; CHECK-NEXT: scvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
150 ; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
152 %1 = sitofp <4 x i16> %a to <4 x half>
157 define <4 x half> @sitofp_i32(<4 x i32> %a) #0 {
158 ; CHECK-LABEL: sitofp_i32:
159 ; CHECK-NEXT: scvtf [[OP1:v[0-9]+\.4s]], v0.4s
160 ; CHECK-NEXT: fcvtn v0.4h, [[OP1]]
161 %1 = sitofp <4 x i32> %a to <4 x half>
166 define <4 x half> @sitofp_i64(<4 x i64> %a) #0 {
167 ; CHECK-LABEL: sitofp_i64:
168 ; CHECK-DAG: scvtf [[OP1:v[0-9]+\.2d]], v0.2d
169 ; CHECK-DAG: scvtf [[OP2:v[0-9]+\.2d]], v1.2d
170 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
171 ; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
172 ; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s
173 %1 = sitofp <4 x i64> %a to <4 x half>
177 define <4 x half> @uitofp_i8(<4 x i8> %a) #0 {
178 ; CHECK-LABEL: uitofp_i8:
179 ; CHECK-NEXT: bic v0.4h, #0xff, lsl #8
180 ; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
181 ; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
182 ; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
184 %1 = uitofp <4 x i8> %a to <4 x half>
189 define <4 x half> @uitofp_i16(<4 x i16> %a) #0 {
190 ; CHECK-LABEL: uitofp_i16:
191 ; CHECK-NEXT: ushll [[OP1:v[0-9]+\.4s]], v0.4h, #0
192 ; CHECK-NEXT: ucvtf [[OP2:v[0-9]+\.4s]], [[OP1]]
193 ; CHECK-NEXT: fcvtn v0.4h, [[OP2]]
195 %1 = uitofp <4 x i16> %a to <4 x half>
200 define <4 x half> @uitofp_i32(<4 x i32> %a) #0 {
201 ; CHECK-LABEL: uitofp_i32:
202 ; CHECK-NEXT: ucvtf [[OP1:v[0-9]+\.4s]], v0.4s
203 ; CHECK-NEXT: fcvtn v0.4h, [[OP1]]
204 %1 = uitofp <4 x i32> %a to <4 x half>
209 define <4 x half> @uitofp_i64(<4 x i64> %a) #0 {
210 ; CHECK-LABEL: uitofp_i64:
211 ; CHECK-DAG: ucvtf [[OP1:v[0-9]+\.2d]], v0.2d
212 ; CHECK-DAG: ucvtf [[OP2:v[0-9]+\.2d]], v1.2d
213 ; CHECK-DAG: fcvtn [[OP3:v[0-9]+]].2s, [[OP1]]
214 ; CHECK-NEXT: fcvtn2 [[OP3]].4s, [[OP2]]
215 ; CHECK-NEXT: fcvtn v0.4h, [[OP3]].4s
216 %1 = uitofp <4 x i64> %a to <4 x half>
220 define void @test_insert_at_zero(half %a, <4 x half>* %b) #0 {
221 ; CHECK-LABEL: test_insert_at_zero:
222 ; CHECK-NEXT: str d0, [x0]
224 %1 = insertelement <4 x half> undef, half %a, i64 0
225 store <4 x half> %1, <4 x half>* %b, align 4
229 define <4 x i8> @fptosi_i8(<4 x half> %a) #0 {
230 ; CHECK-LABEL: fptosi_i8:
231 ; CHECK-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h
232 ; CHECK-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
233 ; CHECK-NEXT: xtn v0.4h, [[REG2]]
235 %1 = fptosi<4 x half> %a to <4 x i8>
239 define <4 x i16> @fptosi_i16(<4 x half> %a) #0 {
240 ; CHECK-LABEL: fptosi_i16:
241 ; CHECK-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h
242 ; CHECK-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
243 ; CHECK-NEXT: xtn v0.4h, [[REG2]]
245 %1 = fptosi<4 x half> %a to <4 x i16>
249 define <4 x i8> @fptoui_i8(<4 x half> %a) #0 {
250 ; CHECK-LABEL: fptoui_i8:
251 ; CHECK-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h
252 ; NOTE: fcvtzs selected here because the xtn shaves the sign bit
253 ; CHECK-NEXT: fcvtzs [[REG2:v[0-9]+\.4s]], [[REG1]]
254 ; CHECK-NEXT: xtn v0.4h, [[REG2]]
256 %1 = fptoui<4 x half> %a to <4 x i8>
260 define <4 x i16> @fptoui_i16(<4 x half> %a) #0 {
261 ; CHECK-LABEL: fptoui_i16:
262 ; CHECK-NEXT: fcvtl [[REG1:v[0-9]+\.4s]], v0.4h
263 ; CHECK-NEXT: fcvtzu [[REG2:v[0-9]+\.4s]], [[REG1]]
264 ; CHECK-NEXT: xtn v0.4h, [[REG2]]
266 %1 = fptoui<4 x half> %a to <4 x i16>
270 ; Function Attrs: nounwind readnone
271 ; CHECK-LABEL: test_fcmp_une:
280 ; CHECK-DAG: csel {{.*}}, wzr, ne
281 ; CHECK-DAG: csel {{.*}}, wzr, ne
282 ; CHECK-DAG: csel {{.*}}, wzr, ne
283 ; CHECK-DAG: csel {{.*}}, wzr, ne
284 define <4 x i1> @test_fcmp_une(<4 x half> %a, <4 x half> %b) #0 {
285 %1 = fcmp une <4 x half> %a, %b
289 ; Function Attrs: nounwind readnone
290 ; CHECK-LABEL: test_fcmp_ueq:
299 ; CHECK-DAG: csel {{.*}}, wzr, eq
300 ; CHECK-DAG: csel {{.*}}, wzr, eq
301 ; CHECK-DAG: csel {{.*}}, wzr, eq
302 ; CHECK-DAG: csel {{.*}}, wzr, eq
303 ; CHECK-DAG: csel {{.*}}, vs
304 ; CHECK-DAG: csel {{.*}}, vs
305 ; CHECK-DAG: csel {{.*}}, vs
306 ; CHECK-DAG: csel {{.*}}, vs
307 define <4 x i1> @test_fcmp_ueq(<4 x half> %a, <4 x half> %b) #0 {
308 %1 = fcmp ueq <4 x half> %a, %b
312 ; Function Attrs: nounwind readnone
313 ; CHECK-LABEL: test_fcmp_ugt:
322 ; CHECK-DAG: csel {{.*}}, wzr, hi
323 ; CHECK-DAG: csel {{.*}}, wzr, hi
324 ; CHECK-DAG: csel {{.*}}, wzr, hi
325 ; CHECK-DAG: csel {{.*}}, wzr, hi
326 define <4 x i1> @test_fcmp_ugt(<4 x half> %a, <4 x half> %b) #0 {
327 %1 = fcmp ugt <4 x half> %a, %b
331 ; Function Attrs: nounwind readnone
332 ; CHECK-LABEL: test_fcmp_uge:
341 ; CHECK-DAG: csel {{.*}}, wzr, pl
342 ; CHECK-DAG: csel {{.*}}, wzr, pl
343 ; CHECK-DAG: csel {{.*}}, wzr, pl
344 ; CHECK-DAG: csel {{.*}}, wzr, pl
345 define <4 x i1> @test_fcmp_uge(<4 x half> %a, <4 x half> %b) #0 {
346 %1 = fcmp uge <4 x half> %a, %b
350 ; Function Attrs: nounwind readnone
351 ; CHECK-LABEL: test_fcmp_ult:
360 ; CHECK-DAG: csel {{.*}}, wzr, lt
361 ; CHECK-DAG: csel {{.*}}, wzr, lt
362 ; CHECK-DAG: csel {{.*}}, wzr, lt
363 ; CHECK-DAG: csel {{.*}}, wzr, lt
364 define <4 x i1> @test_fcmp_ult(<4 x half> %a, <4 x half> %b) #0 {
365 %1 = fcmp ult <4 x half> %a, %b
369 ; Function Attrs: nounwind readnone
370 ; CHECK-LABEL: test_fcmp_ule:
379 ; CHECK-DAG: csel {{.*}}, wzr, le
380 ; CHECK-DAG: csel {{.*}}, wzr, le
381 ; CHECK-DAG: csel {{.*}}, wzr, le
382 ; CHECK-DAG: csel {{.*}}, wzr, le
383 define <4 x i1> @test_fcmp_ule(<4 x half> %a, <4 x half> %b) #0 {
384 %1 = fcmp ule <4 x half> %a, %b
388 ; Function Attrs: nounwind readnone
389 ; CHECK-LABEL: test_fcmp_uno:
398 ; CHECK-DAG: csel {{.*}}, wzr, vs
399 ; CHECK-DAG: csel {{.*}}, wzr, vs
400 ; CHECK-DAG: csel {{.*}}, wzr, vs
401 ; CHECK-DAG: csel {{.*}}, wzr, vs
402 define <4 x i1> @test_fcmp_uno(<4 x half> %a, <4 x half> %b) #0 {
403 %1 = fcmp uno <4 x half> %a, %b
407 ; Function Attrs: nounwind readnone
408 ; CHECK-LABEL: test_fcmp_one:
417 ; CHECK-DAG: csel {{.*}}, wzr, mi
418 ; CHECK-DAG: csel {{.*}}, wzr, mi
419 ; CHECK-DAG: csel {{.*}}, wzr, mi
420 ; CHECK-DAG: csel {{.*}}, wzr, mi
421 ; CHECK-DAG: csel {{.*}}, gt
422 ; CHECK-DAG: csel {{.*}}, gt
423 ; CHECK-DAG: csel {{.*}}, gt
424 ; CHECK-DAG: csel {{.*}}, gt
425 define <4 x i1> @test_fcmp_one(<4 x half> %a, <4 x half> %b) #0 {
426 %1 = fcmp one <4 x half> %a, %b
430 ; Function Attrs: nounwind readnone
431 ; CHECK-LABEL: test_fcmp_oeq:
440 ; CHECK-DAG: csel {{.*}}, wzr, eq
441 ; CHECK-DAG: csel {{.*}}, wzr, eq
442 ; CHECK-DAG: csel {{.*}}, wzr, eq
443 ; CHECK-DAG: csel {{.*}}, wzr, eq
444 define <4 x i1> @test_fcmp_oeq(<4 x half> %a, <4 x half> %b) #0 {
445 %1 = fcmp oeq <4 x half> %a, %b
449 ; Function Attrs: nounwind readnone
450 ; CHECK-LABEL: test_fcmp_ogt:
459 ; CHECK-DAG: csel {{.*}}, wzr, gt
460 ; CHECK-DAG: csel {{.*}}, wzr, gt
461 ; CHECK-DAG: csel {{.*}}, wzr, gt
462 ; CHECK-DAG: csel {{.*}}, wzr, gt
463 define <4 x i1> @test_fcmp_ogt(<4 x half> %a, <4 x half> %b) #0 {
464 %1 = fcmp ogt <4 x half> %a, %b
468 ; Function Attrs: nounwind readnone
469 ; CHECK-LABEL: test_fcmp_oge:
478 ; CHECK-DAG: csel {{.*}}, wzr, ge
479 ; CHECK-DAG: csel {{.*}}, wzr, ge
480 ; CHECK-DAG: csel {{.*}}, wzr, ge
481 ; CHECK-DAG: csel {{.*}}, wzr, ge
482 define <4 x i1> @test_fcmp_oge(<4 x half> %a, <4 x half> %b) #0 {
483 %1 = fcmp oge <4 x half> %a, %b
487 ; Function Attrs: nounwind readnone
488 ; CHECK-LABEL: test_fcmp_olt:
497 ; CHECK-DAG: csel {{.*}}, wzr, mi
498 ; CHECK-DAG: csel {{.*}}, wzr, mi
499 ; CHECK-DAG: csel {{.*}}, wzr, mi
500 ; CHECK-DAG: csel {{.*}}, wzr, mi
501 define <4 x i1> @test_fcmp_olt(<4 x half> %a, <4 x half> %b) #0 {
502 %1 = fcmp olt <4 x half> %a, %b
506 ; Function Attrs: nounwind readnone
507 ; CHECK-LABEL: test_fcmp_ole:
516 ; CHECK-DAG: csel {{.*}}, wzr, ls
517 ; CHECK-DAG: csel {{.*}}, wzr, ls
518 ; CHECK-DAG: csel {{.*}}, wzr, ls
519 ; CHECK-DAG: csel {{.*}}, wzr, ls
520 define <4 x i1> @test_fcmp_ole(<4 x half> %a, <4 x half> %b) #0 {
521 %1 = fcmp ole <4 x half> %a, %b
525 ; Function Attrs: nounwind readnone
526 ; CHECK-LABEL: test_fcmp_ord:
535 ; CHECK-DAG: csel {{.*}}, wzr, vc
536 ; CHECK-DAG: csel {{.*}}, wzr, vc
537 ; CHECK-DAG: csel {{.*}}, wzr, vc
538 ; CHECK-DAG: csel {{.*}}, wzr, vc
539 define <4 x i1> @test_fcmp_ord(<4 x half> %a, <4 x half> %b) #0 {
540 %1 = fcmp ord <4 x half> %a, %b
544 attributes #0 = { nounwind }