1 ; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
2 ; RUN: llc -mtriple=arm64 -o - %s | FileCheck %s
6 define i32 @test_sextloadi32() {
7 ; CHECK-LABEL: test_sextloadi32
10 %ret = sext i1 %val to i32
11 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
12 ; CHECK: {{sbfx x[0-9]+, x[0-9]+, #0, #1|sbfm w[0-9]+, w[0-9]+, #0, #0}}
18 define i64 @test_sextloadi64() {
19 ; CHECK-LABEL: test_sextloadi64
22 %ret = sext i1 %val to i64
23 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
24 ; CHECK: {{sbfx x[0-9]+, x[0-9]+, #0, #1|sbfm x[0-9]+, x[0-9]+, #0, #0}}
30 define i32 @test_zextloadi32() {
31 ; CHECK-LABEL: test_zextloadi32
33 ; It's not actually necessary that "ret" is next, but as far as LLVM
34 ; is concerned only 0 or 1 should be loadable so no extension is
37 %ret = zext i1 %val to i32
38 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]
44 define i64 @test_zextloadi64() {
45 ; CHECK-LABEL: test_zextloadi64
47 ; It's not actually necessary that "ret" is next, but as far as LLVM
48 ; is concerned only 0 or 1 should be loadable so no extension is
51 %ret = zext i1 %val to i64
52 ; CHECK: ldrb {{w[0-9]+}}, [{{x[0-9]+}}, {{#?}}:lo12:var]