1 ; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 < %s | FileCheck %s
2 ; RUN: llc -march=arm64 -aarch64-atomic-cfg-tidy=0 -fast-isel -fast-isel-abort < %s | FileCheck %s
5 ; Get the actual value of the overflow bit.
7 define zeroext i1 @saddo1.i32(i32 %v1, i32 %v2, i32* %res) {
9 ; CHECK-LABEL: saddo1.i32
10 ; CHECK: adds {{w[0-9]+}}, w0, w1
11 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
12 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
13 %val = extractvalue {i32, i1} %t, 0
14 %obit = extractvalue {i32, i1} %t, 1
15 store i32 %val, i32* %res
19 ; Test the immediate version.
20 define zeroext i1 @saddo2.i32(i32 %v1, i32* %res) {
22 ; CHECK-LABEL: saddo2.i32
23 ; CHECK: adds {{w[0-9]+}}, w0, #4
24 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
25 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 4)
26 %val = extractvalue {i32, i1} %t, 0
27 %obit = extractvalue {i32, i1} %t, 1
28 store i32 %val, i32* %res
32 ; Test negative immediates.
33 define zeroext i1 @saddo3.i32(i32 %v1, i32* %res) {
35 ; CHECK-LABEL: saddo3.i32
36 ; CHECK: subs {{w[0-9]+}}, w0, #4
37 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
38 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 -4)
39 %val = extractvalue {i32, i1} %t, 0
40 %obit = extractvalue {i32, i1} %t, 1
41 store i32 %val, i32* %res
45 ; Test immediates that are too large to be encoded.
46 define zeroext i1 @saddo4.i32(i32 %v1, i32* %res) {
48 ; CHECK-LABEL: saddo4.i32
49 ; CHECK: adds {{w[0-9]+}}, w0, {{w[0-9]+}}
50 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
51 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 16777215)
52 %val = extractvalue {i32, i1} %t, 0
53 %obit = extractvalue {i32, i1} %t, 1
54 store i32 %val, i32* %res
58 define zeroext i1 @saddo1.i64(i64 %v1, i64 %v2, i64* %res) {
60 ; CHECK-LABEL: saddo1.i64
61 ; CHECK: adds {{x[0-9]+}}, x0, x1
62 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
63 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
64 %val = extractvalue {i64, i1} %t, 0
65 %obit = extractvalue {i64, i1} %t, 1
66 store i64 %val, i64* %res
70 define zeroext i1 @saddo2.i64(i64 %v1, i64* %res) {
72 ; CHECK-LABEL: saddo2.i64
73 ; CHECK: adds {{x[0-9]+}}, x0, #4
74 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
75 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 4)
76 %val = extractvalue {i64, i1} %t, 0
77 %obit = extractvalue {i64, i1} %t, 1
78 store i64 %val, i64* %res
82 define zeroext i1 @saddo3.i64(i64 %v1, i64* %res) {
84 ; CHECK-LABEL: saddo3.i64
85 ; CHECK: subs {{x[0-9]+}}, x0, #4
86 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
87 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -4)
88 %val = extractvalue {i64, i1} %t, 0
89 %obit = extractvalue {i64, i1} %t, 1
90 store i64 %val, i64* %res
94 define zeroext i1 @uaddo.i32(i32 %v1, i32 %v2, i32* %res) {
96 ; CHECK-LABEL: uaddo.i32
97 ; CHECK: adds {{w[0-9]+}}, w0, w1
98 ; CHECK-NEXT: cset {{w[0-9]+}}, hs
99 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
100 %val = extractvalue {i32, i1} %t, 0
101 %obit = extractvalue {i32, i1} %t, 1
102 store i32 %val, i32* %res
106 define zeroext i1 @uaddo.i64(i64 %v1, i64 %v2, i64* %res) {
108 ; CHECK-LABEL: uaddo.i64
109 ; CHECK: adds {{x[0-9]+}}, x0, x1
110 ; CHECK-NEXT: cset {{w[0-9]+}}, hs
111 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
112 %val = extractvalue {i64, i1} %t, 0
113 %obit = extractvalue {i64, i1} %t, 1
114 store i64 %val, i64* %res
118 define zeroext i1 @ssubo1.i32(i32 %v1, i32 %v2, i32* %res) {
120 ; CHECK-LABEL: ssubo1.i32
121 ; CHECK: subs {{w[0-9]+}}, w0, w1
122 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
123 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
124 %val = extractvalue {i32, i1} %t, 0
125 %obit = extractvalue {i32, i1} %t, 1
126 store i32 %val, i32* %res
130 define zeroext i1 @ssubo2.i32(i32 %v1, i32* %res) {
132 ; CHECK-LABEL: ssubo2.i32
133 ; CHECK: adds {{w[0-9]+}}, w0, #4
134 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
135 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 -4)
136 %val = extractvalue {i32, i1} %t, 0
137 %obit = extractvalue {i32, i1} %t, 1
138 store i32 %val, i32* %res
142 define zeroext i1 @ssubo.i64(i64 %v1, i64 %v2, i64* %res) {
144 ; CHECK-LABEL: ssubo.i64
145 ; CHECK: subs {{x[0-9]+}}, x0, x1
146 ; CHECK-NEXT: cset {{w[0-9]+}}, vs
147 %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
148 %val = extractvalue {i64, i1} %t, 0
149 %obit = extractvalue {i64, i1} %t, 1
150 store i64 %val, i64* %res
154 define zeroext i1 @usubo.i32(i32 %v1, i32 %v2, i32* %res) {
156 ; CHECK-LABEL: usubo.i32
157 ; CHECK: subs {{w[0-9]+}}, w0, w1
158 ; CHECK-NEXT: cset {{w[0-9]+}}, lo
159 %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
160 %val = extractvalue {i32, i1} %t, 0
161 %obit = extractvalue {i32, i1} %t, 1
162 store i32 %val, i32* %res
166 define zeroext i1 @usubo.i64(i64 %v1, i64 %v2, i64* %res) {
168 ; CHECK-LABEL: usubo.i64
169 ; CHECK: subs {{x[0-9]+}}, x0, x1
170 ; CHECK-NEXT: cset {{w[0-9]+}}, lo
171 %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
172 %val = extractvalue {i64, i1} %t, 0
173 %obit = extractvalue {i64, i1} %t, 1
174 store i64 %val, i64* %res
178 define zeroext i1 @smulo.i32(i32 %v1, i32 %v2, i32* %res) {
180 ; CHECK-LABEL: smulo.i32
181 ; CHECK: smull x[[MREG:[0-9]+]], w0, w1
182 ; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x[[MREG]], #32
183 ; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
184 ; CHECK-NEXT: cset {{w[0-9]+}}, ne
185 %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
186 %val = extractvalue {i32, i1} %t, 0
187 %obit = extractvalue {i32, i1} %t, 1
188 store i32 %val, i32* %res
192 define zeroext i1 @smulo.i64(i64 %v1, i64 %v2, i64* %res) {
194 ; CHECK-LABEL: smulo.i64
195 ; CHECK: mul [[MREG:x[0-9]+]], x0, x1
196 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
197 ; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
198 ; CHECK-NEXT: cset {{w[0-9]+}}, ne
199 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
200 %val = extractvalue {i64, i1} %t, 0
201 %obit = extractvalue {i64, i1} %t, 1
202 store i64 %val, i64* %res
206 define zeroext i1 @umulo.i32(i32 %v1, i32 %v2, i32* %res) {
208 ; CHECK-LABEL: umulo.i32
209 ; CHECK: umull [[MREG:x[0-9]+]], w0, w1
210 ; CHECK-NEXT: cmp xzr, [[MREG]], lsr #32
211 ; CHECK-NEXT: cset {{w[0-9]+}}, ne
212 %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
213 %val = extractvalue {i32, i1} %t, 0
214 %obit = extractvalue {i32, i1} %t, 1
215 store i32 %val, i32* %res
219 define zeroext i1 @umulo.i64(i64 %v1, i64 %v2, i64* %res) {
221 ; CHECK-LABEL: umulo.i64
222 ; CHECK: umulh [[MREG:x[0-9]+]], x0, x1
223 ; CHECK-NEXT: cmp xzr, [[MREG]]
224 ; CHECK-NEXT: cset {{w[0-9]+}}, ne
225 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
226 %val = extractvalue {i64, i1} %t, 0
227 %obit = extractvalue {i64, i1} %t, 1
228 store i64 %val, i64* %res
234 ; Check the use of the overflow bit in combination with a select instruction.
236 define i32 @saddo.select.i32(i32 %v1, i32 %v2) {
238 ; CHECK-LABEL: saddo.select.i32
240 ; CHECK-NEXT: csel w0, w0, w1, vs
241 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
242 %obit = extractvalue {i32, i1} %t, 1
243 %ret = select i1 %obit, i32 %v1, i32 %v2
247 define i64 @saddo.select.i64(i64 %v1, i64 %v2) {
249 ; CHECK-LABEL: saddo.select.i64
251 ; CHECK-NEXT: csel x0, x0, x1, vs
252 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
253 %obit = extractvalue {i64, i1} %t, 1
254 %ret = select i1 %obit, i64 %v1, i64 %v2
258 define i32 @uaddo.select.i32(i32 %v1, i32 %v2) {
260 ; CHECK-LABEL: uaddo.select.i32
262 ; CHECK-NEXT: csel w0, w0, w1, hs
263 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
264 %obit = extractvalue {i32, i1} %t, 1
265 %ret = select i1 %obit, i32 %v1, i32 %v2
269 define i64 @uaddo.select.i64(i64 %v1, i64 %v2) {
271 ; CHECK-LABEL: uaddo.select.i64
273 ; CHECK-NEXT: csel x0, x0, x1, hs
274 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
275 %obit = extractvalue {i64, i1} %t, 1
276 %ret = select i1 %obit, i64 %v1, i64 %v2
280 define i32 @ssubo.select.i32(i32 %v1, i32 %v2) {
282 ; CHECK-LABEL: ssubo.select.i32
284 ; CHECK-NEXT: csel w0, w0, w1, vs
285 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
286 %obit = extractvalue {i32, i1} %t, 1
287 %ret = select i1 %obit, i32 %v1, i32 %v2
291 define i64 @ssubo.select.i64(i64 %v1, i64 %v2) {
293 ; CHECK-LABEL: ssubo.select.i64
295 ; CHECK-NEXT: csel x0, x0, x1, vs
296 %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
297 %obit = extractvalue {i64, i1} %t, 1
298 %ret = select i1 %obit, i64 %v1, i64 %v2
302 define i32 @usubo.select.i32(i32 %v1, i32 %v2) {
304 ; CHECK-LABEL: usubo.select.i32
306 ; CHECK-NEXT: csel w0, w0, w1, lo
307 %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
308 %obit = extractvalue {i32, i1} %t, 1
309 %ret = select i1 %obit, i32 %v1, i32 %v2
313 define i64 @usubo.select.i64(i64 %v1, i64 %v2) {
315 ; CHECK-LABEL: usubo.select.i64
317 ; CHECK-NEXT: csel x0, x0, x1, lo
318 %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
319 %obit = extractvalue {i64, i1} %t, 1
320 %ret = select i1 %obit, i64 %v1, i64 %v2
324 define i32 @smulo.select.i32(i32 %v1, i32 %v2) {
326 ; CHECK-LABEL: smulo.select.i32
327 ; CHECK: smull x[[MREG:[0-9]+]], w0, w1
328 ; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x[[MREG]], #32
329 ; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
330 ; CHECK-NEXT: csel w0, w0, w1, ne
331 %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
332 %obit = extractvalue {i32, i1} %t, 1
333 %ret = select i1 %obit, i32 %v1, i32 %v2
337 define i64 @smulo.select.i64(i64 %v1, i64 %v2) {
339 ; CHECK-LABEL: smulo.select.i64
340 ; CHECK: mul [[MREG:x[0-9]+]], x0, x1
341 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
342 ; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
343 ; CHECK-NEXT: csel x0, x0, x1, ne
344 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
345 %obit = extractvalue {i64, i1} %t, 1
346 %ret = select i1 %obit, i64 %v1, i64 %v2
350 define i32 @umulo.select.i32(i32 %v1, i32 %v2) {
352 ; CHECK-LABEL: umulo.select.i32
353 ; CHECK: umull [[MREG:x[0-9]+]], w0, w1
354 ; CHECK-NEXT: cmp xzr, [[MREG]], lsr #32
355 ; CHECK-NEXT: csel w0, w0, w1, ne
356 %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
357 %obit = extractvalue {i32, i1} %t, 1
358 %ret = select i1 %obit, i32 %v1, i32 %v2
362 define i64 @umulo.select.i64(i64 %v1, i64 %v2) {
364 ; CHECK-LABEL: umulo.select.i64
365 ; CHECK: umulh [[MREG:x[0-9]+]], x0, x1
366 ; CHECK-NEXT: cmp xzr, [[MREG]]
367 ; CHECK-NEXT: csel x0, x0, x1, ne
368 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
369 %obit = extractvalue {i64, i1} %t, 1
370 %ret = select i1 %obit, i64 %v1, i64 %v2
376 ; Check the use of the overflow bit in combination with a branch instruction.
378 define zeroext i1 @saddo.br.i32(i32 %v1, i32 %v2) {
380 ; CHECK-LABEL: saddo.br.i32
383 %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2)
384 %val = extractvalue {i32, i1} %t, 0
385 %obit = extractvalue {i32, i1} %t, 1
386 br i1 %obit, label %overflow, label %continue
395 define zeroext i1 @saddo.br.i64(i64 %v1, i64 %v2) {
397 ; CHECK-LABEL: saddo.br.i64
400 %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2)
401 %val = extractvalue {i64, i1} %t, 0
402 %obit = extractvalue {i64, i1} %t, 1
403 br i1 %obit, label %overflow, label %continue
412 define zeroext i1 @uaddo.br.i32(i32 %v1, i32 %v2) {
414 ; CHECK-LABEL: uaddo.br.i32
417 %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2)
418 %val = extractvalue {i32, i1} %t, 0
419 %obit = extractvalue {i32, i1} %t, 1
420 br i1 %obit, label %overflow, label %continue
429 define zeroext i1 @uaddo.br.i64(i64 %v1, i64 %v2) {
431 ; CHECK-LABEL: uaddo.br.i64
434 %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2)
435 %val = extractvalue {i64, i1} %t, 0
436 %obit = extractvalue {i64, i1} %t, 1
437 br i1 %obit, label %overflow, label %continue
446 define zeroext i1 @ssubo.br.i32(i32 %v1, i32 %v2) {
448 ; CHECK-LABEL: ssubo.br.i32
451 %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2)
452 %val = extractvalue {i32, i1} %t, 0
453 %obit = extractvalue {i32, i1} %t, 1
454 br i1 %obit, label %overflow, label %continue
463 define zeroext i1 @ssubo.br.i64(i64 %v1, i64 %v2) {
465 ; CHECK-LABEL: ssubo.br.i64
468 %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2)
469 %val = extractvalue {i64, i1} %t, 0
470 %obit = extractvalue {i64, i1} %t, 1
471 br i1 %obit, label %overflow, label %continue
480 define zeroext i1 @usubo.br.i32(i32 %v1, i32 %v2) {
482 ; CHECK-LABEL: usubo.br.i32
485 %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2)
486 %val = extractvalue {i32, i1} %t, 0
487 %obit = extractvalue {i32, i1} %t, 1
488 br i1 %obit, label %overflow, label %continue
497 define zeroext i1 @usubo.br.i64(i64 %v1, i64 %v2) {
499 ; CHECK-LABEL: usubo.br.i64
502 %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2)
503 %val = extractvalue {i64, i1} %t, 0
504 %obit = extractvalue {i64, i1} %t, 1
505 br i1 %obit, label %overflow, label %continue
514 define zeroext i1 @smulo.br.i32(i32 %v1, i32 %v2) {
516 ; CHECK-LABEL: smulo.br.i32
517 ; CHECK: smull x[[MREG:[0-9]+]], w0, w1
518 ; CHECK-NEXT: lsr x[[SREG:[0-9]+]], x8, #32
519 ; CHECK-NEXT: cmp w[[SREG]], w[[MREG]], asr #31
521 %t = call {i32, i1} @llvm.smul.with.overflow.i32(i32 %v1, i32 %v2)
522 %val = extractvalue {i32, i1} %t, 0
523 %obit = extractvalue {i32, i1} %t, 1
524 br i1 %obit, label %overflow, label %continue
533 define zeroext i1 @smulo.br.i64(i64 %v1, i64 %v2) {
535 ; CHECK-LABEL: smulo.br.i64
536 ; CHECK: mul [[MREG:x[0-9]+]], x0, x1
537 ; CHECK-NEXT: smulh [[HREG:x[0-9]+]], x0, x1
538 ; CHECK-NEXT: cmp [[HREG]], [[MREG]], asr #63
540 %t = call {i64, i1} @llvm.smul.with.overflow.i64(i64 %v1, i64 %v2)
541 %val = extractvalue {i64, i1} %t, 0
542 %obit = extractvalue {i64, i1} %t, 1
543 br i1 %obit, label %overflow, label %continue
552 define zeroext i1 @umulo.br.i32(i32 %v1, i32 %v2) {
554 ; CHECK-LABEL: umulo.br.i32
555 ; CHECK: umull [[MREG:x[0-9]+]], w0, w1
556 ; CHECK-NEXT: cmp xzr, [[MREG]], lsr #32
558 %t = call {i32, i1} @llvm.umul.with.overflow.i32(i32 %v1, i32 %v2)
559 %val = extractvalue {i32, i1} %t, 0
560 %obit = extractvalue {i32, i1} %t, 1
561 br i1 %obit, label %overflow, label %continue
570 define zeroext i1 @umulo.br.i64(i64 %v1, i64 %v2) {
572 ; CHECK-LABEL: umulo.br.i64
573 ; CHECK: umulh [[REG:x[0-9]+]], x0, x1
574 ; CHECK-NEXT: {{cbz|cmp}}
575 %t = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %v1, i64 %v2)
576 %val = extractvalue {i64, i1} %t, 0
577 %obit = extractvalue {i64, i1} %t, 1
578 br i1 %obit, label %overflow, label %continue
587 declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) nounwind readnone
588 declare {i64, i1} @llvm.sadd.with.overflow.i64(i64, i64) nounwind readnone
589 declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) nounwind readnone
590 declare {i64, i1} @llvm.uadd.with.overflow.i64(i64, i64) nounwind readnone
591 declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) nounwind readnone
592 declare {i64, i1} @llvm.ssub.with.overflow.i64(i64, i64) nounwind readnone
593 declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) nounwind readnone
594 declare {i64, i1} @llvm.usub.with.overflow.i64(i64, i64) nounwind readnone
595 declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) nounwind readnone
596 declare {i64, i1} @llvm.smul.with.overflow.i64(i64, i64) nounwind readnone
597 declare {i32, i1} @llvm.umul.with.overflow.i32(i32, i32) nounwind readnone
598 declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64) nounwind readnone