1 ; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin | FileCheck %s
2 ; RUN: llc %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -print-machineinstrs=expand-isel-pseudos -o /dev/null 2> %t
3 ; RUN: FileCheck %s < %t --check-prefix=CHECK-SSA
6 ; CHECK-SSA-LABEL: Machine code for function t1
8 ; CHECK-SSA: [[QUOTREG:%vreg[0-9]+]]<def> = SDIVWr
9 ; CHECK-SSA-NOT: [[QUOTREG]]<def> =
10 ; CHECK-SSA: {{%vreg[0-9]+}}<def> = MSUBWrrr [[QUOTREG]]
12 ; CHECK-SSA-LABEL: Machine code for function t2
14 define i32 @t1(i32 %a, i32 %b) {
16 ; CHECK: sdiv [[TMP:w[0-9]+]], w0, w1
17 ; CHECK: msub w0, [[TMP]], w1, w0
22 define i64 @t2(i64 %a, i64 %b) {
24 ; CHECK: sdiv [[TMP:x[0-9]+]], x0, x1
25 ; CHECK: msub x0, [[TMP]], x1, x0
30 define i32 @t3(i32 %a, i32 %b) {
32 ; CHECK: udiv [[TMP:w[0-9]+]], w0, w1
33 ; CHECK: msub w0, [[TMP]], w1, w0
38 define i64 @t4(i64 %a, i64 %b) {
40 ; CHECK: udiv [[TMP:x[0-9]+]], x0, x1
41 ; CHECK: msub x0, [[TMP]], x1, x0