1 ; RUN: llc < %s -O0 -fast-isel-abort -mtriple=arm64-apple-darwin -mcpu=cyclone | FileCheck %s
3 ;; Test various conversions.
4 define zeroext i32 @trunc_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
7 ; CHECK: sub sp, sp, #16
8 ; CHECK: strb w0, [sp, #15]
9 ; CHECK: strh w1, [sp, #12]
10 ; CHECK: str w2, [sp, #8]
14 ; CHECK: str w0, [sp, #8]
15 ; CHECK: ldr w0, [sp, #8]
16 ; CHECK: strh w0, [sp, #12]
17 ; CHECK: ldrh w0, [sp, #12]
18 ; CHECK: strb w0, [sp, #15]
19 ; CHECK: ldrb w0, [sp, #15]
21 ; CHECK: add sp, sp, #16
23 %a.addr = alloca i8, align 1
24 %b.addr = alloca i16, align 2
25 %c.addr = alloca i32, align 4
26 %d.addr = alloca i64, align 8
27 store i8 %a, i8* %a.addr, align 1
28 store i16 %b, i16* %b.addr, align 2
29 store i32 %c, i32* %c.addr, align 4
30 store i64 %d, i64* %d.addr, align 8
31 %tmp = load i64* %d.addr, align 8
32 %conv = trunc i64 %tmp to i32
33 store i32 %conv, i32* %c.addr, align 4
34 %tmp1 = load i32* %c.addr, align 4
35 %conv2 = trunc i32 %tmp1 to i16
36 store i16 %conv2, i16* %b.addr, align 2
37 %tmp3 = load i16* %b.addr, align 2
38 %conv4 = trunc i16 %tmp3 to i8
39 store i8 %conv4, i8* %a.addr, align 1
40 %tmp5 = load i8* %a.addr, align 1
41 %conv6 = zext i8 %tmp5 to i32
45 define i64 @zext_(i8 zeroext %a, i16 zeroext %b, i32 %c, i64 %d) nounwind ssp {
48 ; CHECK: sub sp, sp, #16
49 ; CHECK: strb w0, [sp, #15]
50 ; CHECK: strh w1, [sp, #12]
51 ; CHECK: str w2, [sp, #8]
53 ; CHECK: ldrb w0, [sp, #15]
55 ; CHECK: strh w0, [sp, #12]
56 ; CHECK: ldrh w0, [sp, #12]
58 ; CHECK: str w0, [sp, #8]
59 ; CHECK: ldr w0, [sp, #8]
61 ; CHECK: ubfx x3, x3, #0, #32
65 %a.addr = alloca i8, align 1
66 %b.addr = alloca i16, align 2
67 %c.addr = alloca i32, align 4
68 %d.addr = alloca i64, align 8
69 store i8 %a, i8* %a.addr, align 1
70 store i16 %b, i16* %b.addr, align 2
71 store i32 %c, i32* %c.addr, align 4
72 store i64 %d, i64* %d.addr, align 8
73 %tmp = load i8* %a.addr, align 1
74 %conv = zext i8 %tmp to i16
75 store i16 %conv, i16* %b.addr, align 2
76 %tmp1 = load i16* %b.addr, align 2
77 %conv2 = zext i16 %tmp1 to i32
78 store i32 %conv2, i32* %c.addr, align 4
79 %tmp3 = load i32* %c.addr, align 4
80 %conv4 = zext i32 %tmp3 to i64
81 store i64 %conv4, i64* %d.addr, align 8
82 %tmp5 = load i64* %d.addr, align 8
86 define i32 @zext_i1_i32(i1 zeroext %a) nounwind ssp {
88 ; CHECK-LABEL: zext_i1_i32
89 ; CHECK-NOT: and w0, w0, #0x1
91 %conv = zext i1 %a to i32
95 define i64 @zext_i1_i64(i1 zeroext %a) nounwind ssp {
97 ; CHECK-LABEL: zext_i1_i64
98 ; CHECK-NOT: and w0, w0, #0x1
100 %conv = zext i1 %a to i64
104 define i64 @sext_(i8 signext %a, i16 signext %b, i32 %c, i64 %d) nounwind ssp {
107 ; CHECK: sub sp, sp, #16
108 ; CHECK: strb w0, [sp, #15]
109 ; CHECK: strh w1, [sp, #12]
110 ; CHECK: str w2, [sp, #8]
111 ; CHECK: str x3, [sp]
112 ; CHECK: ldrb w0, [sp, #15]
114 ; CHECK: strh w0, [sp, #12]
115 ; CHECK: ldrh w0, [sp, #12]
117 ; CHECK: str w0, [sp, #8]
118 ; CHECK: ldr w0, [sp, #8]
121 ; CHECK: str x3, [sp]
122 ; CHECK: ldr x0, [sp]
124 %a.addr = alloca i8, align 1
125 %b.addr = alloca i16, align 2
126 %c.addr = alloca i32, align 4
127 %d.addr = alloca i64, align 8
128 store i8 %a, i8* %a.addr, align 1
129 store i16 %b, i16* %b.addr, align 2
130 store i32 %c, i32* %c.addr, align 4
131 store i64 %d, i64* %d.addr, align 8
132 %tmp = load i8* %a.addr, align 1
133 %conv = sext i8 %tmp to i16
134 store i16 %conv, i16* %b.addr, align 2
135 %tmp1 = load i16* %b.addr, align 2
136 %conv2 = sext i16 %tmp1 to i32
137 store i32 %conv2, i32* %c.addr, align 4
138 %tmp3 = load i32* %c.addr, align 4
139 %conv4 = sext i32 %tmp3 to i64
140 store i64 %conv4, i64* %d.addr, align 8
141 %tmp5 = load i64* %d.addr, align 8
145 ; Test sext i8 to i64
147 define zeroext i64 @sext_i8_i64(i8 zeroext %in) {
148 ; CHECK-LABEL: sext_i8_i64:
149 ; CHECK: mov x[[TMP:[0-9]+]], x0
150 ; CHECK: sxtb x0, w[[TMP]]
151 %big = sext i8 %in to i64
155 define zeroext i64 @sext_i16_i64(i16 zeroext %in) {
156 ; CHECK-LABEL: sext_i16_i64:
157 ; CHECK: mov x[[TMP:[0-9]+]], x0
158 ; CHECK: sxth x0, w[[TMP]]
159 %big = sext i16 %in to i64
163 ; Test sext i1 to i32
164 define i32 @sext_i1_i32(i1 signext %a) nounwind ssp {
166 ; CHECK-LABEL: sext_i1_i32
167 ; CHECK-NOT: sbfx w0, w0, #0, #1
169 %conv = sext i1 %a to i32
173 ; Test sext i1 to i16
174 define signext i16 @sext_i1_i16(i1 %a) nounwind ssp {
176 ; CHECK-LABEL: sext_i1_i16
177 ; CHECK: sbfx w0, w0, #0, #1
178 %conv = sext i1 %a to i16
183 define signext i8 @sext_i1_i8(i1 %a) nounwind ssp {
185 ; CHECK-LABEL: sext_i1_i8
186 ; CHECK: sbfx w0, w0, #0, #1
187 %conv = sext i1 %a to i8
192 define double @fpext_(float %a) nounwind ssp {
194 ; CHECK-LABEL: fpext_
196 %conv = fpext float %a to double
201 define float @fptrunc_(double %a) nounwind ssp {
203 ; CHECK-LABEL: fptrunc_
205 %conv = fptrunc double %a to float
210 define i32 @fptosi_ws(float %a) nounwind ssp {
212 ; CHECK-LABEL: fptosi_ws
213 ; CHECK: fcvtzs w0, s0
214 %conv = fptosi float %a to i32
219 define i32 @fptosi_wd(double %a) nounwind ssp {
221 ; CHECK-LABEL: fptosi_wd
222 ; CHECK: fcvtzs w0, d0
223 %conv = fptosi double %a to i32
228 define i32 @fptoui_ws(float %a) nounwind ssp {
230 ; CHECK-LABEL: fptoui_ws
231 ; CHECK: fcvtzu w0, s0
232 %conv = fptoui float %a to i32
237 define i32 @fptoui_wd(double %a) nounwind ssp {
239 ; CHECK-LABEL: fptoui_wd
240 ; CHECK: fcvtzu w0, d0
241 %conv = fptoui double %a to i32
246 define float @sitofp_sw_i1(i1 %a) nounwind ssp {
248 ; CHECK-LABEL: sitofp_sw_i1
249 ; CHECK: sbfx w0, w0, #0, #1
250 ; CHECK: scvtf s0, w0
251 %conv = sitofp i1 %a to float
256 define float @sitofp_sw_i8(i8 %a) nounwind ssp {
258 ; CHECK-LABEL: sitofp_sw_i8
260 ; CHECK: scvtf s0, w0
261 %conv = sitofp i8 %a to float
266 define float @sitofp_sw_i16(i16 %a) nounwind ssp {
268 ; CHECK-LABEL: sitofp_sw_i16
269 %conv = sitofp i16 %a to float
274 define float @sitofp_sw(i32 %a) nounwind ssp {
276 ; CHECK-LABEL: sitofp_sw
277 ; CHECK: scvtf s0, w0
278 %conv = sitofp i32 %a to float
283 define float @sitofp_sx(i64 %a) nounwind ssp {
285 ; CHECK-LABEL: sitofp_sx
286 ; CHECK: scvtf s0, x0
287 %conv = sitofp i64 %a to float
292 define double @sitofp_dw(i32 %a) nounwind ssp {
294 ; CHECK-LABEL: sitofp_dw
295 ; CHECK: scvtf d0, w0
296 %conv = sitofp i32 %a to double
301 define double @sitofp_dx(i64 %a) nounwind ssp {
303 ; CHECK-LABEL: sitofp_dx
304 ; CHECK: scvtf d0, x0
305 %conv = sitofp i64 %a to double
310 define float @uitofp_sw_i1(i1 %a) nounwind ssp {
312 ; CHECK-LABEL: uitofp_sw_i1
313 ; CHECK: and w0, w0, #0x1
314 ; CHECK: ucvtf s0, w0
315 %conv = uitofp i1 %a to float
320 define float @uitofp_sw_i8(i8 %a) nounwind ssp {
322 ; CHECK-LABEL: uitofp_sw_i8
323 %conv = uitofp i8 %a to float
328 define float @uitofp_sw_i16(i16 %a) nounwind ssp {
330 ; CHECK-LABEL: uitofp_sw_i16
331 %conv = uitofp i16 %a to float
336 define float @uitofp_sw(i32 %a) nounwind ssp {
338 ; CHECK-LABEL: uitofp_sw
339 ; CHECK: ucvtf s0, w0
340 %conv = uitofp i32 %a to float
345 define float @uitofp_sx(i64 %a) nounwind ssp {
347 ; CHECK-LABEL: uitofp_sx
348 ; CHECK: ucvtf s0, x0
349 %conv = uitofp i64 %a to float
354 define double @uitofp_dw(i32 %a) nounwind ssp {
356 ; CHECK-LABEL: uitofp_dw
357 ; CHECK: ucvtf d0, w0
358 %conv = uitofp i32 %a to double
363 define double @uitofp_dx(i64 %a) nounwind ssp {
365 ; CHECK-LABEL: uitofp_dx
366 ; CHECK: ucvtf d0, x0
367 %conv = uitofp i64 %a to double
371 define i32 @i64_trunc_i32(i64 %a) nounwind ssp {
373 ; CHECK-LABEL: i64_trunc_i32
375 %conv = trunc i64 %a to i32
379 define zeroext i16 @i64_trunc_i16(i64 %a) nounwind ssp {
381 ; CHECK-LABEL: i64_trunc_i16
382 ; CHECK: mov x[[REG:[0-9]+]], x0
383 ; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xffff
384 ; CHECK: uxth w0, [[REG2]]
385 %conv = trunc i64 %a to i16
389 define zeroext i8 @i64_trunc_i8(i64 %a) nounwind ssp {
391 ; CHECK-LABEL: i64_trunc_i8
392 ; CHECK: mov x[[REG:[0-9]+]], x0
393 ; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0xff
394 ; CHECK: uxtb w0, [[REG2]]
395 %conv = trunc i64 %a to i8
399 define zeroext i1 @i64_trunc_i1(i64 %a) nounwind ssp {
401 ; CHECK-LABEL: i64_trunc_i1
402 ; CHECK: mov x[[REG:[0-9]+]], x0
403 ; CHECK: and [[REG2:w[0-9]+]], w[[REG]], #0x1
404 ; CHECK: and w0, [[REG2]], #0x1
405 %conv = trunc i64 %a to i1
410 define void @stack_trunc() nounwind {
411 ; CHECK-LABEL: stack_trunc
412 ; CHECK: sub sp, sp, #16
413 ; CHECK: ldr [[REG:x[0-9]+]], [sp]
414 ; CHECK: mov x[[REG2:[0-9]+]], [[REG]]
415 ; CHECK: and [[REG3:w[0-9]+]], w[[REG2]], #0xff
416 ; CHECK: strb [[REG3]], [sp, #15]
417 ; CHECK: add sp, sp, #16
418 %a = alloca i8, align 1
419 %b = alloca i64, align 8
420 %c = load i64* %b, align 8
421 %d = trunc i64 %c to i8
422 store i8 %d, i8* %a, align 1
426 define zeroext i64 @zext_i8_i64(i8 zeroext %in) {
427 ; CHECK-LABEL: zext_i8_i64:
428 ; CHECK-NOT: ubfx x0, {{x[0-9]+}}, #0, #8
430 %big = zext i8 %in to i64
433 define zeroext i64 @zext_i16_i64(i16 zeroext %in) {
434 ; CHECK-LABEL: zext_i16_i64:
435 ; CHECK-NOT: ubfx x0, {{x[0-9]+}}, #0, #16
437 %big = zext i16 %in to i64
441 define float @bitcast_i32_to_float(i32 %a) {
442 %1 = bitcast i32 %a to float
446 define double @bitcast_i64_to_double(i64 %a) {
447 %1 = bitcast i64 %a to double
451 define i32 @bitcast_float_to_i32(float %a) {
452 %1 = bitcast float %a to i32
456 define i64 @bitcast_double_to_i64(double %a) {
457 %1 = bitcast double %a to i64