1 ; RUN: llc < %s -mcpu=cyclone -verify-machineinstrs -aarch64-ccmp -aarch64-stress-ccmp | FileCheck %s
2 target triple = "arm64-apple-ios"
6 ; CHECK-NEXT: ccmp w1, #17, #4, ne
11 define i32 @single_same(i32 %a, i32 %b) nounwind ssp {
13 %cmp = icmp eq i32 %a, 5
14 %cmp1 = icmp eq i32 %b, 17
15 %or.cond = or i1 %cmp, %cmp1
16 br i1 %or.cond, label %if.then, label %if.end
19 %call = tail call i32 @foo() nounwind
26 ; Different condition codes for the two compares.
27 ; CHECK: single_different
29 ; CHECK-NEXT: ccmp w1, #17, #0, ge
34 define i32 @single_different(i32 %a, i32 %b) nounwind ssp {
36 %cmp = icmp sle i32 %a, 5
37 %cmp1 = icmp ne i32 %b, 17
38 %or.cond = or i1 %cmp, %cmp1
39 br i1 %or.cond, label %if.then, label %if.end
42 %call = tail call i32 @foo() nounwind
49 ; Second block clobbers the flags, can't convert (easily).
50 ; CHECK: single_flagclobber
55 define i32 @single_flagclobber(i32 %a, i32 %b) nounwind ssp {
57 %cmp = icmp eq i32 %a, 5
58 br i1 %cmp, label %if.then, label %lor.lhs.false
60 lor.lhs.false: ; preds = %entry
61 %cmp1 = icmp slt i32 %b, 7
62 %mul = shl nsw i32 %b, 1
63 %add = add nsw i32 %b, 1
64 %cond = select i1 %cmp1, i32 %mul, i32 %add
65 %cmp2 = icmp slt i32 %cond, 17
66 br i1 %cmp2, label %if.then, label %if.end
68 if.then: ; preds = %lor.lhs.false, %entry
69 %call = tail call i32 @foo() nounwind
72 if.end: ; preds = %if.then, %lor.lhs.false
76 ; Second block clobbers the flags and ends with a tbz terminator.
77 ; CHECK: single_flagclobber_tbz
82 define i32 @single_flagclobber_tbz(i32 %a, i32 %b) nounwind ssp {
84 %cmp = icmp eq i32 %a, 5
85 br i1 %cmp, label %if.then, label %lor.lhs.false
87 lor.lhs.false: ; preds = %entry
88 %cmp1 = icmp slt i32 %b, 7
89 %mul = shl nsw i32 %b, 1
90 %add = add nsw i32 %b, 1
91 %cond = select i1 %cmp1, i32 %mul, i32 %add
92 %and = and i32 %cond, 8
93 %cmp2 = icmp ne i32 %and, 0
94 br i1 %cmp2, label %if.then, label %if.end
96 if.then: ; preds = %lor.lhs.false, %entry
97 %call = tail call i32 @foo() nounwind
100 if.end: ; preds = %if.then, %lor.lhs.false
104 ; Speculatively execute division by zero.
105 ; The sdiv/udiv instructions do not trap when the divisor is zero, so they are
107 ; CHECK-LABEL: speculate_division:
109 ; CHECK: sdiv [[DIVRES:w[0-9]+]], w1, w0
110 ; CHECK: ccmp [[DIVRES]], #16, #0, ge
111 ; CHECK: b.gt [[BLOCK:LBB[0-9_]+]]
114 ; CHECK: orr w0, wzr, #0x7
115 define i32 @speculate_division(i32 %a, i32 %b) nounwind ssp {
117 %cmp = icmp sgt i32 %a, 0
118 br i1 %cmp, label %land.lhs.true, label %if.end
121 %div = sdiv i32 %b, %a
122 %cmp1 = icmp slt i32 %div, 17
123 br i1 %cmp1, label %if.then, label %if.end
126 %call = tail call i32 @foo() nounwind
133 ; Floating point compare.
137 ; CHECK: fccmp {{.*}}, #8, ge
139 define i32 @single_fcmp(i32 %a, float %b) nounwind ssp {
141 %cmp = icmp sgt i32 %a, 0
142 br i1 %cmp, label %land.lhs.true, label %if.end
145 %conv = sitofp i32 %a to float
146 %div = fdiv float %b, %conv
147 %cmp1 = fcmp oge float %div, 1.700000e+01
148 br i1 %cmp1, label %if.then, label %if.end
151 %call = tail call i32 @foo() nounwind
158 ; Chain multiple compares.
159 ; CHECK: multi_different
164 define void @multi_different(i32 %a, i32 %b, i32 %c) nounwind ssp {
166 %cmp = icmp sgt i32 %a, %b
167 br i1 %cmp, label %land.lhs.true, label %if.end
170 %div = sdiv i32 %b, %a
171 %cmp1 = icmp eq i32 %div, 5
172 %cmp4 = icmp sgt i32 %div, %c
173 %or.cond = and i1 %cmp1, %cmp4
174 br i1 %or.cond, label %if.then, label %if.end
177 %call = tail call i32 @foo() nounwind
184 ; Convert a cbz in the head block.
188 define i32 @cbz_head(i32 %a, i32 %b) nounwind ssp {
190 %cmp = icmp eq i32 %a, 0
191 %cmp1 = icmp ne i32 %b, 17
192 %or.cond = or i1 %cmp, %cmp1
193 br i1 %or.cond, label %if.then, label %if.end
196 %call = tail call i32 @foo() nounwind
203 ; Check that the immediate operand is in range. The ccmp instruction encodes a
204 ; smaller range of immediates than subs/adds.
205 ; The ccmp immediates must be in the range 0-31.
206 ; CHECK: immediate_range
208 define i32 @immediate_range(i32 %a, i32 %b) nounwind ssp {
210 %cmp = icmp eq i32 %a, 5
211 %cmp1 = icmp eq i32 %b, 32
212 %or.cond = or i1 %cmp, %cmp1
213 br i1 %or.cond, label %if.then, label %if.end
216 %call = tail call i32 @foo() nounwind
223 ; Convert a cbz in the second block.
226 ; CHECK: ccmp w1, #0, #0, ne
228 define i32 @cbz_second(i32 %a, i32 %b) nounwind ssp {
230 %cmp = icmp eq i32 %a, 0
231 %cmp1 = icmp ne i32 %b, 0
232 %or.cond = or i1 %cmp, %cmp1
233 br i1 %or.cond, label %if.then, label %if.end
236 %call = tail call i32 @foo() nounwind
243 ; Convert a cbnz in the second block.
246 ; CHECK: ccmp w1, #0, #4, ne
248 define i32 @cbnz_second(i32 %a, i32 %b) nounwind ssp {
250 %cmp = icmp eq i32 %a, 0
251 %cmp1 = icmp eq i32 %b, 0
252 %or.cond = or i1 %cmp, %cmp1
253 br i1 %or.cond, label %if.then, label %if.end
256 %call = tail call i32 @foo() nounwind
264 %str1 = type { %str2 }
265 %str2 = type { [24 x i8], i8*, i32, %str1*, i32, [4 x i8], %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, %str1*, i8*, i8, i8*, %str1*, i8* }
267 ; Test case distilled from 126.gcc.
268 ; The phi in sw.bb.i.i gets multiple operands for the %entry predecessor.
269 ; CHECK: build_modify_expr
270 define void @build_modify_expr() nounwind ssp {
272 switch i32 undef, label %sw.bb.i.i [
273 i32 69, label %if.end85
274 i32 70, label %if.end85
275 i32 71, label %if.end85
276 i32 72, label %if.end85
277 i32 73, label %if.end85
278 i32 105, label %if.end85
279 i32 106, label %if.end85
286 %ref.tr.i.i = phi %str1* [ %0, %sw.bb.i.i ], [ undef, %entry ]
287 %operands.i.i = getelementptr inbounds %str1, %str1* %ref.tr.i.i, i64 0, i32 0, i32 2
288 %arrayidx.i.i = bitcast i32* %operands.i.i to %str1**
289 %0 = load %str1*, %str1** %arrayidx.i.i, align 8
290 %code1.i.i.phi.trans.insert = getelementptr inbounds %str1, %str1* %0, i64 0, i32 0, i32 0, i64 16
294 ; CHECK-LABEL: select_and
295 define i64 @select_and(i32 %w0, i32 %w1, i64 %x2, i64 %x3) {
297 ; CHECK-NEXT: ccmp w0, w1, #0, ne
298 ; CHECK-NEXT: csel x0, x2, x3, lt
300 %1 = icmp slt i32 %w0, %w1
301 %2 = icmp ne i32 5, %w1
303 %sel = select i1 %3, i64 %x2, i64 %x3
307 ; CHECK-LABEL: select_or
308 define i64 @select_or(i32 %w0, i32 %w1, i64 %x2, i64 %x3) {
310 ; CHECK-NEXT: ccmp w0, w1, #8, eq
311 ; CHECK-NEXT: csel x0, x2, x3, lt
313 %1 = icmp slt i32 %w0, %w1
314 %2 = icmp ne i32 5, %w1
316 %sel = select i1 %3, i64 %x2, i64 %x3
320 ; CHECK-LABEL: select_complicated
321 define i16 @select_complicated(double %v1, double %v2, i16 %a, i16 %b) {
322 ; CHECK: ldr [[REG:d[0-9]+]],
324 ; CHECK-NEXT: fmov d2, #13.00000000
325 ; CHECK-NEXT: fccmp d1, d2, #4, ne
326 ; CHECK-NEXT: fccmp d0, d1, #1, ne
327 ; CHECK-NEXT: fccmp d0, d1, #4, vc
328 ; CEHCK-NEXT: csel w0, w0, w1, eq
329 %1 = fcmp one double %v1, %v2
330 %2 = fcmp oeq double %v2, 13.0
331 %3 = fcmp oeq double %v1, 42.0
333 %or1 = or i1 %1, %or0
334 %sel = select i1 %or1, i16 %a, i16 %b
338 ; CHECK-LABEL: gccbug
339 define i64 @gccbug(i64 %x0, i64 %x1) {
341 ; CHECK-NEXT: ccmp x0, #4, #4, ne
342 ; CHECK-NEXT: ccmp x1, #0, #0, eq
343 ; CHECK-NEXT: orr w[[REGNUM:[0-9]+]], wzr, #0x1
344 ; CHECK-NEXT: cinc x0, x[[REGNUM]], eq
346 %cmp0 = icmp eq i64 %x1, 0
347 %cmp1 = icmp eq i64 %x0, 2
348 %cmp2 = icmp eq i64 %x0, 4
350 %or = or i1 %cmp2, %cmp1
351 %and = and i1 %or, %cmp0
353 %sel = select i1 %and, i64 2, i64 1
357 ; CHECK-LABEL: select_ororand
358 define i32 @select_ororand(i32 %w0, i32 %w1, i32 %w2, i32 %w3) {
360 ; CHECK-NEXT: ccmp w2, #2, #0, gt
361 ; CHECK-NEXT: ccmp w1, #13, #2, ge
362 ; CHECK-NEXT: ccmp w0, #0, #4, ls
363 ; CHECK-NEXT: csel w0, w3, wzr, eq
365 %c0 = icmp eq i32 %w0, 0
366 %c1 = icmp ugt i32 %w1, 13
367 %c2 = icmp slt i32 %w2, 2
368 %c4 = icmp sgt i32 %w3, 4
370 %and = and i1 %c2, %c4
371 %or1 = or i1 %or, %and
372 %sel = select i1 %or1, i32 %w3, i32 0
376 ; CHECK-LABEL: select_andor
377 define i32 @select_andor(i32 %v1, i32 %v2, i32 %v3) {
379 ; CHECK-NEXT: ccmp w0, #0, #4, lt
380 ; CHECK-NEXT: ccmp w0, w1, #0, eq
381 ; CHECK-NEXT: csel w0, w0, w1, eq
383 %c0 = icmp eq i32 %v1, %v2
384 %c1 = icmp sge i32 %v2, %v3
385 %c2 = icmp eq i32 %v1, 0
387 %and = and i1 %or, %c0
388 %sel = select i1 %and, i32 %v1, i32 %v2
392 ; CHECK-LABEL: select_noccmp1
393 define i64 @select_noccmp1(i64 %v1, i64 %v2, i64 %v3, i64 %r) {
395 ; CHECK-NEXT: cset [[REG0:w[0-9]+]], lt
396 ; CHECK-NEXT: cmp x0, #13
398 ; CHECK-NEXT: cset [[REG1:w[0-9]+]], gt
399 ; CHECK-NEXT: cmp x2, #2
400 ; CHECK-NEXT: cset [[REG2:w[0-9]+]], lt
401 ; CHECK-NEXT: cmp x2, #4
402 ; CHECK-NEXT: cset [[REG3:w[0-9]+]], gt
403 ; CHECK-NEXT: and [[REG4:w[0-9]+]], [[REG0]], [[REG1]]
404 ; CHECK-NEXT: and [[REG5:w[0-9]+]], [[REG2]], [[REG3]]
405 ; CHECK-NEXT: orr [[REG6:w[0-9]+]], [[REG4]], [[REG5]]
406 ; CHECK-NEXT: cmp [[REG6]], #0
407 ; CHECK-NEXT: csel x0, xzr, x3, ne
409 %c0 = icmp slt i64 %v1, 0
410 %c1 = icmp sgt i64 %v1, 13
411 %c2 = icmp slt i64 %v3, 2
412 %c4 = icmp sgt i64 %v3, 4
413 %and0 = and i1 %c0, %c1
414 %and1 = and i1 %c2, %c4
415 %or = or i1 %and0, %and1
416 %sel = select i1 %or, i64 0, i64 %r
422 ; Should not use ccmp if we have to compute the or expression in an integer
423 ; register anyway because of other users.
424 ; CHECK-LABEL: select_noccmp2
425 define i64 @select_noccmp2(i64 %v1, i64 %v2, i64 %v3, i64 %r) {
427 ; CHECK-NEXT: cset [[REG0:w[0-9]+]], lt
429 ; CHECK-NEXT: cmp x0, #13
430 ; CHECK-NEXT: cset [[REG1:w[0-9]+]], gt
431 ; CHECK-NEXT: orr [[REG2:w[0-9]+]], [[REG0]], [[REG1]]
432 ; CHECK-NEXT: cmp [[REG2]], #0
433 ; CHECK-NEXT: csel x0, xzr, x3, ne
434 ; CHECK-NEXT: sbfx [[REG3:w[0-9]+]], [[REG2]], #0, #1
435 ; CHECK-NEXT: adrp x[[REGN4:[0-9]+]], _g@PAGE
436 ; CHECK-NEXT: str [[REG3]], [x[[REGN4]], _g@PAGEOFF]
438 %c0 = icmp slt i64 %v1, 0
439 %c1 = icmp sgt i64 %v1, 13
441 %sel = select i1 %or, i64 0, i64 %r
442 %ext = sext i1 %or to i32
443 store volatile i32 %ext, i32* @g