1 ; RUN: llc < %s -march=arm64 -asm-verbose=false -verify-machineinstrs -mcpu=cyclone | FileCheck %s
3 define i32 @val_compare_and_swap(i32* %p, i32 %cmp, i32 %new) #0 {
4 ; CHECK-LABEL: val_compare_and_swap:
5 ; CHECK-NEXT: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
6 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x0]
7 ; CHECK-NEXT: cmp [[RESULT]], w1
8 ; CHECK-NEXT: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
9 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], w2, [x0]
10 ; CHECK-NEXT: cbnz [[SCRATCH_REG]], [[LABEL]]
11 ; CHECK-NEXT: [[LABEL2]]:
12 %pair = cmpxchg i32* %p, i32 %cmp, i32 %new acquire acquire
13 %val = extractvalue { i32, i1 } %pair, 0
17 define i32 @val_compare_and_swap_rel(i32* %p, i32 %cmp, i32 %new) #0 {
18 ; CHECK-LABEL: val_compare_and_swap_rel:
19 ; CHECK-NEXT: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
20 ; CHECK-NEXT: ldaxr [[RESULT:w[0-9]+]], [x0]
21 ; CHECK-NEXT: cmp [[RESULT]], w1
22 ; CHECK-NEXT: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
23 ; CHECK-NEXT: stlxr [[SCRATCH_REG:w[0-9]+]], w2, [x0]
24 ; CHECK-NEXT: cbnz [[SCRATCH_REG]], [[LABEL]]
25 ; CHECK-NEXT: [[LABEL2]]:
26 %pair = cmpxchg i32* %p, i32 %cmp, i32 %new acq_rel monotonic
27 %val = extractvalue { i32, i1 } %pair, 0
31 define i64 @val_compare_and_swap_64(i64* %p, i64 %cmp, i64 %new) #0 {
32 ; CHECK-LABEL: val_compare_and_swap_64:
33 ; CHECK-NEXT: mov x[[ADDR:[0-9]+]], x0
34 ; CHECK-NEXT: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
35 ; CHECK-NEXT: ldxr [[RESULT:x[0-9]+]], [x[[ADDR]]]
36 ; CHECK-NEXT: cmp [[RESULT]], x1
37 ; CHECK-NEXT: b.ne [[LABEL2:.?LBB[0-9]+_[0-9]+]]
38 ; CHECK-NEXT: stxr [[SCRATCH_REG:w[0-9]+]], x2, [x[[ADDR]]]
39 ; CHECK-NEXT: cbnz [[SCRATCH_REG]], [[LABEL]]
40 ; CHECK-NEXT: [[LABEL2]]:
41 %pair = cmpxchg i64* %p, i64 %cmp, i64 %new monotonic monotonic
42 %val = extractvalue { i64, i1 } %pair, 0
46 define i32 @fetch_and_nand(i32* %p) #0 {
47 ; CHECK-LABEL: fetch_and_nand:
48 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
49 ; CHECK: ldxr w[[DEST_REG:[0-9]+]], [x0]
50 ; CHECK: mvn [[TMP_REG:w[0-9]+]], w[[DEST_REG]]
51 ; CHECK: orr [[SCRATCH2_REG:w[0-9]+]], [[TMP_REG]], #0xfffffff8
52 ; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
53 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
54 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
55 ; CHECK: mov x0, x[[DEST_REG]]
56 %val = atomicrmw nand i32* %p, i32 7 release
60 define i64 @fetch_and_nand_64(i64* %p) #0 {
61 ; CHECK-LABEL: fetch_and_nand_64:
62 ; CHECK: mov x[[ADDR:[0-9]+]], x0
63 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
64 ; CHECK: ldaxr x[[DEST_REG:[0-9]+]], [x[[ADDR]]]
65 ; CHECK: mvn w[[TMP_REG:[0-9]+]], w[[DEST_REG]]
66 ; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], x[[TMP_REG]], #0xfffffffffffffff8
67 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
68 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
70 %val = atomicrmw nand i64* %p, i64 7 acq_rel
74 define i32 @fetch_and_or(i32* %p) #0 {
75 ; CHECK-LABEL: fetch_and_or:
76 ; CHECK: movz [[OLDVAL_REG:w[0-9]+]], #0x5
77 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
78 ; CHECK: ldaxr w[[DEST_REG:[0-9]+]], [x0]
79 ; CHECK: orr [[SCRATCH2_REG:w[0-9]+]], w[[DEST_REG]], [[OLDVAL_REG]]
80 ; CHECK-NOT: stlxr [[SCRATCH2_REG]], [[SCRATCH2_REG]]
81 ; CHECK: stlxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x0]
82 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
83 ; CHECK: mov x0, x[[DEST_REG]]
84 %val = atomicrmw or i32* %p, i32 5 seq_cst
88 define i64 @fetch_and_or_64(i64* %p) #0 {
89 ; CHECK: fetch_and_or_64:
90 ; CHECK: mov x[[ADDR:[0-9]+]], x0
91 ; CHECK: [[LABEL:.?LBB[0-9]+_[0-9]+]]:
92 ; CHECK: ldxr [[DEST_REG:x[0-9]+]], [x[[ADDR]]]
93 ; CHECK: orr [[SCRATCH2_REG:x[0-9]+]], [[DEST_REG]], #0x7
94 ; CHECK: stxr [[SCRATCH_REG:w[0-9]+]], [[SCRATCH2_REG]], [x[[ADDR]]]
95 ; CHECK: cbnz [[SCRATCH_REG]], [[LABEL]]
96 %val = atomicrmw or i64* %p, i64 7 monotonic
100 define void @acquire_fence() #0 {
103 ; CHECK-LABEL: acquire_fence:
107 define void @release_fence() #0 {
110 ; CHECK-LABEL: release_fence:
111 ; CHECK: dmb ish{{$}}
114 define void @seq_cst_fence() #0 {
117 ; CHECK-LABEL: seq_cst_fence:
118 ; CHECK: dmb ish{{$}}
121 define i32 @atomic_load(i32* %p) #0 {
122 %r = load atomic i32, i32* %p seq_cst, align 4
124 ; CHECK-LABEL: atomic_load:
128 define i8 @atomic_load_relaxed_8(i8* %p, i32 %off32) #0 {
129 ; CHECK-LABEL: atomic_load_relaxed_8:
130 %ptr_unsigned = getelementptr i8, i8* %p, i32 4095
131 %val_unsigned = load atomic i8, i8* %ptr_unsigned monotonic, align 1
132 ; CHECK: ldrb {{w[0-9]+}}, [x0, #4095]
134 %ptr_regoff = getelementptr i8, i8* %p, i32 %off32
135 %val_regoff = load atomic i8, i8* %ptr_regoff unordered, align 1
136 %tot1 = add i8 %val_unsigned, %val_regoff
137 ; CHECK: ldrb {{w[0-9]+}}, [x0, w1, sxtw]
139 %ptr_unscaled = getelementptr i8, i8* %p, i32 -256
140 %val_unscaled = load atomic i8, i8* %ptr_unscaled monotonic, align 1
141 %tot2 = add i8 %tot1, %val_unscaled
142 ; CHECK: ldurb {{w[0-9]+}}, [x0, #-256]
144 %ptr_random = getelementptr i8, i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
145 %val_random = load atomic i8, i8* %ptr_random unordered, align 1
146 %tot3 = add i8 %tot2, %val_random
147 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
148 ; CHECK: ldrb {{w[0-9]+}}, [x[[ADDR]]]
153 define i16 @atomic_load_relaxed_16(i16* %p, i32 %off32) #0 {
154 ; CHECK-LABEL: atomic_load_relaxed_16:
155 %ptr_unsigned = getelementptr i16, i16* %p, i32 4095
156 %val_unsigned = load atomic i16, i16* %ptr_unsigned monotonic, align 2
157 ; CHECK: ldrh {{w[0-9]+}}, [x0, #8190]
159 %ptr_regoff = getelementptr i16, i16* %p, i32 %off32
160 %val_regoff = load atomic i16, i16* %ptr_regoff unordered, align 2
161 %tot1 = add i16 %val_unsigned, %val_regoff
162 ; CHECK: ldrh {{w[0-9]+}}, [x0, w1, sxtw #1]
164 %ptr_unscaled = getelementptr i16, i16* %p, i32 -128
165 %val_unscaled = load atomic i16, i16* %ptr_unscaled monotonic, align 2
166 %tot2 = add i16 %tot1, %val_unscaled
167 ; CHECK: ldurh {{w[0-9]+}}, [x0, #-256]
169 %ptr_random = getelementptr i16, i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
170 %val_random = load atomic i16, i16* %ptr_random unordered, align 2
171 %tot3 = add i16 %tot2, %val_random
172 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
173 ; CHECK: ldrh {{w[0-9]+}}, [x[[ADDR]]]
178 define i32 @atomic_load_relaxed_32(i32* %p, i32 %off32) #0 {
179 ; CHECK-LABEL: atomic_load_relaxed_32:
180 %ptr_unsigned = getelementptr i32, i32* %p, i32 4095
181 %val_unsigned = load atomic i32, i32* %ptr_unsigned monotonic, align 4
182 ; CHECK: ldr {{w[0-9]+}}, [x0, #16380]
184 %ptr_regoff = getelementptr i32, i32* %p, i32 %off32
185 %val_regoff = load atomic i32, i32* %ptr_regoff unordered, align 4
186 %tot1 = add i32 %val_unsigned, %val_regoff
187 ; CHECK: ldr {{w[0-9]+}}, [x0, w1, sxtw #2]
189 %ptr_unscaled = getelementptr i32, i32* %p, i32 -64
190 %val_unscaled = load atomic i32, i32* %ptr_unscaled monotonic, align 4
191 %tot2 = add i32 %tot1, %val_unscaled
192 ; CHECK: ldur {{w[0-9]+}}, [x0, #-256]
194 %ptr_random = getelementptr i32, i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
195 %val_random = load atomic i32, i32* %ptr_random unordered, align 4
196 %tot3 = add i32 %tot2, %val_random
197 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
198 ; CHECK: ldr {{w[0-9]+}}, [x[[ADDR]]]
203 define i64 @atomic_load_relaxed_64(i64* %p, i32 %off32) #0 {
204 ; CHECK-LABEL: atomic_load_relaxed_64:
205 %ptr_unsigned = getelementptr i64, i64* %p, i32 4095
206 %val_unsigned = load atomic i64, i64* %ptr_unsigned monotonic, align 8
207 ; CHECK: ldr {{x[0-9]+}}, [x0, #32760]
209 %ptr_regoff = getelementptr i64, i64* %p, i32 %off32
210 %val_regoff = load atomic i64, i64* %ptr_regoff unordered, align 8
211 %tot1 = add i64 %val_unsigned, %val_regoff
212 ; CHECK: ldr {{x[0-9]+}}, [x0, w1, sxtw #3]
214 %ptr_unscaled = getelementptr i64, i64* %p, i32 -32
215 %val_unscaled = load atomic i64, i64* %ptr_unscaled monotonic, align 8
216 %tot2 = add i64 %tot1, %val_unscaled
217 ; CHECK: ldur {{x[0-9]+}}, [x0, #-256]
219 %ptr_random = getelementptr i64, i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
220 %val_random = load atomic i64, i64* %ptr_random unordered, align 8
221 %tot3 = add i64 %tot2, %val_random
222 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
223 ; CHECK: ldr {{x[0-9]+}}, [x[[ADDR]]]
229 define void @atomc_store(i32* %p) #0 {
230 store atomic i32 4, i32* %p seq_cst, align 4
232 ; CHECK-LABEL: atomc_store:
236 define void @atomic_store_relaxed_8(i8* %p, i32 %off32, i8 %val) #0 {
237 ; CHECK-LABEL: atomic_store_relaxed_8:
238 %ptr_unsigned = getelementptr i8, i8* %p, i32 4095
239 store atomic i8 %val, i8* %ptr_unsigned monotonic, align 1
240 ; CHECK: strb {{w[0-9]+}}, [x0, #4095]
242 %ptr_regoff = getelementptr i8, i8* %p, i32 %off32
243 store atomic i8 %val, i8* %ptr_regoff unordered, align 1
244 ; CHECK: strb {{w[0-9]+}}, [x0, w1, sxtw]
246 %ptr_unscaled = getelementptr i8, i8* %p, i32 -256
247 store atomic i8 %val, i8* %ptr_unscaled monotonic, align 1
248 ; CHECK: sturb {{w[0-9]+}}, [x0, #-256]
250 %ptr_random = getelementptr i8, i8* %p, i32 1191936 ; 0x123000 (i.e. ADD imm)
251 store atomic i8 %val, i8* %ptr_random unordered, align 1
252 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
253 ; CHECK: strb {{w[0-9]+}}, [x[[ADDR]]]
258 define void @atomic_store_relaxed_16(i16* %p, i32 %off32, i16 %val) #0 {
259 ; CHECK-LABEL: atomic_store_relaxed_16:
260 %ptr_unsigned = getelementptr i16, i16* %p, i32 4095
261 store atomic i16 %val, i16* %ptr_unsigned monotonic, align 2
262 ; CHECK: strh {{w[0-9]+}}, [x0, #8190]
264 %ptr_regoff = getelementptr i16, i16* %p, i32 %off32
265 store atomic i16 %val, i16* %ptr_regoff unordered, align 2
266 ; CHECK: strh {{w[0-9]+}}, [x0, w1, sxtw #1]
268 %ptr_unscaled = getelementptr i16, i16* %p, i32 -128
269 store atomic i16 %val, i16* %ptr_unscaled monotonic, align 2
270 ; CHECK: sturh {{w[0-9]+}}, [x0, #-256]
272 %ptr_random = getelementptr i16, i16* %p, i32 595968 ; 0x123000/2 (i.e. ADD imm)
273 store atomic i16 %val, i16* %ptr_random unordered, align 2
274 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
275 ; CHECK: strh {{w[0-9]+}}, [x[[ADDR]]]
280 define void @atomic_store_relaxed_32(i32* %p, i32 %off32, i32 %val) #0 {
281 ; CHECK-LABEL: atomic_store_relaxed_32:
282 %ptr_unsigned = getelementptr i32, i32* %p, i32 4095
283 store atomic i32 %val, i32* %ptr_unsigned monotonic, align 4
284 ; CHECK: str {{w[0-9]+}}, [x0, #16380]
286 %ptr_regoff = getelementptr i32, i32* %p, i32 %off32
287 store atomic i32 %val, i32* %ptr_regoff unordered, align 4
288 ; CHECK: str {{w[0-9]+}}, [x0, w1, sxtw #2]
290 %ptr_unscaled = getelementptr i32, i32* %p, i32 -64
291 store atomic i32 %val, i32* %ptr_unscaled monotonic, align 4
292 ; CHECK: stur {{w[0-9]+}}, [x0, #-256]
294 %ptr_random = getelementptr i32, i32* %p, i32 297984 ; 0x123000/4 (i.e. ADD imm)
295 store atomic i32 %val, i32* %ptr_random unordered, align 4
296 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
297 ; CHECK: str {{w[0-9]+}}, [x[[ADDR]]]
302 define void @atomic_store_relaxed_64(i64* %p, i32 %off32, i64 %val) #0 {
303 ; CHECK-LABEL: atomic_store_relaxed_64:
304 %ptr_unsigned = getelementptr i64, i64* %p, i32 4095
305 store atomic i64 %val, i64* %ptr_unsigned monotonic, align 8
306 ; CHECK: str {{x[0-9]+}}, [x0, #32760]
308 %ptr_regoff = getelementptr i64, i64* %p, i32 %off32
309 store atomic i64 %val, i64* %ptr_regoff unordered, align 8
310 ; CHECK: str {{x[0-9]+}}, [x0, w1, sxtw #3]
312 %ptr_unscaled = getelementptr i64, i64* %p, i32 -32
313 store atomic i64 %val, i64* %ptr_unscaled monotonic, align 8
314 ; CHECK: stur {{x[0-9]+}}, [x0, #-256]
316 %ptr_random = getelementptr i64, i64* %p, i32 148992 ; 0x123000/8 (i.e. ADD imm)
317 store atomic i64 %val, i64* %ptr_random unordered, align 8
318 ; CHECK: add x[[ADDR:[0-9]+]], x0, #291, lsl #12
319 ; CHECK: str {{x[0-9]+}}, [x[[ADDR]]]
327 %"class.X::Atomic" = type { %struct.x_atomic_t }
328 %struct.x_atomic_t = type { i32 }
330 @counter = external hidden global %"class.X::Atomic", align 4
332 define i32 @next_id() nounwind optsize ssp align 2 {
334 %0 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic", %"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst
335 %add.i = add i32 %0, 1
336 %tobool = icmp eq i32 %add.i, 0
337 br i1 %tobool, label %if.else, label %return
339 if.else: ; preds = %entry
340 %1 = atomicrmw add i32* getelementptr inbounds (%"class.X::Atomic", %"class.X::Atomic"* @counter, i64 0, i32 0, i32 0), i32 1 seq_cst
341 %add.i2 = add i32 %1, 1
344 return: ; preds = %if.else, %entry
345 %retval.0 = phi i32 [ %add.i2, %if.else ], [ %add.i, %entry ]
349 attributes #0 = { nounwind }