1 ; RUN: llc -mtriple=aarch64_be--linux-gnu < %s | FileCheck %s
3 @vec_v8i16 = global <8 x i16> <i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7, i16 8>
5 ; CHECK-LABEL: movi_modimm_t1:
6 define i16 @movi_modimm_t1() nounwind {
7 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
8 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1
9 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
10 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
11 %in = load <8 x i16>* @vec_v8i16
12 %rv = add <8 x i16> %in, <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0>
13 %el = extractelement <8 x i16> %rv, i32 0
17 ; CHECK-LABEL: movi_modimm_t2:
18 define i16 @movi_modimm_t2() nounwind {
19 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
20 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1, lsl #8
21 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
22 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
23 %in = load <8 x i16>* @vec_v8i16
24 %rv = add <8 x i16> %in, <i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0>
25 %el = extractelement <8 x i16> %rv, i32 0
29 ; CHECK-LABEL: movi_modimm_t3:
30 define i16 @movi_modimm_t3() nounwind {
31 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
32 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1, lsl #16
33 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
34 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
35 %in = load <8 x i16>* @vec_v8i16
36 %rv = add <8 x i16> %in, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
37 %el = extractelement <8 x i16> %rv, i32 0
41 ; CHECK-LABEL: movi_modimm_t4:
42 define i16 @movi_modimm_t4() nounwind {
43 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
44 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1, lsl #24
45 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
46 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
47 %in = load <8 x i16>* @vec_v8i16
48 %rv = add <8 x i16> %in, <i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256>
49 %el = extractelement <8 x i16> %rv, i32 0
53 ; CHECK-LABEL: movi_modimm_t5:
54 define i16 @movi_modimm_t5() nounwind {
55 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
56 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #0x1
57 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
58 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
59 %in = load <8 x i16>* @vec_v8i16
60 %rv = add <8 x i16> %in, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
61 %el = extractelement <8 x i16> %rv, i32 0
65 ; CHECK-LABEL: movi_modimm_t6:
66 define i16 @movi_modimm_t6() nounwind {
67 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
68 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].8h, #0x1, lsl #8
69 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
70 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
71 %in = load <8 x i16>* @vec_v8i16
72 %rv = add <8 x i16> %in, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
73 %el = extractelement <8 x i16> %rv, i32 0
77 ; CHECK-LABEL: movi_modimm_t7:
78 define i16 @movi_modimm_t7() nounwind {
79 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
80 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1, msl #8
81 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
82 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
83 %in = load <8 x i16>* @vec_v8i16
84 %rv = add <8 x i16> %in, <i16 511, i16 0, i16 511, i16 0, i16 511, i16 0, i16 511, i16 0>
85 %el = extractelement <8 x i16> %rv, i32 0
89 ; CHECK-LABEL: movi_modimm_t8:
90 define i16 @movi_modimm_t8() nounwind {
91 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
92 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].4s, #0x1, msl #16
93 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
94 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
95 %in = load <8 x i16>* @vec_v8i16
96 %rv = add <8 x i16> %in, <i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 1, i16 65535, i16 1>
97 %el = extractelement <8 x i16> %rv, i32 0
101 ; CHECK-LABEL: movi_modimm_t9:
102 define i16 @movi_modimm_t9() nounwind {
103 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
104 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].16b, #0x1
105 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
106 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
107 %in = load <8 x i16>* @vec_v8i16
108 %rv = add <8 x i16> %in, <i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257, i16 257>
109 %el = extractelement <8 x i16> %rv, i32 0
113 ; CHECK-LABEL: movi_modimm_t10:
114 define i16 @movi_modimm_t10() nounwind {
115 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
116 ; CHECK-NEXT: movi v[[REG2:[0-9]+]].2d, #0x00ffff0000ffff
117 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
118 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
119 %in = load <8 x i16>* @vec_v8i16
120 %rv = add <8 x i16> %in, <i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0, i16 -1, i16 0>
121 %el = extractelement <8 x i16> %rv, i32 0
125 ; CHECK-LABEL: fmov_modimm_t11:
126 define i16 @fmov_modimm_t11() nounwind {
127 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
128 ; CHECK-NEXT: fmov v[[REG2:[0-9]+]].4s, #3.00000000
129 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
130 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
131 %in = load <8 x i16>* @vec_v8i16
132 %rv = add <8 x i16> %in, <i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448>
133 %el = extractelement <8 x i16> %rv, i32 0
137 ; CHECK-LABEL: fmov_modimm_t12:
138 define i16 @fmov_modimm_t12() nounwind {
139 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
140 ; CHECK-NEXT: fmov v[[REG2:[0-9]+]].2d, #0.17968750
141 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
142 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
143 %in = load <8 x i16>* @vec_v8i16
144 %rv = add <8 x i16> %in, <i16 0, i16 0, i16 0, i16 16327, i16 0, i16 0, i16 0, i16 16327>
145 %el = extractelement <8 x i16> %rv, i32 0
149 ; CHECK-LABEL: mvni_modimm_t1:
150 define i16 @mvni_modimm_t1() nounwind {
151 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
152 ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1
153 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
154 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
155 %in = load <8 x i16>* @vec_v8i16
156 %rv = add <8 x i16> %in, <i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535>
157 %el = extractelement <8 x i16> %rv, i32 0
161 ; CHECK-LABEL: mvni_modimm_t2:
162 define i16 @mvni_modimm_t2() nounwind {
163 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
164 ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1, lsl #8
165 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
166 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
167 %in = load <8 x i16>* @vec_v8i16
168 %rv = add <8 x i16> %in, <i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535>
169 %el = extractelement <8 x i16> %rv, i32 0
173 ; CHECK-LABEL: mvni_modimm_t3:
174 define i16 @mvni_modimm_t3() nounwind {
175 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
176 ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1, lsl #16
177 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
178 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
179 %in = load <8 x i16>* @vec_v8i16
180 %rv = add <8 x i16> %in, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
181 %el = extractelement <8 x i16> %rv, i32 0
185 ; CHECK-LABEL: mvni_modimm_t4:
186 define i16 @mvni_modimm_t4() nounwind {
187 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
188 ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1, lsl #24
189 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
190 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
191 %in = load <8 x i16>* @vec_v8i16
192 %rv = add <8 x i16> %in, <i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279>
193 %el = extractelement <8 x i16> %rv, i32 0
197 ; CHECK-LABEL: mvni_modimm_t5:
198 define i16 @mvni_modimm_t5() nounwind {
199 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
200 ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].8h, #0x1
201 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
202 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
203 %in = load <8 x i16>* @vec_v8i16
204 %rv = add <8 x i16> %in, <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>
205 %el = extractelement <8 x i16> %rv, i32 0
209 ; CHECK-LABEL: mvni_modimm_t6:
210 define i16 @mvni_modimm_t6() nounwind {
211 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
212 ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].8h, #0x1, lsl #8
213 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
214 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
215 %in = load <8 x i16>* @vec_v8i16
216 %rv = add <8 x i16> %in, <i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279>
217 %el = extractelement <8 x i16> %rv, i32 0
221 ; CHECK-LABEL: mvni_modimm_t7:
222 define i16 @mvni_modimm_t7() nounwind {
223 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
224 ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1, msl #8
225 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
226 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
227 %in = load <8 x i16>* @vec_v8i16
228 %rv = add <8 x i16> %in, <i16 65024, i16 65535, i16 65024, i16 65535, i16 65024, i16 65535, i16 65024, i16 65535>
229 %el = extractelement <8 x i16> %rv, i32 0
233 ; CHECK-LABEL: mvni_modimm_t8:
234 define i16 @mvni_modimm_t8() nounwind {
235 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
236 ; CHECK-NEXT: mvni v[[REG2:[0-9]+]].4s, #0x1, msl #16
237 ; CHECK-NEXT: add v[[REG1]].8h, v[[REG1]].8h, v[[REG2]].8h
238 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
239 %in = load <8 x i16>* @vec_v8i16
240 %rv = add <8 x i16> %in, <i16 0, i16 65534, i16 0, i16 65534, i16 0, i16 65534, i16 0, i16 65534>
241 %el = extractelement <8 x i16> %rv, i32 0
245 ; CHECK-LABEL: bic_modimm_t1:
246 define i16 @bic_modimm_t1() nounwind {
247 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
248 ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #0x1
249 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
250 %in = load <8 x i16>* @vec_v8i16
251 %rv = and <8 x i16> %in, <i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535>
252 %el = extractelement <8 x i16> %rv, i32 0
256 ; CHECK-LABEL: bic_modimm_t2:
257 define i16 @bic_modimm_t2() nounwind {
258 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
259 ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #0x1, lsl #8
260 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
261 %in = load <8 x i16>* @vec_v8i16
262 %rv = and <8 x i16> %in, <i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535>
263 %el = extractelement <8 x i16> %rv, i32 0
267 ; CHECK-LABEL: bic_modimm_t3:
268 define i16 @bic_modimm_t3() nounwind {
269 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
270 ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #0x1, lsl #16
271 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
272 %in = load <8 x i16>* @vec_v8i16
273 %rv = and <8 x i16> %in, <i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534, i16 65535, i16 65534>
274 %el = extractelement <8 x i16> %rv, i32 0
278 ; CHECK-LABEL: bic_modimm_t4:
279 define i16 @bic_modimm_t4() nounwind {
280 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
281 ; CHECK-NEXT: bic v[[REG2:[0-9]+]].4s, #0x1, lsl #24
282 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
283 %in = load <8 x i16>* @vec_v8i16
284 %rv = and <8 x i16> %in, <i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279, i16 65535, i16 65279>
285 %el = extractelement <8 x i16> %rv, i32 0
289 ; CHECK-LABEL: bic_modimm_t5:
290 define i16 @bic_modimm_t5() nounwind {
291 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
292 ; CHECK-NEXT: bic v[[REG2:[0-9]+]].8h, #0x1
293 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
294 %in = load <8 x i16>* @vec_v8i16
295 %rv = and <8 x i16> %in, <i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534, i16 65534>
296 %el = extractelement <8 x i16> %rv, i32 0
300 ; CHECK-LABEL: bic_modimm_t6:
301 define i16 @bic_modimm_t6() nounwind {
302 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
303 ; CHECK-NEXT: bic v[[REG2:[0-9]+]].8h, #0x1, lsl #8
304 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
305 %in = load <8 x i16>* @vec_v8i16
306 %rv = and <8 x i16> %in, <i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279, i16 65279>
307 %el = extractelement <8 x i16> %rv, i32 0
311 ; CHECK-LABEL: orr_modimm_t1:
312 define i16 @orr_modimm_t1() nounwind {
313 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
314 ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #0x1
315 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
316 %in = load <8 x i16>* @vec_v8i16
317 %rv = or <8 x i16> %in, <i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0>
318 %el = extractelement <8 x i16> %rv, i32 0
322 ; CHECK-LABEL: orr_modimm_t2:
323 define i16 @orr_modimm_t2() nounwind {
324 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
325 ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #0x1, lsl #8
326 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
327 %in = load <8 x i16>* @vec_v8i16
328 %rv = or <8 x i16> %in, <i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0>
329 %el = extractelement <8 x i16> %rv, i32 0
333 ; CHECK-LABEL: orr_modimm_t3:
334 define i16 @orr_modimm_t3() nounwind {
335 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
336 ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #0x1, lsl #16
337 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
338 %in = load <8 x i16>* @vec_v8i16
339 %rv = or <8 x i16> %in, <i16 0, i16 1, i16 0, i16 1, i16 0, i16 1, i16 0, i16 1>
340 %el = extractelement <8 x i16> %rv, i32 0
344 ; CHECK-LABEL: orr_modimm_t4:
345 define i16 @orr_modimm_t4() nounwind {
346 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
347 ; CHECK-NEXT: orr v[[REG2:[0-9]+]].4s, #0x1, lsl #24
348 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
349 %in = load <8 x i16>* @vec_v8i16
350 %rv = or <8 x i16> %in, <i16 0, i16 256, i16 0, i16 256, i16 0, i16 256, i16 0, i16 256>
351 %el = extractelement <8 x i16> %rv, i32 0
355 ; CHECK-LABEL: orr_modimm_t5:
356 define i16 @orr_modimm_t5() nounwind {
357 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
358 ; CHECK-NEXT: orr v[[REG2:[0-9]+]].8h, #0x1
359 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
360 %in = load <8 x i16>* @vec_v8i16
361 %rv = or <8 x i16> %in, <i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1, i16 1>
362 %el = extractelement <8 x i16> %rv, i32 0
366 ; CHECK-LABEL: orr_modimm_t6:
367 define i16 @orr_modimm_t6() nounwind {
368 ; CHECK: ld1 { v[[REG1:[0-9]+]].8h }, [x{{[0-9]+}}]
369 ; CHECK-NEXT: orr v[[REG2:[0-9]+]].8h, #0x1, lsl #8
370 ; CHECK-NEXT: umov w{{[0-9]+}}, v[[REG1]].h[0]
371 %in = load <8 x i16>* @vec_v8i16
372 %rv = or <8 x i16> %in, <i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256, i16 256>
373 %el = extractelement <8 x i16> %rv, i32 0
377 declare i8 @f_v8i8(<8 x i8> %arg)
378 declare i16 @f_v4i16(<4 x i16> %arg)
379 declare i32 @f_v2i32(<2 x i32> %arg)
380 declare i8 @f_v16i8(<16 x i8> %arg)
381 declare i16 @f_v8i16(<8 x i16> %arg)
382 declare i32 @f_v4i32(<4 x i32> %arg)
384 ; CHECK-LABEL: modimm_t1_call:
385 define void @modimm_t1_call() {
386 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8
387 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
388 ; CHECK-NEXT: bl f_v8i8
389 call i8 @f_v8i8(<8 x i8> <i8 8, i8 0, i8 0, i8 0, i8 8, i8 0, i8 0, i8 0>)
390 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x7
391 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
392 ; CHECK-NEXT: bl f_v4i16
393 call i16 @f_v4i16(<4 x i16> <i16 7, i16 0, i16 7, i16 0>)
394 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x6
395 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
396 ; CHECK-NEXT: bl f_v2i32
397 call i32 @f_v2i32(<2 x i32> <i32 6, i32 6>)
398 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x5
399 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
400 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
401 ; CHECK-NEXT: bl f_v16i8
402 call i8 @f_v16i8(<16 x i8> <i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0>)
403 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x4
404 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
405 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
406 ; CHECK-NEXT: bl f_v8i16
407 call i16 @f_v8i16(<8 x i16> <i16 4, i16 0, i16 4, i16 0, i16 4, i16 0, i16 4, i16 0>)
408 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x3
409 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
410 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
411 ; CHECK-NEXT: bl f_v4i32
412 call i32 @f_v4i32(<4 x i32> <i32 3, i32 3, i32 3, i32 3>)
417 ; CHECK-LABEL: modimm_t2_call:
418 define void @modimm_t2_call() {
419 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8, lsl #8
420 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
421 ; CHECK-NEXT: bl f_v8i8
422 call i8 @f_v8i8(<8 x i8> <i8 0, i8 8, i8 0, i8 0, i8 0, i8 8, i8 0, i8 0>)
423 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x7, lsl #8
424 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
425 ; CHECK-NEXT: bl f_v4i16
426 call i16 @f_v4i16(<4 x i16> <i16 1792, i16 0, i16 1792, i16 0>)
427 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x6, lsl #8
428 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
429 ; CHECK-NEXT: bl f_v2i32
430 call i32 @f_v2i32(<2 x i32> <i32 1536, i32 1536>)
431 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x5, lsl #8
432 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
433 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
434 ; CHECK-NEXT: bl f_v16i8
435 call i8 @f_v16i8(<16 x i8> <i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0>)
436 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x4, lsl #8
437 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
438 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
439 ; CHECK-NEXT: bl f_v8i16
440 call i16 @f_v8i16(<8 x i16> <i16 1024, i16 0, i16 1024, i16 0, i16 1024, i16 0, i16 1024, i16 0>)
441 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x3, lsl #8
442 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
443 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
444 ; CHECK-NEXT: bl f_v4i32
445 call i32 @f_v4i32(<4 x i32> <i32 768, i32 768, i32 768, i32 768>)
450 ; CHECK-LABEL: modimm_t3_call:
451 define void @modimm_t3_call() {
452 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8, lsl #16
453 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
454 ; CHECK-NEXT: bl f_v8i8
455 call i8 @f_v8i8(<8 x i8> <i8 0, i8 0, i8 8, i8 0, i8 0, i8 0, i8 8, i8 0>)
456 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x7, lsl #16
457 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
458 ; CHECK-NEXT: bl f_v4i16
459 call i16 @f_v4i16(<4 x i16> <i16 0, i16 7, i16 0, i16 7>)
460 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x6, lsl #16
461 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
462 ; CHECK-NEXT: bl f_v2i32
463 call i32 @f_v2i32(<2 x i32> <i32 393216, i32 393216>)
464 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x5, lsl #16
465 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
466 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
467 ; CHECK-NEXT: bl f_v16i8
468 call i8 @f_v16i8(<16 x i8> <i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0>)
469 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x4, lsl #16
470 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
471 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
472 ; CHECK-NEXT: bl f_v8i16
473 call i16 @f_v8i16(<8 x i16> <i16 0, i16 4, i16 0, i16 4, i16 0, i16 4, i16 0, i16 4>)
474 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x3, lsl #16
475 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
476 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
477 ; CHECK-NEXT: bl f_v4i32
478 call i32 @f_v4i32(<4 x i32> <i32 196608, i32 196608, i32 196608, i32 196608>)
483 ; CHECK-LABEL: modimm_t4_call:
484 define void @modimm_t4_call() {
485 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8, lsl #24
486 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
487 ; CHECK-NEXT: bl f_v8i8
488 call i8 @f_v8i8(<8 x i8> <i8 0, i8 0, i8 0, i8 8, i8 0, i8 0, i8 0, i8 8>)
489 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x7, lsl #24
490 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
491 ; CHECK-NEXT: bl f_v4i16
492 call i16 @f_v4i16(<4 x i16> <i16 0, i16 1792, i16 0, i16 1792>)
493 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x6, lsl #24
494 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
495 ; CHECK-NEXT: bl f_v2i32
496 call i32 @f_v2i32(<2 x i32> <i32 100663296, i32 100663296>)
497 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x5, lsl #24
498 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
499 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
500 ; CHECK-NEXT: bl f_v16i8
501 call i8 @f_v16i8(<16 x i8> <i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5, i8 0, i8 0, i8 0, i8 5>)
502 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x4, lsl #24
503 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
504 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
505 ; CHECK-NEXT: bl f_v8i16
506 call i16 @f_v8i16(<8 x i16> <i16 0, i16 1024, i16 0, i16 1024, i16 0, i16 1024, i16 0, i16 1024>)
507 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x3, lsl #24
508 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
509 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
510 ; CHECK-NEXT: bl f_v4i32
511 call i32 @f_v4i32(<4 x i32> <i32 50331648, i32 50331648, i32 50331648, i32 50331648>)
516 ; CHECK-LABEL: modimm_t5_call:
517 define void @modimm_t5_call() {
518 ; CHECK: movi v[[REG1:[0-9]+]].4h, #0x8
519 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
520 ; CHECK-NEXT: bl f_v8i8
521 call i8 @f_v8i8(<8 x i8> <i8 8, i8 0, i8 8, i8 0, i8 8, i8 0, i8 8, i8 0>)
522 ; CHECK: movi v[[REG1:[0-9]+]].4h, #0x7
523 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
524 ; CHECK-NEXT: bl f_v4i16
525 call i16 @f_v4i16(<4 x i16> <i16 7, i16 7, i16 7, i16 7>)
526 ; CHECK: movi v[[REG1:[0-9]+]].4h, #0x6
527 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
528 ; CHECK-NEXT: bl f_v2i32
529 call i32 @f_v2i32(<2 x i32> <i32 393222, i32 393222>)
530 ; CHECK: movi v[[REG1:[0-9]+]].8h, #0x5
531 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
532 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
533 ; CHECK-NEXT: bl f_v16i8
534 call i8 @f_v16i8(<16 x i8> <i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0>)
535 ; CHECK: movi v[[REG1:[0-9]+]].8h, #0x4
536 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
537 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
538 ; CHECK-NEXT: bl f_v8i16
539 call i16 @f_v8i16(<8 x i16> <i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4, i16 4>)
540 ; CHECK: movi v[[REG1:[0-9]+]].8h, #0x3
541 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
542 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
543 ; CHECK-NEXT: bl f_v4i32
544 call i32 @f_v4i32(<4 x i32> <i32 196611, i32 196611, i32 196611, i32 196611>)
549 ; CHECK-LABEL: modimm_t6_call:
550 define void @modimm_t6_call() {
551 ; CHECK: movi v[[REG1:[0-9]+]].4h, #0x8, lsl #8
552 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
553 ; CHECK-NEXT: bl f_v8i8
554 call i8 @f_v8i8(<8 x i8> <i8 0, i8 8, i8 0, i8 8, i8 0, i8 8, i8 0, i8 8>)
555 ; CHECK: movi v[[REG1:[0-9]+]].4h, #0x7, lsl #8
556 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
557 ; CHECK-NEXT: bl f_v4i16
558 call i16 @f_v4i16(<4 x i16> <i16 1792, i16 1792, i16 1792, i16 1792>)
559 ; CHECK: movi v[[REG1:[0-9]+]].4h, #0x6, lsl #8
560 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
561 ; CHECK-NEXT: bl f_v2i32
562 call i32 @f_v2i32(<2 x i32> <i32 100664832, i32 100664832>)
563 ; CHECK: movi v[[REG1:[0-9]+]].8h, #0x5, lsl #8
564 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
565 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
566 ; CHECK-NEXT: bl f_v16i8
567 call i8 @f_v16i8(<16 x i8> <i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5, i8 0, i8 5>)
568 ; CHECK: movi v[[REG1:[0-9]+]].8h, #0x4, lsl #8
569 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
570 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
571 ; CHECK-NEXT: bl f_v8i16
572 call i16 @f_v8i16(<8 x i16> <i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024, i16 1024>)
573 ; CHECK: movi v[[REG1:[0-9]+]].8h, #0x3, lsl #8
574 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
575 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
576 ; CHECK-NEXT: bl f_v4i32
577 call i32 @f_v4i32(<4 x i32> <i32 50332416, i32 50332416, i32 50332416, i32 50332416>)
582 ; CHECK-LABEL: modimm_t7_call:
583 define void @modimm_t7_call() {
584 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8, msl #8
585 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
586 ; CHECK-NEXT: bl f_v8i8
587 call i8 @f_v8i8(<8 x i8> <i8 255, i8 8, i8 0, i8 0, i8 255, i8 8, i8 0, i8 0>)
588 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x7, msl #8
589 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
590 ; CHECK-NEXT: bl f_v4i16
591 call i16 @f_v4i16(<4 x i16> <i16 2047, i16 0, i16 2047, i16 0>)
592 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x6, msl #8
593 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
594 ; CHECK-NEXT: bl f_v2i32
595 call i32 @f_v2i32(<2 x i32> <i32 1791, i32 1791>)
596 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x5, msl #8
597 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
598 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
599 ; CHECK-NEXT: bl f_v16i8
600 call i8 @f_v16i8(<16 x i8> <i8 255, i8 5, i8 0, i8 0, i8 255, i8 5, i8 0, i8 0, i8 255, i8 5, i8 0, i8 0, i8 255, i8 5, i8 0, i8 0>)
601 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x4, msl #8
602 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
603 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
604 ; CHECK-NEXT: bl f_v8i16
605 call i16 @f_v8i16(<8 x i16> <i16 1279, i16 0, i16 1279, i16 0, i16 1279, i16 0, i16 1279, i16 0>)
606 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x3, msl #8
607 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
608 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
609 ; CHECK-NEXT: bl f_v4i32
610 call i32 @f_v4i32(<4 x i32> <i32 1023, i32 1023, i32 1023, i32 1023>)
615 ; CHECK-LABEL: modimm_t8_call:
616 define void @modimm_t8_call() {
617 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x8, msl #16
618 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
619 ; CHECK-NEXT: bl f_v8i8
620 call i8 @f_v8i8(<8 x i8> <i8 255, i8 255, i8 8, i8 0, i8 255, i8 255, i8 8, i8 0>)
621 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x7, msl #16
622 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
623 ; CHECK-NEXT: bl f_v4i16
624 call i16 @f_v4i16(<4 x i16> <i16 65535, i16 7, i16 65535, i16 7>)
625 ; CHECK: movi v[[REG1:[0-9]+]].2s, #0x6, msl #16
626 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
627 ; CHECK-NEXT: bl f_v2i32
628 call i32 @f_v2i32(<2 x i32> <i32 458751, i32 458751>)
629 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x5, msl #16
630 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
631 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
632 ; CHECK-NEXT: bl f_v16i8
633 call i8 @f_v16i8(<16 x i8> <i8 255, i8 255, i8 5, i8 0, i8 255, i8 255, i8 5, i8 0, i8 255, i8 255, i8 5, i8 0, i8 255, i8 255, i8 5, i8 0>)
634 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x4, msl #16
635 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
636 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
637 ; CHECK-NEXT: bl f_v8i16
638 call i16 @f_v8i16(<8 x i16> <i16 65535, i16 4, i16 65535, i16 4, i16 65535, i16 4, i16 65535, i16 4>)
639 ; CHECK: movi v[[REG1:[0-9]+]].4s, #0x3, msl #16
640 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
641 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
642 ; CHECK-NEXT: bl f_v4i32
643 call i32 @f_v4i32(<4 x i32> <i32 262143, i32 262143, i32 262143, i32 262143>)
648 ; CHECK-LABEL: modimm_t9_call:
649 define void @modimm_t9_call() {
650 ; CHECK: movi v[[REG1:[0-9]+]].8b, #0x8
651 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
652 ; CHECK-NEXT: bl f_v8i8
653 call i8 @f_v8i8(<8 x i8> <i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8, i8 8>)
654 ; CHECK: movi v[[REG1:[0-9]+]].8b, #0x7
655 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
656 ; CHECK-NEXT: bl f_v4i16
657 call i16 @f_v4i16(<4 x i16> <i16 1799, i16 1799, i16 1799, i16 1799>)
658 ; CHECK: movi v[[REG1:[0-9]+]].8b, #0x6
659 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
660 ; CHECK-NEXT: bl f_v2i32
661 call i32 @f_v2i32(<2 x i32> <i32 101058054, i32 101058054>)
662 ; CHECK: movi v[[REG1:[0-9]+]].16b, #0x5
663 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
664 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
665 ; CHECK-NEXT: bl f_v16i8
666 call i8 @f_v16i8(<16 x i8> <i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5, i8 5>)
667 ; CHECK: movi v[[REG1:[0-9]+]].16b, #0x4
668 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
669 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
670 ; CHECK-NEXT: bl f_v8i16
671 call i16 @f_v8i16(<8 x i16> <i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028, i16 1028>)
672 ; CHECK: movi v[[REG1:[0-9]+]].16b, #0x3
673 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
674 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
675 ; CHECK-NEXT: bl f_v4i32
676 call i32 @f_v4i32(<4 x i32> <i32 50529027, i32 50529027, i32 50529027, i32 50529027>)
681 ; CHECK-LABEL: modimm_t10_call:
682 define void @modimm_t10_call() {
683 ; CHECK: movi d[[REG1:[0-9]+]], #0x0000ff000000ff
684 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
685 ; CHECK-NEXT: bl f_v8i8
686 call i8 @f_v8i8(<8 x i8> <i8 -1, i8 0, i8 0, i8 0, i8 -1, i8 0, i8 0, i8 0>)
687 ; CHECK: movi d[[REG1:[0-9]+]], #0x00ffff0000ffff
688 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
689 ; CHECK-NEXT: bl f_v4i16
690 call i16 @f_v4i16(<4 x i16> <i16 -1, i16 0, i16 -1, i16 0>)
691 ; CHECK: movi d[[REG1:[0-9]+]], #0xffffffffffffffff
692 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
693 ; CHECK-NEXT: bl f_v2i32
694 call i32 @f_v2i32(<2 x i32> <i32 -1, i32 -1>)
695 ; CHECK: movi v[[REG1:[0-9]+]].2d, #0xffffff00ffffff
696 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
697 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
698 ; CHECK-NEXT: bl f_v16i8
699 call i8 @f_v16i8(<16 x i8> <i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0, i8 -1, i8 -1, i8 -1, i8 0>)
700 ; CHECK: movi v[[REG1:[0-9]+]].2d, #0xffffffffffff0000
701 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
702 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
703 ; CHECK-NEXT: bl f_v8i16
704 call i16 @f_v8i16(<8 x i16> <i16 0, i16 -1, i16 -1, i16 -1, i16 0, i16 -1, i16 -1, i16 -1>)
705 ; CHECK: movi v[[REG1:[0-9]+]].2d, #0xffffffff00000000
706 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
707 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
708 ; CHECK-NEXT: bl f_v4i32
709 call i32 @f_v4i32(<4 x i32> <i32 0, i32 -1, i32 0, i32 -1>)
714 ; CHECK-LABEL: modimm_t11_call:
715 define void @modimm_t11_call() {
716 ; CHECK: fmov v[[REG1:[0-9]+]].2s, #4.00000000
717 ; CHECK-NEXT: rev64 v{{[0-9]+}}.8b, v[[REG1]].8b
718 ; CHECK-NEXT: bl f_v8i8
719 call i8 @f_v8i8(<8 x i8> <i8 0, i8 0, i8 128, i8 64, i8 0, i8 0, i8 128, i8 64>)
720 ; CHECK: fmov v[[REG1:[0-9]+]].2s, #3.75000000
721 ; CHECK-NEXT: rev64 v{{[0-9]+}}.4h, v[[REG1]].4h
722 ; CHECK-NEXT: bl f_v4i16
723 call i16 @f_v4i16(<4 x i16> <i16 0, i16 16496, i16 0, i16 16496>)
724 ; CHECK: fmov v[[REG1:[0-9]+]].2s, #3.50000000
725 ; CHECK-NEXT: rev64 v{{[0-9]+}}.2s, v[[REG1]].2s
726 ; CHECK-NEXT: bl f_v2i32
727 call i32 @f_v2i32(<2 x i32> <i32 1080033280, i32 1080033280>)
728 ; CHECK: fmov v[[REG1:[0-9]+]].4s, #3.25000000
729 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
730 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
731 ; CHECK-NEXT: bl f_v16i8
732 call i8 @f_v16i8(<16 x i8> <i8 0, i8 0, i8 80, i8 64, i8 0, i8 0, i8 80, i8 64, i8 0, i8 0, i8 80, i8 64, i8 0, i8 0, i8 80, i8 64>)
733 ; CHECK: fmov v[[REG1:[0-9]+]].4s, #3.00000000
734 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
735 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
736 ; CHECK-NEXT: bl f_v8i16
737 call i16 @f_v8i16(<8 x i16> <i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448, i16 0, i16 16448>)
738 ; CHECK: fmov v[[REG1:[0-9]+]].4s, #2.75000000
739 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
740 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
741 ; CHECK-NEXT: bl f_v4i32
742 call i32 @f_v4i32(<4 x i32> <i32 1076887552, i32 1076887552, i32 1076887552, i32 1076887552>)
747 ; CHECK-LABEL: modimm_t12_call:
748 define void @modimm_t12_call() {
749 ; CHECK: fmov v[[REG1:[0-9]+]].2d, #0.18750000
750 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].16b, v[[REG1]].16b
751 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
752 ; CHECK-NEXT: bl f_v16i8
753 call i8 @f_v16i8(<16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 200, i8 63, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 200, i8 63>)
754 ; CHECK: fmov v[[REG1:[0-9]+]].2d, #0.17968750
755 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].8h, v[[REG1]].8h
756 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
757 ; CHECK-NEXT: bl f_v8i16
758 call i16 @f_v8i16(<8 x i16> <i16 0, i16 0, i16 0, i16 16327, i16 0, i16 0, i16 0, i16 16327>)
759 ; CHECK: fmov v[[REG1:[0-9]+]].2d, #0.17187500
760 ; CHECK-NEXT: rev64 v[[REG2:[0-9]+]].4s, v[[REG1]].4s
761 ; CHECK-NEXT: ext v[[REG2]].16b, v[[REG2]].16b, v[[REG2]].16b, #8
762 ; CHECK-NEXT: bl f_v4i32
763 call i32 @f_v4i32(<4 x i32> <i32 0, i32 1069940736, i32 0, i32 1069940736>)