1 //===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
15 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetFrameInfo.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Type.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
38 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
39 : XCoreGenRegisterInfo(XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
44 static inline bool isImmUs(unsigned val) {
48 static inline bool isImmU6(unsigned val) {
49 return val < (1 << 6);
52 static inline bool isImmU16(unsigned val) {
53 return val < (1 << 16);
56 static const unsigned XCore_ArgRegs[] = {
57 XCore::R0, XCore::R1, XCore::R2, XCore::R3
60 const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
65 unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
67 return array_lengthof(XCore_ArgRegs);
70 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
71 return MF.getMMI().hasDebugInfo() || !MF.getFunction()->doesNotThrow() ||
72 UnwindTablesMandatory;
75 const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
77 static const unsigned CalleeSavedRegs[] = {
78 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
79 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
82 return CalleeSavedRegs;
85 const TargetRegisterClass* const*
86 XCoreRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
87 static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
88 XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
89 XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
90 XCore::GRRegsRegisterClass, XCore::GRRegsRegisterClass,
91 XCore::GRRegsRegisterClass, XCore::RRegsRegisterClass,
94 return CalleeSavedRegClasses;
97 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
98 BitVector Reserved(getNumRegs());
99 Reserved.set(XCore::CP);
100 Reserved.set(XCore::DP);
101 Reserved.set(XCore::SP);
102 Reserved.set(XCore::LR);
104 Reserved.set(XCore::R10);
110 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
111 // TODO can we estimate stack size?
115 bool XCoreRegisterInfo::hasFP(const MachineFunction &MF) const {
116 return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
119 // This function eliminates ADJCALLSTACKDOWN,
120 // ADJCALLSTACKUP pseudo instructions
121 void XCoreRegisterInfo::
122 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
123 MachineBasicBlock::iterator I) const {
124 if (!hasReservedCallFrame(MF)) {
125 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
126 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
127 MachineInstr *Old = I;
128 uint64_t Amount = Old->getOperand(0).getImm();
130 // We need to keep the stack aligned properly. To do this, we round the
131 // amount of space needed for the outgoing arguments up to the next
132 // alignment boundary.
133 unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
134 Amount = (Amount+Align-1)/Align*Align;
136 assert(Amount%4 == 0);
139 bool isU6 = isImmU6(Amount);
141 if (!isU6 && !isImmU16(Amount)) {
142 // FIX could emit multiple instructions in this case.
144 errs() << "eliminateCallFramePseudoInstr size too big: "
151 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
152 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
153 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
156 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
157 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
158 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
162 // Replace the pseudo instruction with a new instruction...
171 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
172 int SPAdj, FrameIndexValue *Value,
173 RegScavenger *RS) const {
174 assert(SPAdj == 0 && "Unexpected");
175 MachineInstr &MI = *II;
176 DebugLoc dl = MI.getDebugLoc();
179 while (!MI.getOperand(i).isFI()) {
181 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
184 MachineOperand &FrameOp = MI.getOperand(i);
185 int FrameIndex = FrameOp.getIndex();
187 MachineFunction &MF = *MI.getParent()->getParent();
188 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
189 int StackSize = MF.getFrameInfo()->getStackSize();
192 DEBUG(errs() << "\nFunction : "
193 << MF.getFunction()->getName() << "\n");
194 DEBUG(errs() << "<--------->\n");
195 DEBUG(MI.print(errs()));
196 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
197 DEBUG(errs() << "FrameOffset : " << Offset << "\n");
198 DEBUG(errs() << "StackSize : " << StackSize << "\n");
203 // fold constant into offset.
204 Offset += MI.getOperand(i + 1).getImm();
205 MI.getOperand(i + 1).ChangeToImmediate(0);
207 assert(Offset%4 == 0 && "Misaligned stack offset");
209 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
215 unsigned Reg = MI.getOperand(0).getReg();
216 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
218 assert(XCore::GRRegsRegisterClass->contains(Reg) &&
219 "Unexpected register operand");
221 MachineBasicBlock &MBB = *MI.getParent();
224 bool isUs = isImmUs(Offset);
225 unsigned FramePtr = XCore::R10;
230 raw_string_ostream Msg(msg);
231 Msg << "eliminateFrameIndex Frame size too big: " << Offset;
232 llvm_report_error(Msg.str());
234 unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
236 loadConstant(MBB, II, ScratchReg, Offset, dl);
237 switch (MI.getOpcode()) {
239 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
241 .addReg(ScratchReg, RegState::Kill);
244 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
245 .addReg(Reg, getKillRegState(isKill))
247 .addReg(ScratchReg, RegState::Kill);
250 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
252 .addReg(ScratchReg, RegState::Kill);
255 llvm_unreachable("Unexpected Opcode");
258 switch (MI.getOpcode()) {
260 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
265 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
266 .addReg(Reg, getKillRegState(isKill))
271 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
276 llvm_unreachable("Unexpected Opcode");
280 bool isU6 = isImmU6(Offset);
281 if (!isU6 && !isImmU16(Offset)) {
283 raw_string_ostream Msg(msg);
284 Msg << "eliminateFrameIndex Frame size too big: " << Offset;
285 llvm_report_error(Msg.str());
288 switch (MI.getOpcode()) {
291 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
292 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
296 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
297 BuildMI(MBB, II, dl, TII.get(NewOpcode))
298 .addReg(Reg, getKillRegState(isKill))
302 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
303 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
307 llvm_unreachable("Unexpected Opcode");
310 // Erase old instruction.
316 XCoreRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
317 RegScavenger *RS) const {
318 MachineFrameInfo *MFI = MF.getFrameInfo();
319 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
320 const TargetRegisterClass *RC = XCore::GRRegsRegisterClass;
321 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
323 MF.getRegInfo().setPhysRegUnused(XCore::LR);
325 bool isVarArg = MF.getFunction()->isVarArg();
328 // A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
329 FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true, false);
331 FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(),
334 XFI->setUsesLR(FrameIdx);
335 XFI->setLRSpillSlot(FrameIdx);
337 if (requiresRegisterScavenging(MF)) {
338 // Reserve a slot close to SP or frame pointer.
339 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
344 // A callee save register is used to hold the FP.
345 // This needs saving / restoring in the epilogue / prologue.
346 XFI->setFPSpillSlot(MFI->CreateStackObject(RC->getSize(),
352 void XCoreRegisterInfo::
353 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {
357 void XCoreRegisterInfo::
358 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
359 unsigned DstReg, int64_t Value, DebugLoc dl) const {
360 // TODO use mkmsk if possible.
361 if (!isImmU16(Value)) {
362 // TODO use constant pool.
364 raw_string_ostream Msg(msg);
365 Msg << "loadConstant value too big " << Value;
366 llvm_report_error(Msg.str());
368 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
369 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
372 void XCoreRegisterInfo::
373 storeToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
374 unsigned SrcReg, int Offset, DebugLoc dl) const {
375 assert(Offset%4 == 0 && "Misaligned stack offset");
377 bool isU6 = isImmU6(Offset);
378 if (!isU6 && !isImmU16(Offset)) {
380 raw_string_ostream Msg(msg);
381 Msg << "storeToStack offset too big " << Offset;
382 llvm_report_error(Msg.str());
384 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
385 BuildMI(MBB, I, dl, TII.get(Opcode))
390 void XCoreRegisterInfo::
391 loadFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
392 unsigned DstReg, int Offset, DebugLoc dl) const {
393 assert(Offset%4 == 0 && "Misaligned stack offset");
395 bool isU6 = isImmU6(Offset);
396 if (!isU6 && !isImmU16(Offset)) {
398 raw_string_ostream Msg(msg);
399 Msg << "loadFromStack offset too big " << Offset;
400 llvm_report_error(Msg.str());
402 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
403 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
407 void XCoreRegisterInfo::emitPrologue(MachineFunction &MF) const {
408 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
409 MachineBasicBlock::iterator MBBI = MBB.begin();
410 MachineFrameInfo *MFI = MF.getFrameInfo();
411 MachineModuleInfo *MMI = &MF.getMMI();
412 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
413 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
417 // Work out frame sizes.
418 int FrameSize = MFI->getStackSize();
420 assert(FrameSize%4 == 0 && "Misaligned frame size");
424 bool isU6 = isImmU6(FrameSize);
426 if (!isU6 && !isImmU16(FrameSize)) {
427 // FIXME could emit multiple instructions.
429 raw_string_ostream Msg(msg);
430 Msg << "emitPrologue Frame size too big: " << FrameSize;
431 llvm_report_error(Msg.str());
433 bool emitFrameMoves = needsFrameMoves(MF);
435 // Do we need to allocate space on the stack?
437 bool saveLR = XFI->getUsesLR();
438 bool LRSavedOnEntry = false;
440 if (saveLR && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0)) {
441 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
442 MBB.addLiveIn(XCore::LR);
444 LRSavedOnEntry = true;
446 Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
448 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
450 if (emitFrameMoves) {
451 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
453 // Show update of SP.
454 MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
455 BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addSym(FrameLabel);
457 MachineLocation SPDst(MachineLocation::VirtualFP);
458 MachineLocation SPSrc(MachineLocation::VirtualFP, -FrameSize * 4);
459 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc));
461 if (LRSavedOnEntry) {
462 MachineLocation CSDst(MachineLocation::VirtualFP, 0);
463 MachineLocation CSSrc(XCore::LR);
464 Moves.push_back(MachineMove(FrameLabel, CSDst, CSSrc));
468 int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
469 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl);
470 MBB.addLiveIn(XCore::LR);
472 if (emitFrameMoves) {
473 MCSymbol *SaveLRLabel = MMI->getContext().CreateTempSymbol();
474 BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addSym(SaveLRLabel);
475 MachineLocation CSDst(MachineLocation::VirtualFP, LRSpillOffset);
476 MachineLocation CSSrc(XCore::LR);
477 MMI->getFrameMoves().push_back(MachineMove(SaveLRLabel, CSDst, CSSrc));
483 // Save R10 to the stack.
484 int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
485 storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl);
486 // R10 is live-in. It is killed at the spill.
487 MBB.addLiveIn(XCore::R10);
488 if (emitFrameMoves) {
489 MCSymbol *SaveR10Label = MMI->getContext().CreateTempSymbol();
490 BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addSym(SaveR10Label);
491 MachineLocation CSDst(MachineLocation::VirtualFP, FPSpillOffset);
492 MachineLocation CSSrc(XCore::R10);
493 MMI->getFrameMoves().push_back(MachineMove(SaveR10Label, CSDst, CSSrc));
495 // Set the FP from the SP.
496 unsigned FramePtr = XCore::R10;
497 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr)
499 if (emitFrameMoves) {
500 // Show FP is now valid.
501 MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
502 BuildMI(MBB, MBBI, dl, TII.get(XCore::DBG_LABEL)).addSym(FrameLabel);
503 MachineLocation SPDst(FramePtr);
504 MachineLocation SPSrc(MachineLocation::VirtualFP);
505 MMI->getFrameMoves().push_back(MachineMove(FrameLabel, SPDst, SPSrc));
509 if (emitFrameMoves) {
510 // Frame moves for callee saved.
511 std::vector<MachineMove> &Moves = MMI->getFrameMoves();
512 std::vector<std::pair<MCSymbol*, CalleeSavedInfo> >&SpillLabels =
513 XFI->getSpillLabels();
514 for (unsigned I = 0, E = SpillLabels.size(); I != E; ++I) {
515 MCSymbol *SpillLabel = SpillLabels[I].first;
516 CalleeSavedInfo &CSI = SpillLabels[I].second;
517 int Offset = MFI->getObjectOffset(CSI.getFrameIdx());
518 unsigned Reg = CSI.getReg();
519 MachineLocation CSDst(MachineLocation::VirtualFP, Offset);
520 MachineLocation CSSrc(Reg);
521 Moves.push_back(MachineMove(SpillLabel, CSDst, CSSrc));
526 void XCoreRegisterInfo::emitEpilogue(MachineFunction &MF,
527 MachineBasicBlock &MBB) const {
528 MachineFrameInfo *MFI = MF.getFrameInfo();
529 MachineBasicBlock::iterator MBBI = prior(MBB.end());
530 DebugLoc dl = MBBI->getDebugLoc();
535 // Restore the stack pointer.
536 unsigned FramePtr = XCore::R10;
537 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r))
541 // Work out frame sizes.
542 int FrameSize = MFI->getStackSize();
544 assert(FrameSize%4 == 0 && "Misaligned frame size");
548 bool isU6 = isImmU6(FrameSize);
550 if (!isU6 && !isImmU16(FrameSize)) {
551 // FIXME could emit multiple instructions.
553 raw_string_ostream Msg(msg);
554 Msg << "emitEpilogue Frame size too big: " << FrameSize;
555 llvm_report_error(Msg.str());
559 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
563 int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
564 FPSpillOffset += FrameSize*4;
565 loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl);
567 bool restoreLR = XFI->getUsesLR();
568 if (restoreLR && MFI->getObjectOffset(XFI->getLRSpillSlot()) != 0) {
569 int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
570 LRSpillOffset += FrameSize*4;
571 loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl);
575 // Fold prologue into return instruction
576 assert(MBBI->getOpcode() == XCore::RETSP_u6
577 || MBBI->getOpcode() == XCore::RETSP_lu6);
578 int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
579 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
582 int Opcode = (isU6) ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
583 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize);
588 int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
589 return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
592 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
595 return FP ? XCore::R10 : XCore::SP;
598 unsigned XCoreRegisterInfo::getRARegister() const {
602 void XCoreRegisterInfo::getInitialFrameState(std::vector<MachineMove> &Moves)
604 // Initial state of the frame pointer is SP.
605 MachineLocation Dst(MachineLocation::VirtualFP);
606 MachineLocation Src(XCore::SP, 0);
607 Moves.push_back(MachineMove(0, Dst, Src));
610 #include "XCoreGenRegisterInfo.inc"