1 //===-- XCoreRegisterInfo.cpp - XCore Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
16 #include "XCoreInstrInfo.h"
17 #include "XCoreMachineFunctionInfo.h"
18 #include "XCoreSubtarget.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/RegisterScavenging.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/Type.h"
29 #include "llvm/Support/Debug.h"
30 #include "llvm/Support/ErrorHandling.h"
31 #include "llvm/Support/MathExtras.h"
32 #include "llvm/Support/raw_ostream.h"
33 #include "llvm/Target/TargetFrameLowering.h"
34 #include "llvm/Target/TargetMachine.h"
35 #include "llvm/Target/TargetOptions.h"
39 #define DEBUG_TYPE "xcore-reg-info"
41 #define GET_REGINFO_TARGET_DESC
42 #include "XCoreGenRegisterInfo.inc"
44 XCoreRegisterInfo::XCoreRegisterInfo()
45 : XCoreGenRegisterInfo(XCore::LR) {
49 static inline bool isImmUs(unsigned val) {
53 static inline bool isImmU6(unsigned val) {
54 return val < (1 << 6);
57 static inline bool isImmU16(unsigned val) {
58 return val < (1 << 16);
62 static void InsertFPImmInst(MachineBasicBlock::iterator II,
63 const XCoreInstrInfo &TII,
64 unsigned Reg, unsigned FrameReg, int Offset ) {
65 MachineInstr &MI = *II;
66 MachineBasicBlock &MBB = *MI.getParent();
67 DebugLoc dl = MI.getDebugLoc();
69 switch (MI.getOpcode()) {
71 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
74 .addMemOperand(*MI.memoperands_begin());
77 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
78 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
81 .addMemOperand(*MI.memoperands_begin());
84 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
89 llvm_unreachable("Unexpected Opcode");
93 static void InsertFPConstInst(MachineBasicBlock::iterator II,
94 const XCoreInstrInfo &TII,
95 unsigned Reg, unsigned FrameReg,
96 int Offset, RegScavenger *RS ) {
97 assert(RS && "requiresRegisterScavenging failed");
98 MachineInstr &MI = *II;
99 MachineBasicBlock &MBB = *MI.getParent();
100 DebugLoc dl = MI.getDebugLoc();
101 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
102 RS->setUsed(ScratchOffset);
103 TII.loadImmediate(MBB, II, ScratchOffset, Offset);
105 switch (MI.getOpcode()) {
107 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
109 .addReg(ScratchOffset, RegState::Kill)
110 .addMemOperand(*MI.memoperands_begin());
113 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
114 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
116 .addReg(ScratchOffset, RegState::Kill)
117 .addMemOperand(*MI.memoperands_begin());
120 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
122 .addReg(ScratchOffset, RegState::Kill);
125 llvm_unreachable("Unexpected Opcode");
129 static void InsertSPImmInst(MachineBasicBlock::iterator II,
130 const XCoreInstrInfo &TII,
131 unsigned Reg, int Offset) {
132 MachineInstr &MI = *II;
133 MachineBasicBlock &MBB = *MI.getParent();
134 DebugLoc dl = MI.getDebugLoc();
135 bool isU6 = isImmU6(Offset);
137 switch (MI.getOpcode()) {
140 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
141 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
143 .addMemOperand(*MI.memoperands_begin());
146 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
147 BuildMI(MBB, II, dl, TII.get(NewOpcode))
148 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
150 .addMemOperand(*MI.memoperands_begin());
153 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
154 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
158 llvm_unreachable("Unexpected Opcode");
162 static void InsertSPConstInst(MachineBasicBlock::iterator II,
163 const XCoreInstrInfo &TII,
164 unsigned Reg, int Offset, RegScavenger *RS ) {
165 assert(RS && "requiresRegisterScavenging failed");
166 MachineInstr &MI = *II;
167 MachineBasicBlock &MBB = *MI.getParent();
168 DebugLoc dl = MI.getDebugLoc();
169 unsigned OpCode = MI.getOpcode();
171 unsigned ScratchBase;
172 if (OpCode==XCore::STWFI) {
173 ScratchBase = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
174 RS->setUsed(ScratchBase);
177 BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0);
178 unsigned ScratchOffset = RS->scavengeRegister(&XCore::GRRegsRegClass, II, 0);
179 RS->setUsed(ScratchOffset);
180 TII.loadImmediate(MBB, II, ScratchOffset, Offset);
184 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
185 .addReg(ScratchBase, RegState::Kill)
186 .addReg(ScratchOffset, RegState::Kill)
187 .addMemOperand(*MI.memoperands_begin());
190 BuildMI(MBB, II, dl, TII.get(XCore::STW_l3r))
191 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
192 .addReg(ScratchBase, RegState::Kill)
193 .addReg(ScratchOffset, RegState::Kill)
194 .addMemOperand(*MI.memoperands_begin());
197 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
198 .addReg(ScratchBase, RegState::Kill)
199 .addReg(ScratchOffset, RegState::Kill);
202 llvm_unreachable("Unexpected Opcode");
206 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
207 return MF.getMMI().hasDebugInfo() ||
208 MF.getFunction()->needsUnwindTableEntry();
211 const MCPhysReg* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
213 // The callee saved registers LR & FP are explicitly handled during
214 // emitPrologue & emitEpilogue and related functions.
215 static const MCPhysReg CalleeSavedRegs[] = {
216 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
217 XCore::R8, XCore::R9, XCore::R10,
220 static const MCPhysReg CalleeSavedRegsFP[] = {
221 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
222 XCore::R8, XCore::R9,
225 const TargetFrameLowering *TFI =
226 MF->getTarget().getSubtargetImpl()->getFrameLowering();
228 return CalleeSavedRegsFP;
229 return CalleeSavedRegs;
232 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
233 BitVector Reserved(getNumRegs());
234 const TargetFrameLowering *TFI =
235 MF.getTarget().getSubtargetImpl()->getFrameLowering();
237 Reserved.set(XCore::CP);
238 Reserved.set(XCore::DP);
239 Reserved.set(XCore::SP);
240 Reserved.set(XCore::LR);
241 if (TFI->hasFP(MF)) {
242 Reserved.set(XCore::R10);
248 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
253 XCoreRegisterInfo::trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
258 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
263 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
264 int SPAdj, unsigned FIOperandNum,
265 RegScavenger *RS) const {
266 assert(SPAdj == 0 && "Unexpected");
267 MachineInstr &MI = *II;
268 MachineOperand &FrameOp = MI.getOperand(FIOperandNum);
269 int FrameIndex = FrameOp.getIndex();
271 MachineFunction &MF = *MI.getParent()->getParent();
272 const XCoreInstrInfo &TII =
273 *static_cast<const XCoreInstrInfo *>(
274 MF.getTarget().getSubtargetImpl()->getInstrInfo());
276 const TargetFrameLowering *TFI =
277 MF.getTarget().getSubtargetImpl()->getFrameLowering();
278 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
279 int StackSize = MF.getFrameInfo()->getStackSize();
282 DEBUG(errs() << "\nFunction : "
283 << MF.getName() << "\n");
284 DEBUG(errs() << "<--------->\n");
285 DEBUG(MI.print(errs()));
286 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
287 DEBUG(errs() << "FrameOffset : " << Offset << "\n");
288 DEBUG(errs() << "StackSize : " << StackSize << "\n");
293 unsigned FrameReg = getFrameRegister(MF);
295 // Special handling of DBG_VALUE instructions.
296 if (MI.isDebugValue()) {
297 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false /*isDef*/);
298 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
302 // fold constant into offset.
303 Offset += MI.getOperand(FIOperandNum + 1).getImm();
304 MI.getOperand(FIOperandNum + 1).ChangeToImmediate(0);
306 assert(Offset%4 == 0 && "Misaligned stack offset");
307 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
310 unsigned Reg = MI.getOperand(0).getReg();
311 assert(XCore::GRRegsRegClass.contains(Reg) && "Unexpected register operand");
313 if (TFI->hasFP(MF)) {
315 InsertFPImmInst(II, TII, Reg, FrameReg, Offset);
317 InsertFPConstInst(II, TII, Reg, FrameReg, Offset, RS);
319 if (isImmU16(Offset))
320 InsertSPImmInst(II, TII, Reg, Offset);
322 InsertSPConstInst(II, TII, Reg, Offset, RS);
324 // Erase old instruction.
325 MachineBasicBlock &MBB = *MI.getParent();
330 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
331 const TargetFrameLowering *TFI =
332 MF.getTarget().getSubtargetImpl()->getFrameLowering();
334 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;