1 //===- XCoreRegisterInfo.cpp - XCore Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the XCore implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreRegisterInfo.h"
15 #include "XCoreMachineFunctionInfo.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/CodeGen/MachineModuleInfo.h"
22 #include "llvm/CodeGen/MachineRegisterInfo.h"
23 #include "llvm/CodeGen/RegisterScavenging.h"
24 #include "llvm/Target/TargetFrameLowering.h"
25 #include "llvm/Target/TargetMachine.h"
26 #include "llvm/Target/TargetOptions.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Type.h"
29 #include "llvm/Function.h"
30 #include "llvm/ADT/BitVector.h"
31 #include "llvm/ADT/STLExtras.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "XCoreGenRegisterDesc.inc"
36 #include "XCoreGenRegisterInfo.inc"
39 XCoreRegisterInfo::XCoreRegisterInfo(const TargetInstrInfo &tii)
40 : XCoreGenRegisterInfo(XCoreRegDesc, XCoreRegInfoDesc,
41 XCore::ADJCALLSTACKDOWN, XCore::ADJCALLSTACKUP),
46 static inline bool isImmUs(unsigned val) {
50 static inline bool isImmU6(unsigned val) {
51 return val < (1 << 6);
54 static inline bool isImmU16(unsigned val) {
55 return val < (1 << 16);
58 static const unsigned XCore_ArgRegs[] = {
59 XCore::R0, XCore::R1, XCore::R2, XCore::R3
62 const unsigned * XCoreRegisterInfo::getArgRegs(const MachineFunction *MF)
67 unsigned XCoreRegisterInfo::getNumArgRegs(const MachineFunction *MF)
69 return array_lengthof(XCore_ArgRegs);
72 bool XCoreRegisterInfo::needsFrameMoves(const MachineFunction &MF) {
73 return MF.getMMI().hasDebugInfo() ||
74 MF.getFunction()->needsUnwindTableEntry();
77 const unsigned* XCoreRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
79 static const unsigned CalleeSavedRegs[] = {
80 XCore::R4, XCore::R5, XCore::R6, XCore::R7,
81 XCore::R8, XCore::R9, XCore::R10, XCore::LR,
84 return CalleeSavedRegs;
87 BitVector XCoreRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
88 BitVector Reserved(getNumRegs());
89 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
91 Reserved.set(XCore::CP);
92 Reserved.set(XCore::DP);
93 Reserved.set(XCore::SP);
94 Reserved.set(XCore::LR);
96 Reserved.set(XCore::R10);
102 XCoreRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
103 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
105 // TODO can we estimate stack size?
106 return TFI->hasFP(MF);
110 XCoreRegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
114 // This function eliminates ADJCALLSTACKDOWN,
115 // ADJCALLSTACKUP pseudo instructions
116 void XCoreRegisterInfo::
117 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
118 MachineBasicBlock::iterator I) const {
119 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
121 if (!TFI->hasReservedCallFrame(MF)) {
122 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
123 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
124 MachineInstr *Old = I;
125 uint64_t Amount = Old->getOperand(0).getImm();
127 // We need to keep the stack aligned properly. To do this, we round the
128 // amount of space needed for the outgoing arguments up to the next
129 // alignment boundary.
130 unsigned Align = TFI->getStackAlignment();
131 Amount = (Amount+Align-1)/Align*Align;
133 assert(Amount%4 == 0);
136 bool isU6 = isImmU6(Amount);
137 if (!isU6 && !isImmU16(Amount)) {
138 // FIX could emit multiple instructions in this case.
140 errs() << "eliminateCallFramePseudoInstr size too big: "
147 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
148 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
149 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
152 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
153 int Opcode = isU6 ? XCore::LDAWSP_ru6_RRegs : XCore::LDAWSP_lru6_RRegs;
154 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
158 // Replace the pseudo instruction with a new instruction...
167 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
168 int SPAdj, RegScavenger *RS) const {
169 assert(SPAdj == 0 && "Unexpected");
170 MachineInstr &MI = *II;
171 DebugLoc dl = MI.getDebugLoc();
174 while (!MI.getOperand(i).isFI()) {
176 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
179 MachineOperand &FrameOp = MI.getOperand(i);
180 int FrameIndex = FrameOp.getIndex();
182 MachineFunction &MF = *MI.getParent()->getParent();
183 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
184 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
185 int StackSize = MF.getFrameInfo()->getStackSize();
188 DEBUG(errs() << "\nFunction : "
189 << MF.getFunction()->getName() << "\n");
190 DEBUG(errs() << "<--------->\n");
191 DEBUG(MI.print(errs()));
192 DEBUG(errs() << "FrameIndex : " << FrameIndex << "\n");
193 DEBUG(errs() << "FrameOffset : " << Offset << "\n");
194 DEBUG(errs() << "StackSize : " << StackSize << "\n");
199 // fold constant into offset.
200 Offset += MI.getOperand(i + 1).getImm();
201 MI.getOperand(i + 1).ChangeToImmediate(0);
203 assert(Offset%4 == 0 && "Misaligned stack offset");
205 DEBUG(errs() << "Offset : " << Offset << "\n" << "<--------->\n");
209 bool FP = TFI->hasFP(MF);
211 unsigned Reg = MI.getOperand(0).getReg();
212 bool isKill = MI.getOpcode() == XCore::STWFI && MI.getOperand(0).isKill();
214 assert(XCore::GRRegsRegisterClass->contains(Reg) &&
215 "Unexpected register operand");
217 MachineBasicBlock &MBB = *MI.getParent();
220 bool isUs = isImmUs(Offset);
221 unsigned FramePtr = XCore::R10;
225 report_fatal_error("eliminateFrameIndex Frame size too big: " +
227 unsigned ScratchReg = RS->scavengeRegister(XCore::GRRegsRegisterClass, II,
229 loadConstant(MBB, II, ScratchReg, Offset, dl);
230 switch (MI.getOpcode()) {
232 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
234 .addReg(ScratchReg, RegState::Kill);
237 BuildMI(MBB, II, dl, TII.get(XCore::STW_3r))
238 .addReg(Reg, getKillRegState(isKill))
240 .addReg(ScratchReg, RegState::Kill);
243 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
245 .addReg(ScratchReg, RegState::Kill);
248 llvm_unreachable("Unexpected Opcode");
251 switch (MI.getOpcode()) {
253 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
258 BuildMI(MBB, II, dl, TII.get(XCore::STW_2rus))
259 .addReg(Reg, getKillRegState(isKill))
264 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
269 llvm_unreachable("Unexpected Opcode");
273 bool isU6 = isImmU6(Offset);
274 if (!isU6 && !isImmU16(Offset))
275 report_fatal_error("eliminateFrameIndex Frame size too big: " +
278 switch (MI.getOpcode()) {
281 NewOpcode = (isU6) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
282 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
286 NewOpcode = (isU6) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
287 BuildMI(MBB, II, dl, TII.get(NewOpcode))
288 .addReg(Reg, getKillRegState(isKill))
292 NewOpcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
293 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
297 llvm_unreachable("Unexpected Opcode");
300 // Erase old instruction.
304 void XCoreRegisterInfo::
305 loadConstant(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
306 unsigned DstReg, int64_t Value, DebugLoc dl) const {
307 // TODO use mkmsk if possible.
308 if (!isImmU16(Value)) {
309 // TODO use constant pool.
310 report_fatal_error("loadConstant value too big " + Twine(Value));
312 int Opcode = isImmU6(Value) ? XCore::LDC_ru6 : XCore::LDC_lru6;
313 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg).addImm(Value);
316 int XCoreRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
317 return XCoreGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
320 int XCoreRegisterInfo::getLLVMRegNum(unsigned DwarfRegNo, bool isEH) const {
321 return XCoreGenRegisterInfo::getLLVMRegNumFull(DwarfRegNo,0);
324 unsigned XCoreRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
325 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
327 return TFI->hasFP(MF) ? XCore::R10 : XCore::SP;
330 unsigned XCoreRegisterInfo::getRARegister() const {