1 //===-- XCoreInstrInfo.td - Target Description for XCore ---*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the XCore instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 // Uses of CP, DP are not currently reflected in the patterns, since
15 // having a physical register as an operand prevents loop hoisting and
16 // since the value of these registers never changes during the life of the
19 //===----------------------------------------------------------------------===//
20 // Instruction format superclass.
21 //===----------------------------------------------------------------------===//
23 include "XCoreInstrFormats.td"
25 //===----------------------------------------------------------------------===//
26 // XCore specific DAG Nodes.
30 def SDT_XCoreBranchLink : SDTypeProfile<0, 1, [SDTCisPtrTy<0>]>;
31 def XCoreBranchLink : SDNode<"XCoreISD::BL",SDT_XCoreBranchLink,
32 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
35 def XCoreRetsp : SDNode<"XCoreISD::RETSP", SDTBrind,
36 [SDNPHasChain, SDNPOptInGlue, SDNPMayLoad, SDNPVariadic]>;
38 def SDT_XCoreBR_JT : SDTypeProfile<0, 2,
39 [SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
41 def XCoreBR_JT : SDNode<"XCoreISD::BR_JT", SDT_XCoreBR_JT,
44 def XCoreBR_JT32 : SDNode<"XCoreISD::BR_JT32", SDT_XCoreBR_JT,
47 def SDT_XCoreAddress : SDTypeProfile<1, 1,
48 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
50 def pcrelwrapper : SDNode<"XCoreISD::PCRelativeWrapper", SDT_XCoreAddress,
53 def dprelwrapper : SDNode<"XCoreISD::DPRelativeWrapper", SDT_XCoreAddress,
56 def cprelwrapper : SDNode<"XCoreISD::CPRelativeWrapper", SDT_XCoreAddress,
59 def SDT_XCoreStwsp : SDTypeProfile<0, 2, [SDTCisInt<1>]>;
60 def XCoreStwsp : SDNode<"XCoreISD::STWSP", SDT_XCoreStwsp,
61 [SDNPHasChain, SDNPMayStore]>;
63 // These are target-independent nodes, but have target-specific formats.
64 def SDT_XCoreCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
65 def SDT_XCoreCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
68 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_XCoreCallSeqStart,
69 [SDNPHasChain, SDNPOutGlue]>;
70 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XCoreCallSeqEnd,
71 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
73 //===----------------------------------------------------------------------===//
74 // Instruction Pattern Stuff
75 //===----------------------------------------------------------------------===//
77 def div4_xform : SDNodeXForm<imm, [{
78 // Transformation function: imm/4
79 assert(N->getZExtValue() % 4 == 0);
80 return getI32Imm(N->getZExtValue()/4);
83 def msksize_xform : SDNodeXForm<imm, [{
84 // Transformation function: get the size of a mask
85 assert(isMask_32(N->getZExtValue()));
86 // look for the first non-zero bit
87 return getI32Imm(32 - CountLeadingZeros_32(N->getZExtValue()));
90 def neg_xform : SDNodeXForm<imm, [{
91 // Transformation function: -imm
92 uint32_t value = N->getZExtValue();
93 return getI32Imm(-value);
96 def bpwsub_xform : SDNodeXForm<imm, [{
97 // Transformation function: 32-imm
98 uint32_t value = N->getZExtValue();
99 return getI32Imm(32-value);
102 def div4neg_xform : SDNodeXForm<imm, [{
103 // Transformation function: -imm/4
104 uint32_t value = N->getZExtValue();
105 assert(-value % 4 == 0);
106 return getI32Imm(-value/4);
109 def immUs4Neg : PatLeaf<(imm), [{
110 uint32_t value = (uint32_t)N->getZExtValue();
111 return (-value)%4 == 0 && (-value)/4 <= 11;
114 def immUs4 : PatLeaf<(imm), [{
115 uint32_t value = (uint32_t)N->getZExtValue();
116 return value%4 == 0 && value/4 <= 11;
119 def immUsNeg : PatLeaf<(imm), [{
120 return -((uint32_t)N->getZExtValue()) <= 11;
123 def immUs : PatLeaf<(imm), [{
124 return (uint32_t)N->getZExtValue() <= 11;
127 def immU6 : PatLeaf<(imm), [{
128 return (uint32_t)N->getZExtValue() < (1 << 6);
131 def immU10 : PatLeaf<(imm), [{
132 return (uint32_t)N->getZExtValue() < (1 << 10);
135 def immU16 : PatLeaf<(imm), [{
136 return (uint32_t)N->getZExtValue() < (1 << 16);
139 def immU20 : PatLeaf<(imm), [{
140 return (uint32_t)N->getZExtValue() < (1 << 20);
143 def immMskBitp : PatLeaf<(imm), [{ return immMskBitp(N); }]>;
145 def immBitp : PatLeaf<(imm), [{
146 uint32_t value = (uint32_t)N->getZExtValue();
147 return (value >= 1 && value <= 8)
153 def immBpwSubBitp : PatLeaf<(imm), [{
154 uint32_t value = (uint32_t)N->getZExtValue();
155 return (value >= 24 && value <= 31)
161 def lda16f : PatFrag<(ops node:$addr, node:$offset),
162 (add node:$addr, (shl node:$offset, 1))>;
163 def lda16b : PatFrag<(ops node:$addr, node:$offset),
164 (sub node:$addr, (shl node:$offset, 1))>;
165 def ldawf : PatFrag<(ops node:$addr, node:$offset),
166 (add node:$addr, (shl node:$offset, 2))>;
167 def ldawb : PatFrag<(ops node:$addr, node:$offset),
168 (sub node:$addr, (shl node:$offset, 2))>;
170 // Instruction operand types
171 def calltarget : Operand<i32>;
172 def brtarget : Operand<OtherVT>;
173 def pclabel : Operand<i32>;
176 def ADDRspii : ComplexPattern<i32, 2, "SelectADDRspii", [add, frameindex], []>;
177 def ADDRdpii : ComplexPattern<i32, 2, "SelectADDRdpii", [add, dprelwrapper],
179 def ADDRcpii : ComplexPattern<i32, 2, "SelectADDRcpii", [add, cprelwrapper],
183 def MEMii : Operand<i32> {
184 let PrintMethod = "printMemOperand";
185 let DecoderMethod = "DecodeMEMiiOperand";
186 let MIOperandInfo = (ops i32imm, i32imm);
190 def InlineJT : Operand<i32> {
191 let PrintMethod = "printInlineJT";
194 def InlineJT32 : Operand<i32> {
195 let PrintMethod = "printInlineJT32";
198 //===----------------------------------------------------------------------===//
199 // Instruction Class Templates
200 //===----------------------------------------------------------------------===//
202 // Three operand short
204 multiclass F3R_2RUS<bits<5> opc1, bits<5> opc2, string OpcStr, SDNode OpNode> {
205 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
206 !strconcat(OpcStr, " $dst, $b, $c"),
207 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
208 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
209 !strconcat(OpcStr, " $dst, $b, $c"),
210 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
213 multiclass F3R_2RUS_np<bits<5> opc1, bits<5> opc2, string OpcStr> {
214 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
215 !strconcat(OpcStr, " $dst, $b, $c"), []>;
216 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
217 !strconcat(OpcStr, " $dst, $b, $c"), []>;
220 multiclass F3R_2RBITP<bits<5> opc1, bits<5> opc2, string OpcStr,
222 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
223 !strconcat(OpcStr, " $dst, $b, $c"),
224 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
225 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
226 !strconcat(OpcStr, " $dst, $b, $c"),
227 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
230 class F3R<bits<5> opc, string OpcStr, SDNode OpNode> :
231 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
232 !strconcat(OpcStr, " $dst, $b, $c"),
233 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
235 class F3R_np<bits<5> opc, string OpcStr> :
236 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
237 !strconcat(OpcStr, " $dst, $b, $c"), []>;
238 // Three operand long
240 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
241 multiclass FL3R_L2RUS<bits<9> opc1, bits<9> opc2, string OpcStr,
243 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
244 !strconcat(OpcStr, " $dst, $b, $c"),
245 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
246 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
247 !strconcat(OpcStr, " $dst, $b, $c"),
248 [(set GRRegs:$dst, (OpNode GRRegs:$b, immUs:$c))]>;
251 /// FL3R_L2RUS multiclass - Define a normal FL3R/FL2RUS pattern in one shot.
252 multiclass FL3R_L2RBITP<bits<9> opc1, bits<9> opc2, string OpcStr,
254 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
255 !strconcat(OpcStr, " $dst, $b, $c"),
256 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
257 def _l2rus : _FL2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
258 !strconcat(OpcStr, " $dst, $b, $c"),
259 [(set GRRegs:$dst, (OpNode GRRegs:$b, immBitp:$c))]>;
262 class FL3R<bits<9> opc, string OpcStr, SDNode OpNode> :
263 _FL3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
264 !strconcat(OpcStr, " $dst, $b, $c"),
265 [(set GRRegs:$dst, (OpNode GRRegs:$b, GRRegs:$c))]>;
268 // Operand register - U6
269 multiclass FRU6_LRU6_branch<bits<6> opc, string OpcStr> {
270 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
271 !strconcat(OpcStr, " $a, $b"), []>;
272 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
273 !strconcat(OpcStr, " $a, $b"), []>;
276 multiclass FRU6_LRU6_backwards_branch<bits<6> opc, string OpcStr> {
277 def _ru6: _FRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
278 !strconcat(OpcStr, " $a, -$b"), []>;
279 def _lru6: _FLRU6<opc, (outs), (ins GRRegs:$a, brtarget:$b),
280 !strconcat(OpcStr, " $a, -$b"), []>;
283 multiclass FRU6_LRU6_cp<bits<6> opc, string OpcStr> {
284 def _ru6: _FRU6<opc, (outs RRegs:$a), (ins i32imm:$b),
285 !strconcat(OpcStr, " $a, cp[$b]"), []>;
286 def _lru6: _FLRU6<opc, (outs RRegs:$a), (ins i32imm:$b),
287 !strconcat(OpcStr, " $a, cp[$b]"), []>;
291 multiclass FU6_LU6<bits<10> opc, string OpcStr, SDNode OpNode> {
292 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
293 [(OpNode immU6:$a)]>;
294 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
295 [(OpNode immU16:$a)]>;
298 multiclass FU6_LU6_int<bits<10> opc, string OpcStr, Intrinsic Int> {
299 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
301 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"),
305 multiclass FU6_LU6_np<bits<10> opc, string OpcStr> {
306 def _u6: _FU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
307 def _lu6: _FLU6<opc, (outs), (ins i32imm:$a), !strconcat(OpcStr, " $a"), []>;
312 class F2R_np<bits<6> opc, string OpcStr> :
313 _F2R<opc, (outs GRRegs:$dst), (ins GRRegs:$b),
314 !strconcat(OpcStr, " $dst, $b"), []>;
318 //===----------------------------------------------------------------------===//
319 // Pseudo Instructions
320 //===----------------------------------------------------------------------===//
322 let Defs = [SP], Uses = [SP] in {
323 def ADJCALLSTACKDOWN : PseudoInstXCore<(outs), (ins i32imm:$amt),
324 "# ADJCALLSTACKDOWN $amt",
325 [(callseq_start timm:$amt)]>;
326 def ADJCALLSTACKUP : PseudoInstXCore<(outs), (ins i32imm:$amt1, i32imm:$amt2),
327 "# ADJCALLSTACKUP $amt1",
328 [(callseq_end timm:$amt1, timm:$amt2)]>;
331 def LDWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
332 "# LDWFI $dst, $addr",
333 [(set GRRegs:$dst, (load ADDRspii:$addr))]>;
335 def LDAWFI : PseudoInstXCore<(outs GRRegs:$dst), (ins MEMii:$addr),
336 "# LDAWFI $dst, $addr",
337 [(set GRRegs:$dst, ADDRspii:$addr)]>;
339 def STWFI : PseudoInstXCore<(outs), (ins GRRegs:$src, MEMii:$addr),
340 "# STWFI $src, $addr",
341 [(store GRRegs:$src, ADDRspii:$addr)]>;
343 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
344 // instruction selection into a branch sequence.
345 let usesCustomInserter = 1 in {
346 def SELECT_CC : PseudoInstXCore<(outs GRRegs:$dst),
347 (ins GRRegs:$cond, GRRegs:$T, GRRegs:$F),
348 "# SELECT_CC PSEUDO!",
350 (select GRRegs:$cond, GRRegs:$T, GRRegs:$F))]>;
353 //===----------------------------------------------------------------------===//
355 //===----------------------------------------------------------------------===//
357 // Three operand short
358 defm ADD : F3R_2RUS<0b00010, 0b10010, "add", add>;
359 defm SUB : F3R_2RUS<0b00011, 0b10011, "sub", sub>;
360 let neverHasSideEffects = 1 in {
361 defm EQ : F3R_2RUS_np<0b00110, 0b10110, "eq">;
362 def LSS_3r : F3R_np<0b11000, "lss">;
363 def LSU_3r : F3R_np<0b11001, "lsu">;
365 def AND_3r : F3R<0b00111, "and", and>;
366 def OR_3r : F3R<0b01000, "or", or>;
369 def LDW_3r : _F3R<0b01001, (outs GRRegs:$dst),
370 (ins GRRegs:$addr, GRRegs:$offset),
371 "ldw $dst, $addr[$offset]", []>;
373 def LDW_2rus : _F2RUS<0b00001, (outs GRRegs:$dst),
374 (ins GRRegs:$addr, i32imm:$offset),
375 "ldw $dst, $addr[$offset]", []>;
377 def LD16S_3r : _F3R<0b10000, (outs GRRegs:$dst),
378 (ins GRRegs:$addr, GRRegs:$offset),
379 "ld16s $dst, $addr[$offset]", []>;
381 def LD8U_3r : _F3R<0b10001, (outs GRRegs:$dst),
382 (ins GRRegs:$addr, GRRegs:$offset),
383 "ld8u $dst, $addr[$offset]", []>;
387 def STW_l3r : _FL3R<0b000001100, (outs),
388 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
389 "stw $val, $addr[$offset]", []>;
391 def STW_2rus : _F2RUS<0b0000, (outs),
392 (ins GRRegs:$val, GRRegs:$addr, i32imm:$offset),
393 "stw $val, $addr[$offset]", []>;
396 defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>;
397 defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>;
399 // The first operand is treated as an immediate since it refers to a register
400 // number in another thread.
401 def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c),
402 "set t[$c]:r$a, $b", []>;
404 // Three operand long
405 def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst),
406 (ins GRRegs:$addr, GRRegs:$offset),
407 "ldaw $dst, $addr[$offset]",
409 (ldawf GRRegs:$addr, GRRegs:$offset))]>;
411 let neverHasSideEffects = 1 in
412 def LDAWF_l2rus : _FL2RUS<0b100111100, (outs GRRegs:$dst),
413 (ins GRRegs:$addr, i32imm:$offset),
414 "ldaw $dst, $addr[$offset]", []>;
416 def LDAWB_l3r : _FL3R<0b001001100, (outs GRRegs:$dst),
417 (ins GRRegs:$addr, GRRegs:$offset),
418 "ldaw $dst, $addr[-$offset]",
420 (ldawb GRRegs:$addr, GRRegs:$offset))]>;
422 let neverHasSideEffects = 1 in
423 def LDAWB_l2rus : _FL2RUS<0b101001100, (outs GRRegs:$dst),
424 (ins GRRegs:$addr, i32imm:$offset),
425 "ldaw $dst, $addr[-$offset]", []>;
427 def LDA16F_l3r : _FL3R<0b001011100, (outs GRRegs:$dst),
428 (ins GRRegs:$addr, GRRegs:$offset),
429 "lda16 $dst, $addr[$offset]",
431 (lda16f GRRegs:$addr, GRRegs:$offset))]>;
433 def LDA16B_l3r : _FL3R<0b001101100, (outs GRRegs:$dst),
434 (ins GRRegs:$addr, GRRegs:$offset),
435 "lda16 $dst, $addr[-$offset]",
437 (lda16b GRRegs:$addr, GRRegs:$offset))]>;
439 def MUL_l3r : FL3R<0b001111100, "mul", mul>;
440 // Instructions which may trap are marked as side effecting.
441 let hasSideEffects = 1 in {
442 def DIVS_l3r : FL3R<0b010001100, "divs", sdiv>;
443 def DIVU_l3r : FL3R<0b010011100, "divu", udiv>;
444 def REMS_l3r : FL3R<0b110001100, "rems", srem>;
445 def REMU_l3r : FL3R<0b110011100, "remu", urem>;
447 def XOR_l3r : FL3R<0b000011100, "xor", xor>;
448 defm ASHR : FL3R_L2RBITP<0b000101100, 0b100101100, "ashr", sra>;
450 let Constraints = "$src1 = $dst" in
451 def CRC_l3r : _FL3RSrcDst<0b101011100, (outs GRRegs:$dst),
452 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
453 "crc32 $dst, $src2, $src3",
455 (int_xcore_crc32 GRRegs:$src1, GRRegs:$src2,
459 def ST16_l3r : _FL3R<0b100001100, (outs),
460 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
461 "st16 $val, $addr[$offset]", []>;
463 def ST8_l3r : _FL3R<0b100011100, (outs),
464 (ins GRRegs:$val, GRRegs:$addr, GRRegs:$offset),
465 "st8 $val, $addr[$offset]", []>;
468 def INPW_l2rus : _FL2RUSBitp<0b100101110, (outs GRRegs:$a),
469 (ins GRRegs:$b, i32imm:$c), "inpw $a, res[$b], $c",
472 def OUTPW_l2rus : _FL2RUSBitp<0b100101101, (outs),
473 (ins GRRegs:$a, GRRegs:$b, i32imm:$c),
474 "outpw res[$b], $a, $c", []>;
477 let Constraints = "$e = $a,$f = $b" in {
478 def MACCU_l4r : _FL4RSrcDstSrcDst<
479 0b000001, (outs GRRegs:$a, GRRegs:$b),
480 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccu $a, $b, $c, $d", []>;
482 def MACCS_l4r : _FL4RSrcDstSrcDst<
483 0b000010, (outs GRRegs:$a, GRRegs:$b),
484 (ins GRRegs:$e, GRRegs:$f, GRRegs:$c, GRRegs:$d), "maccs $a, $b, $c, $d", []>;
487 let Constraints = "$e = $b" in
488 def CRC8_l4r : _FL4RSrcDst<0b000000, (outs GRRegs:$a, GRRegs:$b),
489 (ins GRRegs:$e, GRRegs:$c, GRRegs:$d),
490 "crc8 $b, $a, $c, $d", []>;
494 def LADD_l5r : _FL5R<0b000001, (outs GRRegs:$dst1, GRRegs:$dst2),
495 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
496 "ladd $dst2, $dst1, $src1, $src2, $src3",
499 def LSUB_l5r : _FL5R<0b000010, (outs GRRegs:$dst1, GRRegs:$dst2),
500 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
501 "lsub $dst2, $dst1, $src1, $src2, $src3", []>;
503 def LDIVU_l5r : _FL5R<0b000000, (outs GRRegs:$dst1, GRRegs:$dst2),
504 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3),
505 "ldivu $dst1, $dst2, $src3, $src1, $src2", []>;
509 def LMUL_l6r : _FL6R<
510 0b00000, (outs GRRegs:$dst1, GRRegs:$dst2),
511 (ins GRRegs:$src1, GRRegs:$src2, GRRegs:$src3, GRRegs:$src4),
512 "lmul $dst1, $dst2, $src1, $src2, $src3, $src4", []>;
516 //let Uses = [DP] in ...
517 let neverHasSideEffects = 1, isReMaterializable = 1 in
518 def LDAWDP_ru6: _FRU6<0b011000, (outs RRegs:$a), (ins MEMii:$b),
519 "ldaw $a, dp[$b]", []>;
521 let isReMaterializable = 1 in
522 def LDAWDP_lru6: _FLRU6<0b011000, (outs RRegs:$a), (ins MEMii:$b),
524 [(set RRegs:$a, ADDRdpii:$b)]>;
527 def LDWDP_ru6: _FRU6<0b010110, (outs RRegs:$a), (ins MEMii:$b),
528 "ldw $a, dp[$b]", []>;
530 def LDWDP_lru6: _FLRU6<0b010110, (outs RRegs:$a), (ins MEMii:$b),
532 [(set RRegs:$a, (load ADDRdpii:$b))]>;
535 def STWDP_ru6 : _FRU6<0b010100, (outs), (ins RRegs:$a, MEMii:$b),
536 "stw $a, dp[$b]", []>;
538 def STWDP_lru6 : _FLRU6<0b010100, (outs), (ins RRegs:$a, MEMii:$b),
540 [(store RRegs:$a, ADDRdpii:$b)]>;
542 //let Uses = [CP] in ..
543 let mayLoad = 1, isReMaterializable = 1, neverHasSideEffects = 1 in
544 defm LDWCP : FRU6_LRU6_cp<0b011011, "ldw">;
548 def STWSP_ru6 : _FRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b),
550 [(XCoreStwsp RRegs:$a, immU6:$b)]>;
552 def STWSP_lru6 : _FLRU6<0b010101, (outs), (ins RRegs:$a, i32imm:$b),
554 [(XCoreStwsp RRegs:$a, immU16:$b)]>;
558 def LDWSP_ru6 : _FRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b),
559 "ldw $a, sp[$b]", []>;
561 def LDWSP_lru6 : _FLRU6<0b010111, (outs RRegs:$a), (ins i32imm:$b),
562 "ldw $a, sp[$b]", []>;
565 let neverHasSideEffects = 1 in {
566 def LDAWSP_ru6 : _FRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
567 "ldaw $a, sp[$b]", []>;
569 def LDAWSP_lru6 : _FLRU6<0b011001, (outs RRegs:$a), (ins i32imm:$b),
570 "ldaw $a, sp[$b]", []>;
574 let isReMaterializable = 1 in {
575 def LDC_ru6 : _FRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b),
576 "ldc $a, $b", [(set RRegs:$a, immU6:$b)]>;
578 def LDC_lru6 : _FLRU6<0b011010, (outs RRegs:$a), (ins i32imm:$b),
579 "ldc $a, $b", [(set RRegs:$a, immU16:$b)]>;
582 def SETC_ru6 : _FRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
584 [(int_xcore_setc GRRegs:$a, immU6:$b)]>;
586 def SETC_lru6 : _FLRU6<0b111010, (outs), (ins GRRegs:$a, i32imm:$b),
588 [(int_xcore_setc GRRegs:$a, immU16:$b)]>;
590 // Operand register - U6
591 let isBranch = 1, isTerminator = 1 in {
592 defm BRFT: FRU6_LRU6_branch<0b011100, "bt">;
593 defm BRBT: FRU6_LRU6_backwards_branch<0b011101, "bt">;
594 defm BRFF: FRU6_LRU6_branch<0b011110, "bf">;
595 defm BRBF: FRU6_LRU6_backwards_branch<0b011111, "bf">;
599 let Defs = [SP], Uses = [SP] in {
600 let neverHasSideEffects = 1 in
601 defm EXTSP : FU6_LU6_np<0b0111011110, "extsp">;
604 defm ENTSP : FU6_LU6_np<0b0111011101, "entsp">;
606 let isReturn = 1, isTerminator = 1, mayLoad = 1, isBarrier = 1 in {
607 defm RETSP : FU6_LU6<0b0111011111, "retsp", XCoreRetsp>;
611 let neverHasSideEffects = 1 in
612 defm EXTDP : FU6_LU6_np<0b0111001110, "extdp">;
614 let Uses = [R11], isCall=1 in
615 defm BLAT : FU6_LU6_np<0b0111001101, "blat">;
617 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
618 def BRBU_u6 : _FU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>;
620 def BRBU_lu6 : _FLU6<0b0111011100, (outs), (ins brtarget:$a), "bu -$a", []>;
622 def BRFU_u6 : _FU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
624 def BRFU_lu6 : _FLU6<0b0111001100, (outs), (ins brtarget:$a), "bu $a", []>;
627 //let Uses = [CP] in ...
628 let Defs = [R11], neverHasSideEffects = 1, isReMaterializable = 1 in
629 def LDAWCP_u6: _FU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]",
632 let Defs = [R11], isReMaterializable = 1 in
633 def LDAWCP_lu6: _FLU6<0b0111111101, (outs), (ins MEMii:$a), "ldaw r11, cp[$a]",
634 [(set R11, ADDRcpii:$a)]>;
637 defm GETSR : FU6_LU6_np<0b0111111100, "getsr r11,">;
639 defm SETSR : FU6_LU6_int<0b0111101101, "setsr", int_xcore_setsr>;
641 defm CLRSR : FU6_LU6_int<0b0111101100, "clrsr", int_xcore_clrsr>;
643 // setsr may cause a branch if it is used to enable events. clrsr may
644 // branch if it is executed while events are enabled.
645 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
646 isCodeGenOnly = 1 in {
647 defm SETSR_branch : FU6_LU6_np<0b0111101101, "setsr">;
648 defm CLRSR_branch : FU6_LU6_np<0b0111101100, "clrsr">;
651 defm KCALL : FU6_LU6_np<0b0111001111, "kcall">;
653 let Uses = [SP], Defs = [SP], mayStore = 1 in
654 defm KENTSP : FU6_LU6_np<0b0111101110, "kentsp">;
656 let Uses = [SP], Defs = [SP], mayLoad = 1 in
657 defm KRESTSP : FU6_LU6_np<0b0111101111, "krestsp">;
661 let Defs = [R11], isReMaterializable = 1, neverHasSideEffects = 1 in
662 def LDAPF_u10 : _FU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a", []>;
664 let Defs = [R11], isReMaterializable = 1 in
665 def LDAPF_lu10 : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a",
666 [(set R11, (pcrelwrapper tglobaladdr:$a))]>;
668 let Defs = [R11], isReMaterializable = 1, isCodeGenOnly = 1 in
669 def LDAPF_lu10_ba : _FLU10<0b110110, (outs), (ins i32imm:$a), "ldap r11, $a",
670 [(set R11, (pcrelwrapper tblockaddress:$a))]>;
673 // All calls clobber the link register and the non-callee-saved registers:
674 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
675 def BLACP_u10 : _FU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>;
677 def BLACP_lu10 : _FLU10<0b111000, (outs), (ins i32imm:$a), "bla cp[$a]", []>;
679 def BLRF_u10 : _FU10<0b110100, (outs), (ins calltarget:$a), "bl $a",
680 [(XCoreBranchLink immU10:$a)]>;
682 def BLRF_lu10 : _FLU10<0b110100, (outs), (ins calltarget:$a), "bl $a",
683 [(XCoreBranchLink immU20:$a)]>;
686 let Defs = [R11], mayLoad = 1, isReMaterializable = 1,
687 neverHasSideEffects = 1 in {
688 def LDWCP_u10 : _FU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]", []>;
690 def LDWCP_lu10 : _FLU10<0b111001, (outs), (ins i32imm:$a), "ldw r11, cp[$a]",
695 def NOT : _F2R<0b100010, (outs GRRegs:$dst), (ins GRRegs:$b),
696 "not $dst, $b", [(set GRRegs:$dst, (not GRRegs:$b))]>;
698 def NEG : _F2R<0b100100, (outs GRRegs:$dst), (ins GRRegs:$b),
699 "neg $dst, $b", [(set GRRegs:$dst, (ineg GRRegs:$b))]>;
701 let Constraints = "$src1 = $dst" in {
703 _FRUSSrcDstBitp<0b001101, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
705 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1,
709 _F2RSrcDst<0b001100, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
711 [(set GRRegs:$dst, (int_xcore_sext GRRegs:$src1, GRRegs:$src2))]>;
714 _FRUSSrcDstBitp<0b010001, (outs GRRegs:$dst), (ins GRRegs:$src1, i32imm:$src2),
716 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1,
720 _F2RSrcDst<0b010000, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
722 [(set GRRegs:$dst, (int_xcore_zext GRRegs:$src1, GRRegs:$src2))]>;
725 _F2RSrcDst<0b001010, (outs GRRegs:$dst), (ins GRRegs:$src1, GRRegs:$src2),
726 "andnot $dst, $src2",
727 [(set GRRegs:$dst, (and GRRegs:$src1, (not GRRegs:$src2)))]>;
730 let isReMaterializable = 1, neverHasSideEffects = 1 in
731 def MKMSK_rus : _FRUSBitp<0b101001, (outs GRRegs:$dst), (ins i32imm:$size),
732 "mkmsk $dst, $size", []>;
734 def MKMSK_2r : _F2R<0b101000, (outs GRRegs:$dst), (ins GRRegs:$size),
736 [(set GRRegs:$dst, (add (shl 1, GRRegs:$size), -1))]>;
738 def GETR_rus : _FRUS<0b100000, (outs GRRegs:$dst), (ins i32imm:$type),
740 [(set GRRegs:$dst, (int_xcore_getr immUs:$type))]>;
742 def GETTS_2r : _F2R<0b001110, (outs GRRegs:$dst), (ins GRRegs:$r),
743 "getts $dst, res[$r]",
744 [(set GRRegs:$dst, (int_xcore_getts GRRegs:$r))]>;
746 def SETPT_2r : _FR2R<0b001111, (outs), (ins GRRegs:$r, GRRegs:$val),
747 "setpt res[$r], $val",
748 [(int_xcore_setpt GRRegs:$r, GRRegs:$val)]>;
750 def OUTCT_2r : _F2R<0b010010, (outs), (ins GRRegs:$r, GRRegs:$val),
751 "outct res[$r], $val",
752 [(int_xcore_outct GRRegs:$r, GRRegs:$val)]>;
754 def OUTCT_rus : _FRUS<0b010011, (outs), (ins GRRegs:$r, i32imm:$val),
755 "outct res[$r], $val",
756 [(int_xcore_outct GRRegs:$r, immUs:$val)]>;
758 def OUTT_2r : _FR2R<0b000011, (outs), (ins GRRegs:$r, GRRegs:$val),
759 "outt res[$r], $val",
760 [(int_xcore_outt GRRegs:$r, GRRegs:$val)]>;
762 def OUT_2r : _FR2R<0b101010, (outs), (ins GRRegs:$r, GRRegs:$val),
764 [(int_xcore_out GRRegs:$r, GRRegs:$val)]>;
766 let Constraints = "$src = $dst" in
768 _F2RSrcDst<0b101011, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
769 "outshr res[$r], $src",
770 [(set GRRegs:$dst, (int_xcore_outshr GRRegs:$r, GRRegs:$src))]>;
772 def INCT_2r : _F2R<0b100001, (outs GRRegs:$dst), (ins GRRegs:$r),
773 "inct $dst, res[$r]",
774 [(set GRRegs:$dst, (int_xcore_inct GRRegs:$r))]>;
776 def INT_2r : _F2R<0b100011, (outs GRRegs:$dst), (ins GRRegs:$r),
778 [(set GRRegs:$dst, (int_xcore_int GRRegs:$r))]>;
780 def IN_2r : _F2R<0b101100, (outs GRRegs:$dst), (ins GRRegs:$r),
782 [(set GRRegs:$dst, (int_xcore_in GRRegs:$r))]>;
784 let Constraints = "$src = $dst" in
786 _F2RSrcDst<0b101101, (outs GRRegs:$dst), (ins GRRegs:$src, GRRegs:$r),
787 "inshr $dst, res[$r]",
788 [(set GRRegs:$dst, (int_xcore_inshr GRRegs:$r, GRRegs:$src))]>;
790 def CHKCT_2r : _F2R<0b110010, (outs), (ins GRRegs:$r, GRRegs:$val),
791 "chkct res[$r], $val",
792 [(int_xcore_chkct GRRegs:$r, GRRegs:$val)]>;
794 def CHKCT_rus : _FRUSBitp<0b110011, (outs), (ins GRRegs:$r, i32imm:$val),
795 "chkct res[$r], $val",
796 [(int_xcore_chkct GRRegs:$r, immUs:$val)]>;
798 def TESTCT_2r : _F2R<0b101111, (outs GRRegs:$dst), (ins GRRegs:$src),
799 "testct $dst, res[$src]",
800 [(set GRRegs:$dst, (int_xcore_testct GRRegs:$src))]>;
802 def TESTWCT_2r : _F2R<0b110001, (outs GRRegs:$dst), (ins GRRegs:$src),
803 "testwct $dst, res[$src]",
804 [(set GRRegs:$dst, (int_xcore_testwct GRRegs:$src))]>;
806 def SETD_2r : _FR2R<0b000101, (outs), (ins GRRegs:$r, GRRegs:$val),
807 "setd res[$r], $val",
808 [(int_xcore_setd GRRegs:$r, GRRegs:$val)]>;
810 def SETPSC_2r : _FR2R<0b110000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
811 "setpsc res[$src1], $src2",
812 [(int_xcore_setpsc GRRegs:$src1, GRRegs:$src2)]>;
814 def GETST_2r : _F2R<0b000001, (outs GRRegs:$dst), (ins GRRegs:$r),
815 "getst $dst, res[$r]",
816 [(set GRRegs:$dst, (int_xcore_getst GRRegs:$r))]>;
818 def INITSP_2r : _F2R<0b000100, (outs), (ins GRRegs:$src, GRRegs:$t),
819 "init t[$t]:sp, $src",
820 [(int_xcore_initsp GRRegs:$t, GRRegs:$src)]>;
822 def INITPC_2r : _F2R<0b000000, (outs), (ins GRRegs:$src, GRRegs:$t),
823 "init t[$t]:pc, $src",
824 [(int_xcore_initpc GRRegs:$t, GRRegs:$src)]>;
826 def INITCP_2r : _F2R<0b000110, (outs), (ins GRRegs:$src, GRRegs:$t),
827 "init t[$t]:cp, $src",
828 [(int_xcore_initcp GRRegs:$t, GRRegs:$src)]>;
830 def INITDP_2r : _F2R<0b000010, (outs), (ins GRRegs:$src, GRRegs:$t),
831 "init t[$t]:dp, $src",
832 [(int_xcore_initdp GRRegs:$t, GRRegs:$src)]>;
834 def PEEK_2r : _F2R<0b101110, (outs GRRegs:$dst), (ins GRRegs:$src),
835 "peek $dst, res[$src]",
836 [(set GRRegs:$dst, (int_xcore_peek GRRegs:$src))]>;
838 def ENDIN_2r : _F2R<0b100101, (outs GRRegs:$dst), (ins GRRegs:$src),
839 "endin $dst, res[$src]",
840 [(set GRRegs:$dst, (int_xcore_endin GRRegs:$src))]>;
842 def EEF_2r : _F2R<0b001011, (outs), (ins GRRegs:$a, GRRegs:$b),
843 "eef $a, res[$b]", []>;
845 def EET_2r : _F2R<0b001001, (outs), (ins GRRegs:$a, GRRegs:$b),
846 "eet $a, res[$b]", []>;
848 def TSETMR_2r : _F2RImm<0b000111, (outs), (ins i32imm:$a, GRRegs:$b),
849 "tsetmr r$a, $b", []>;
852 def BITREV_l2r : _FL2R<0b0000011000, (outs GRRegs:$dst), (ins GRRegs:$src),
854 [(set GRRegs:$dst, (int_xcore_bitrev GRRegs:$src))]>;
856 def BYTEREV_l2r : _FL2R<0b0000011001, (outs GRRegs:$dst), (ins GRRegs:$src),
857 "byterev $dst, $src",
858 [(set GRRegs:$dst, (bswap GRRegs:$src))]>;
860 def CLZ_l2r : _FL2R<0b000111000, (outs GRRegs:$dst), (ins GRRegs:$src),
862 [(set GRRegs:$dst, (ctlz GRRegs:$src))]>;
864 def GETD_l2r : _FL2R<0b0001111001, (outs GRRegs:$dst), (ins GRRegs:$src),
865 "getd $dst, res[$src]", []>;
867 def GETN_l2r : _FL2R<0b0011011001, (outs GRRegs:$dst), (ins GRRegs:$src),
868 "getn $dst, res[$src]", []>;
870 def SETC_l2r : _FL2R<0b0010111001, (outs), (ins GRRegs:$r, GRRegs:$val),
871 "setc res[$r], $val",
872 [(int_xcore_setc GRRegs:$r, GRRegs:$val)]>;
874 def SETTW_l2r : _FLR2R<0b0010011001, (outs), (ins GRRegs:$r, GRRegs:$val),
875 "settw res[$r], $val",
876 [(int_xcore_settw GRRegs:$r, GRRegs:$val)]>;
878 def GETPS_l2r : _FL2R<0b0001011001, (outs GRRegs:$dst), (ins GRRegs:$src),
879 "get $dst, ps[$src]",
880 [(set GRRegs:$dst, (int_xcore_getps GRRegs:$src))]>;
882 def SETPS_l2r : _FLR2R<0b0001111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
883 "set ps[$src1], $src2",
884 [(int_xcore_setps GRRegs:$src1, GRRegs:$src2)]>;
886 def INITLR_l2r : _FL2R<0b0001011000, (outs), (ins GRRegs:$src, GRRegs:$t),
887 "init t[$t]:lr, $src",
888 [(int_xcore_initlr GRRegs:$t, GRRegs:$src)]>;
890 def SETCLK_l2r : _FLR2R<0b0000111001, (outs), (ins GRRegs:$src1, GRRegs:$src2),
891 "setclk res[$src1], $src2",
892 [(int_xcore_setclk GRRegs:$src1, GRRegs:$src2)]>;
894 def SETN_l2r : _FLR2R<0b0011011000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
895 "setn res[$src1], $src2", []>;
897 def SETRDY_l2r : _FLR2R<0b0010111000, (outs), (ins GRRegs:$src1, GRRegs:$src2),
898 "setrdy res[$src1], $src2",
899 [(int_xcore_setrdy GRRegs:$src1, GRRegs:$src2)]>;
901 def TESTLCL_l2r : _FL2R<0b0010011000, (outs GRRegs:$dst), (ins GRRegs:$src),
902 "testlcl $dst, res[$src]", []>;
905 def MSYNC_1r : _F1R<0b000111, (outs), (ins GRRegs:$a),
907 [(int_xcore_msync GRRegs:$a)]>;
908 def MJOIN_1r : _F1R<0b000101, (outs), (ins GRRegs:$a),
910 [(int_xcore_mjoin GRRegs:$a)]>;
912 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
913 def BAU_1r : _F1R<0b001001, (outs), (ins GRRegs:$a),
915 [(brind GRRegs:$a)]>;
917 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
918 def BR_JT : PseudoInstXCore<(outs), (ins InlineJT:$t, GRRegs:$i),
920 [(XCoreBR_JT tjumptable:$t, GRRegs:$i)]>;
922 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1 in
923 def BR_JT32 : PseudoInstXCore<(outs), (ins InlineJT32:$t, GRRegs:$i),
925 [(XCoreBR_JT32 tjumptable:$t, GRRegs:$i)]>;
927 let Defs=[SP], neverHasSideEffects=1 in
928 def SETSP_1r : _F1R<0b001011, (outs), (ins GRRegs:$a), "set sp, $a", []>;
930 let neverHasSideEffects=1 in
931 def SETDP_1r : _F1R<0b001100, (outs), (ins GRRegs:$a), "set dp, $a", []>;
933 let neverHasSideEffects=1 in
934 def SETCP_1r : _F1R<0b001101, (outs), (ins GRRegs:$a), "set cp, $a", []>;
936 let hasCtrlDep = 1 in
937 def ECALLT_1r : _F1R<0b010011, (outs), (ins GRRegs:$a),
941 let hasCtrlDep = 1 in
942 def ECALLF_1r : _F1R<0b010010, (outs), (ins GRRegs:$a),
947 // All calls clobber the link register and the non-callee-saved registers:
948 Defs = [R0, R1, R2, R3, R11, LR], Uses = [SP] in {
949 def BLA_1r : _F1R<0b001000, (outs), (ins GRRegs:$a),
951 [(XCoreBranchLink GRRegs:$a)]>;
954 def SYNCR_1r : _F1R<0b100001, (outs), (ins GRRegs:$a),
956 [(int_xcore_syncr GRRegs:$a)]>;
958 def FREER_1r : _F1R<0b000100, (outs), (ins GRRegs:$a),
960 [(int_xcore_freer GRRegs:$a)]>;
963 def SETV_1r : _F1R<0b010001, (outs), (ins GRRegs:$a),
965 [(int_xcore_setv GRRegs:$a, R11)]>;
967 def SETEV_1r : _F1R<0b001111, (outs), (ins GRRegs:$a),
968 "setev res[$a], r11",
969 [(int_xcore_setev GRRegs:$a, R11)]>;
972 def DGETREG_1r : _F1R<0b001110, (outs GRRegs:$a), (ins), "dgetreg $a", []>;
974 def EDU_1r : _F1R<0b000000, (outs), (ins GRRegs:$a), "edu res[$a]", []>;
976 def EEU_1r : _F1R<0b000001, (outs), (ins GRRegs:$a),
978 [(int_xcore_eeu GRRegs:$a)]>;
980 def KCALL_1r : _F1R<0b010000, (outs), (ins GRRegs:$a), "kcall $a", []>;
982 def WAITEF_1R : _F1R<0b000011, (outs), (ins GRRegs:$a), "waitef $a", []>;
984 def WAITET_1R : _F1R<0b000010, (outs), (ins GRRegs:$a), "waitet $a", []>;
986 def TSTART_1R : _F1R<0b000110, (outs), (ins GRRegs:$a), "start t[$a]", []>;
988 def CLRPT_1R : _F1R<0b100000, (outs), (ins GRRegs:$a), "clrpt res[$a]", []>;
990 // Zero operand short
992 def CLRE_0R : _F0R<0b0000001101, (outs), (ins), "clre", [(int_xcore_clre)]>;
994 def DCALL_0R : _F0R<0b0000011100, (outs), (ins), "dcall", []>;
996 let Defs = [SP], Uses = [SP] in
997 def DENTSP_0R : _F0R<0b0001001100, (outs), (ins), "dentsp", []>;
1000 def DRESTSP_0R : _F0R<0b0001001101, (outs), (ins), "drestsp", []>;
1002 def DRET_0R : _F0R<0b0000011110, (outs), (ins), "dret", []>;
1004 def FREET_0R : _F0R<0b0000001111, (outs), (ins), "freet", []>;
1006 let Defs = [R11] in {
1007 def GETID_0R : _F0R<0b0001001110, (outs), (ins),
1009 [(set R11, (int_xcore_getid))]>;
1011 def GETED_0R : _F0R<0b0000111110, (outs), (ins),
1013 [(set R11, (int_xcore_geted))]>;
1015 def GETET_0R : _F0R<0b0000111111, (outs), (ins),
1017 [(set R11, (int_xcore_getet))]>;
1019 def GETKEP_0R : _F0R<0b0001001111, (outs), (ins),
1020 "get r11, kep", []>;
1022 def GETKSP_0R : _F0R<0b0001011100, (outs), (ins),
1023 "get r11, ksp", []>;
1027 def KRET_0R : _F0R<0b0000011101, (outs), (ins), "kret", []>;
1029 let Uses = [SP], mayLoad = 1 in {
1030 def LDET_0R : _F0R<0b0001011110, (outs), (ins), "ldw et, sp[4]", []>;
1032 def LDSED_0R : _F0R<0b0001011101, (outs), (ins), "ldw sed, sp[3]", []>;
1034 def LDSPC_0R : _F0R<0b0000101100, (outs), (ins), "ldw spc, sp[1]", []>;
1036 def LDSSR_0R : _F0R<0b0000101110, (outs), (ins), "ldw ssr, sp[2]", []>;
1040 def SETKEP_0R : _F0R<0b0000011111, (outs), (ins), "set kep, r11", []>;
1042 def SSYNC_0r : _F0R<0b0000001110, (outs), (ins),
1044 [(int_xcore_ssync)]>;
1046 let Uses = [SP], mayStore = 1 in {
1047 def STET_0R : _F0R<0b0000111101, (outs), (ins), "stw et, sp[4]", []>;
1049 def STSED_0R : _F0R<0b0000111100, (outs), (ins), "stw sed, sp[3]", []>;
1051 def STSPC_0R : _F0R<0b0000101101, (outs), (ins), "stw spc, sp[1]", []>;
1053 def STSSR_0R : _F0R<0b0000101111, (outs), (ins), "stw ssr, sp[2]", []>;
1056 let isBranch=1, isIndirectBranch=1, isTerminator=1, isBarrier = 1,
1057 hasSideEffects = 1 in
1058 def WAITEU_0R : _F0R<0b0000001100, (outs), (ins),
1060 [(brind (int_xcore_waitevent))]>;
1062 //===----------------------------------------------------------------------===//
1063 // Non-Instruction Patterns
1064 //===----------------------------------------------------------------------===//
1066 def : Pat<(XCoreBranchLink tglobaladdr:$addr), (BLRF_lu10 tglobaladdr:$addr)>;
1067 def : Pat<(XCoreBranchLink texternalsym:$addr), (BLRF_lu10 texternalsym:$addr)>;
1070 def : Pat<(sext_inreg GRRegs:$b, i1), (SEXT_rus GRRegs:$b, 1)>;
1071 def : Pat<(sext_inreg GRRegs:$b, i8), (SEXT_rus GRRegs:$b, 8)>;
1072 def : Pat<(sext_inreg GRRegs:$b, i16), (SEXT_rus GRRegs:$b, 16)>;
1075 def : Pat<(zextloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1076 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1077 def : Pat<(zextloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1079 def : Pat<(sextloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1080 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1081 def : Pat<(sextloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1083 def : Pat<(load (ldawf GRRegs:$addr, GRRegs:$offset)),
1084 (LDW_3r GRRegs:$addr, GRRegs:$offset)>;
1085 def : Pat<(load (add GRRegs:$addr, immUs4:$offset)),
1086 (LDW_2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1087 def : Pat<(load GRRegs:$addr), (LDW_2rus GRRegs:$addr, 0)>;
1090 def : Pat<(extloadi8 (add GRRegs:$addr, GRRegs:$offset)),
1091 (LD8U_3r GRRegs:$addr, GRRegs:$offset)>;
1092 def : Pat<(extloadi8 GRRegs:$addr), (LD8U_3r GRRegs:$addr, (LDC_ru6 0))>;
1093 def : Pat<(extloadi16 (lda16f GRRegs:$addr, GRRegs:$offset)),
1094 (LD16S_3r GRRegs:$addr, GRRegs:$offset)>;
1095 def : Pat<(extloadi16 GRRegs:$addr), (LD16S_3r GRRegs:$addr, (LDC_ru6 0))>;
1098 def : Pat<(truncstorei8 GRRegs:$val, (add GRRegs:$addr, GRRegs:$offset)),
1099 (ST8_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1100 def : Pat<(truncstorei8 GRRegs:$val, GRRegs:$addr),
1101 (ST8_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1103 def : Pat<(truncstorei16 GRRegs:$val, (lda16f GRRegs:$addr, GRRegs:$offset)),
1104 (ST16_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1105 def : Pat<(truncstorei16 GRRegs:$val, GRRegs:$addr),
1106 (ST16_l3r GRRegs:$val, GRRegs:$addr, (LDC_ru6 0))>;
1108 def : Pat<(store GRRegs:$val, (ldawf GRRegs:$addr, GRRegs:$offset)),
1109 (STW_l3r GRRegs:$val, GRRegs:$addr, GRRegs:$offset)>;
1110 def : Pat<(store GRRegs:$val, (add GRRegs:$addr, immUs4:$offset)),
1111 (STW_2rus GRRegs:$val, GRRegs:$addr, (div4_xform immUs4:$offset))>;
1112 def : Pat<(store GRRegs:$val, GRRegs:$addr),
1113 (STW_2rus GRRegs:$val, GRRegs:$addr, 0)>;
1116 def : Pat<(cttz GRRegs:$src), (CLZ_l2r (BITREV_l2r GRRegs:$src))>;
1119 def : Pat<(trap), (ECALLF_1r (LDC_ru6 0))>;
1125 // unconditional branch
1126 def : Pat<(br bb:$addr), (BRFU_lu6 bb:$addr)>;
1128 // direct match equal/notequal zero brcond
1129 def : Pat<(brcond (setne GRRegs:$lhs, 0), bb:$dst),
1130 (BRFT_lru6 GRRegs:$lhs, bb:$dst)>;
1131 def : Pat<(brcond (seteq GRRegs:$lhs, 0), bb:$dst),
1132 (BRFF_lru6 GRRegs:$lhs, bb:$dst)>;
1134 def : Pat<(brcond (setle GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1135 (BRFF_lru6 (LSS_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1136 def : Pat<(brcond (setule GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1137 (BRFF_lru6 (LSU_3r GRRegs:$rhs, GRRegs:$lhs), bb:$dst)>;
1138 def : Pat<(brcond (setge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1139 (BRFF_lru6 (LSS_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1140 def : Pat<(brcond (setuge GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1141 (BRFF_lru6 (LSU_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1142 def : Pat<(brcond (setne GRRegs:$lhs, GRRegs:$rhs), bb:$dst),
1143 (BRFF_lru6 (EQ_3r GRRegs:$lhs, GRRegs:$rhs), bb:$dst)>;
1144 def : Pat<(brcond (setne GRRegs:$lhs, immUs:$rhs), bb:$dst),
1145 (BRFF_lru6 (EQ_2rus GRRegs:$lhs, immUs:$rhs), bb:$dst)>;
1147 // generic brcond pattern
1148 def : Pat<(brcond GRRegs:$cond, bb:$addr), (BRFT_lru6 GRRegs:$cond, bb:$addr)>;
1155 // direct match equal/notequal zero select
1156 def : Pat<(select (setne GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1157 (SELECT_CC GRRegs:$lhs, GRRegs:$T, GRRegs:$F)>;
1159 def : Pat<(select (seteq GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1160 (SELECT_CC GRRegs:$lhs, GRRegs:$F, GRRegs:$T)>;
1162 def : Pat<(select (setle GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1163 (SELECT_CC (LSS_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1164 def : Pat<(select (setule GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1165 (SELECT_CC (LSU_3r GRRegs:$rhs, GRRegs:$lhs), GRRegs:$F, GRRegs:$T)>;
1166 def : Pat<(select (setge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1167 (SELECT_CC (LSS_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1168 def : Pat<(select (setuge GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1169 (SELECT_CC (LSU_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1170 def : Pat<(select (setne GRRegs:$lhs, GRRegs:$rhs), GRRegs:$T, GRRegs:$F),
1171 (SELECT_CC (EQ_3r GRRegs:$lhs, GRRegs:$rhs), GRRegs:$F, GRRegs:$T)>;
1172 def : Pat<(select (setne GRRegs:$lhs, immUs:$rhs), GRRegs:$T, GRRegs:$F),
1173 (SELECT_CC (EQ_2rus GRRegs:$lhs, immUs:$rhs), GRRegs:$F, GRRegs:$T)>;
1176 /// setcc patterns, only matched when none of the above brcond
1180 // setcc 2 register operands
1181 def : Pat<(setle GRRegs:$lhs, GRRegs:$rhs),
1182 (EQ_2rus (LSS_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1183 def : Pat<(setule GRRegs:$lhs, GRRegs:$rhs),
1184 (EQ_2rus (LSU_3r GRRegs:$rhs, GRRegs:$lhs), 0)>;
1186 def : Pat<(setgt GRRegs:$lhs, GRRegs:$rhs),
1187 (LSS_3r GRRegs:$rhs, GRRegs:$lhs)>;
1188 def : Pat<(setugt GRRegs:$lhs, GRRegs:$rhs),
1189 (LSU_3r GRRegs:$rhs, GRRegs:$lhs)>;
1191 def : Pat<(setge GRRegs:$lhs, GRRegs:$rhs),
1192 (EQ_2rus (LSS_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1193 def : Pat<(setuge GRRegs:$lhs, GRRegs:$rhs),
1194 (EQ_2rus (LSU_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1196 def : Pat<(setlt GRRegs:$lhs, GRRegs:$rhs),
1197 (LSS_3r GRRegs:$lhs, GRRegs:$rhs)>;
1198 def : Pat<(setult GRRegs:$lhs, GRRegs:$rhs),
1199 (LSU_3r GRRegs:$lhs, GRRegs:$rhs)>;
1201 def : Pat<(setne GRRegs:$lhs, GRRegs:$rhs),
1202 (EQ_2rus (EQ_3r GRRegs:$lhs, GRRegs:$rhs), 0)>;
1204 def : Pat<(seteq GRRegs:$lhs, GRRegs:$rhs),
1205 (EQ_3r GRRegs:$lhs, GRRegs:$rhs)>;
1207 // setcc reg/imm operands
1208 def : Pat<(seteq GRRegs:$lhs, immUs:$rhs),
1209 (EQ_2rus GRRegs:$lhs, immUs:$rhs)>;
1210 def : Pat<(setne GRRegs:$lhs, immUs:$rhs),
1211 (EQ_2rus (EQ_2rus GRRegs:$lhs, immUs:$rhs), 0)>;
1214 def : Pat<(add GRRegs:$addr, immUs4:$offset),
1215 (LDAWF_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1217 def : Pat<(sub GRRegs:$addr, immUs4:$offset),
1218 (LDAWB_l2rus GRRegs:$addr, (div4_xform immUs4:$offset))>;
1220 def : Pat<(and GRRegs:$val, immMskBitp:$mask),
1221 (ZEXT_rus GRRegs:$val, (msksize_xform immMskBitp:$mask))>;
1223 // (sub X, imm) gets canonicalized to (add X, -imm). Match this form.
1224 def : Pat<(add GRRegs:$src1, immUsNeg:$src2),
1225 (SUB_2rus GRRegs:$src1, (neg_xform immUsNeg:$src2))>;
1227 def : Pat<(add GRRegs:$src1, immUs4Neg:$src2),
1228 (LDAWB_l2rus GRRegs:$src1, (div4neg_xform immUs4Neg:$src2))>;
1234 def : Pat<(mul GRRegs:$src, 3),
1235 (LDA16F_l3r GRRegs:$src, GRRegs:$src)>;
1237 def : Pat<(mul GRRegs:$src, 5),
1238 (LDAWF_l3r GRRegs:$src, GRRegs:$src)>;
1240 def : Pat<(mul GRRegs:$src, -3),
1241 (LDAWB_l3r GRRegs:$src, GRRegs:$src)>;
1243 // ashr X, 32 is equivalent to ashr X, 31 on the XCore.
1244 def : Pat<(sra GRRegs:$src, 31),
1245 (ASHR_l2rus GRRegs:$src, 32)>;
1247 def : Pat<(brcond (setlt GRRegs:$lhs, 0), bb:$dst),
1248 (BRFT_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1250 // setge X, 0 is canonicalized to setgt X, -1
1251 def : Pat<(brcond (setgt GRRegs:$lhs, -1), bb:$dst),
1252 (BRFF_lru6 (ASHR_l2rus GRRegs:$lhs, 32), bb:$dst)>;
1254 def : Pat<(select (setlt GRRegs:$lhs, 0), GRRegs:$T, GRRegs:$F),
1255 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$T, GRRegs:$F)>;
1257 def : Pat<(select (setgt GRRegs:$lhs, -1), GRRegs:$T, GRRegs:$F),
1258 (SELECT_CC (ASHR_l2rus GRRegs:$lhs, 32), GRRegs:$F, GRRegs:$T)>;
1260 def : Pat<(setgt GRRegs:$lhs, -1),
1261 (EQ_2rus (ASHR_l2rus GRRegs:$lhs, 32), 0)>;
1263 def : Pat<(sra (shl GRRegs:$src, immBpwSubBitp:$imm), immBpwSubBitp:$imm),
1264 (SEXT_rus GRRegs:$src, (bpwsub_xform immBpwSubBitp:$imm))>;