lib/Target/XCore/XCoreISelLowering.h

   1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that XCore uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef XCOREISELLOWERING_H
  16 #define XCOREISELLOWERING_H
  17
  18 #include "llvm/CodeGen/SelectionDAG.h"
  19 #include "llvm/Target/TargetLowering.h"
  20 #include "XCore.h"
  21
  22 namespace llvm {
  23
  24   // Forward delcarations
  25   class XCoreSubtarget;
  26   class XCoreTargetMachine;
  27
  28   namespace XCoreISD {
  29     enum NodeType {
  30       // Start the numbering where the builtin ops and target ops leave off.
  31       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  32
  33       // Branch and link (call)
  34       BL,
  35
  36       // pc relative address
  37       PCRelativeWrapper,
  38
  39       // dp relative address
  40       DPRelativeWrapper,
  41
  42       // cp relative address
  43       CPRelativeWrapper,
  44
  45       // Store word to stack
  46       STWSP,
  47
  48       // Corresponds to retsp instruction
  49       RETSP,
  50
  51       // Corresponds to LADD instruction
  52       LADD,
  53
  54       // Corresponds to LSUB instruction
  55       LSUB,
  56
  57       // Corresponds to MACCU instruction
  58       MACCU,
  59
  60       // Corresponds to MACCS instruction
  61       MACCS,
  62
  63       // Jumptable branch.
  64       BR_JT,
  65
  66       // Jumptable branch using long branches for each entry.
  67       BR_JT32
  68     };
  69   }
  70
  71   //===--------------------------------------------------------------------===//
  72   // TargetLowering Implementation
  73   //===--------------------------------------------------------------------===//
  74   class XCoreTargetLowering : public TargetLowering
  75   {
  76   public:
  77
  78     explicit XCoreTargetLowering(XCoreTargetMachine &TM);
  79
  80     /// LowerOperation - Provide custom lowering hooks for some operations.
  81     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
  82
  83     /// ReplaceNodeResults - Replace the results of node with an illegal result
  84     /// type with new values built out of custom code.
  85     ///
  86     virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
  87                                     SelectionDAG &DAG);
  88
  89     /// getTargetNodeName - This method returns the name of a target specific
  90     //  DAG node.
  91     virtual const char *getTargetNodeName(unsigned Opcode) const;
  92
  93     virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
  94                                                          MachineBasicBlock *MBB,
  95                     DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
  96
  97     virtual bool isLegalAddressingMode(const AddrMode &AM,
  98                                        const Type *Ty) const;
  99
 100     /// getFunctionAlignment - Return the Log2 alignment of this function.
 101     virtual unsigned getFunctionAlignment(const Function *F) const;
 102
 103   private:
 104     const XCoreTargetMachine &TM;
 105     const XCoreSubtarget &Subtarget;
 106
 107     // Lower Operand helpers
 108     SDValue LowerCCCArguments(SDValue Chain,
 109                               CallingConv::ID CallConv,
 110                               bool isVarArg,
 111                               const SmallVectorImpl<ISD::InputArg> &Ins,
 112                               DebugLoc dl, SelectionDAG &DAG,
 113                               SmallVectorImpl<SDValue> &InVals);
 114     SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
 115                            CallingConv::ID CallConv, bool isVarArg,
 116                            bool isTailCall,
 117                            const SmallVectorImpl<ISD::OutputArg> &Outs,
 118                            const SmallVectorImpl<ISD::InputArg> &Ins,
 119                            DebugLoc dl, SelectionDAG &DAG,
 120                            SmallVectorImpl<SDValue> &InVals);
 121     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 122                             CallingConv::ID CallConv, bool isVarArg,
 123                             const SmallVectorImpl<ISD::InputArg> &Ins,
 124                             DebugLoc dl, SelectionDAG &DAG,
 125                             SmallVectorImpl<SDValue> &InVals);
 126     SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
 127     SDValue getGlobalAddressWrapper(SDValue GA, GlobalValue *GV,
 128                                     SelectionDAG &DAG);
 129
 130     // Lower Operand specifics
 131     SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG);
 132     SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG);
 133     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
 134     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
 135     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);
 136     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
 137     SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
 138     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
 139     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG);
 140     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG);
 141     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
 142
 143     // Inline asm support
 144     std::vector<unsigned>
 145     getRegClassForInlineAsmConstraint(const std::string &Constraint,
 146               EVT VT) const;
 147
 148     // Expand specifics
 149     SDValue TryExpandADDSUBWithMul(SDNode *Op, SelectionDAG &DAG);
 150     SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG);
 151
 152     virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 153
 154     virtual void computeMaskedBitsForTargetNode(const SDValue Op,
 155                                                 const APInt &Mask,
 156                                                 APInt &KnownZero,
 157                                                 APInt &KnownOne,
 158                                                 const SelectionDAG &DAG,
 159                                                 unsigned Depth = 0) const;
 160
 161     virtual SDValue
 162       LowerFormalArguments(SDValue Chain,
 163                            CallingConv::ID CallConv,
 164                            bool isVarArg,
 165                            const SmallVectorImpl<ISD::InputArg> &Ins,
 166                            DebugLoc dl, SelectionDAG &DAG,
 167                            SmallVectorImpl<SDValue> &InVals);
 168
 169     virtual SDValue
 170       LowerCall(SDValue Chain, SDValue Callee,
 171                 CallingConv::ID CallConv, bool isVarArg,
 172                 bool &isTailCall,
 173                 const SmallVectorImpl<ISD::OutputArg> &Outs,
 174                 const SmallVectorImpl<ISD::InputArg> &Ins,
 175                 DebugLoc dl, SelectionDAG &DAG,
 176                 SmallVectorImpl<SDValue> &InVals);
 177
 178     virtual SDValue
 179       LowerReturn(SDValue Chain,
 180                   CallingConv::ID CallConv, bool isVarArg,
 181                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 182                   DebugLoc dl, SelectionDAG &DAG);
 183
 184     virtual bool
 185       CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
 186                      const SmallVectorImpl<EVT> &OutTys,
 187                      const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
 188                      SelectionDAG &DAG);
 189   };
 190 }
 191
 192 #endif // XCOREISELLOWERING_H