1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that XCore uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef XCOREISELLOWERING_H
16 #define XCOREISELLOWERING_H
18 #include "llvm/CodeGen/SelectionDAG.h"
19 #include "llvm/Target/TargetLowering.h"
24 // Forward delcarations
26 class XCoreTargetMachine;
30 // Start the numbering where the builtin ops and target ops leave off.
31 FIRST_NUMBER = ISD::BUILTIN_OP_END,
33 // Branch and link (call)
36 // pc relative address
39 // dp relative address
42 // cp relative address
45 // Store word to stack
48 // Corresponds to retsp instruction
51 // Corresponds to LADD instruction
54 // Corresponds to LSUB instruction
57 // Corresponds to MACCU instruction
60 // Corresponds to MACCS instruction
66 // Jumptable branch using long branches for each entry.
71 //===--------------------------------------------------------------------===//
72 // TargetLowering Implementation
73 //===--------------------------------------------------------------------===//
74 class XCoreTargetLowering : public TargetLowering
78 explicit XCoreTargetLowering(XCoreTargetMachine &TM);
80 /// LowerOperation - Provide custom lowering hooks for some operations.
81 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG);
83 /// ReplaceNodeResults - Replace the results of node with an illegal result
84 /// type with new values built out of custom code.
86 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
89 /// getTargetNodeName - This method returns the name of a target specific
91 virtual const char *getTargetNodeName(unsigned Opcode) const;
93 virtual MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
94 MachineBasicBlock *MBB,
95 DenseMap<MachineBasicBlock*, MachineBasicBlock*> *EM) const;
97 virtual bool isLegalAddressingMode(const AddrMode &AM,
98 const Type *Ty) const;
100 /// getFunctionAlignment - Return the Log2 alignment of this function.
101 virtual unsigned getFunctionAlignment(const Function *F) const;
104 const XCoreTargetMachine &TM;
105 const XCoreSubtarget &Subtarget;
107 // Lower Operand helpers
108 SDValue LowerCCCArguments(SDValue Chain,
109 CallingConv::ID CallConv,
111 const SmallVectorImpl<ISD::InputArg> &Ins,
112 DebugLoc dl, SelectionDAG &DAG,
113 SmallVectorImpl<SDValue> &InVals);
114 SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
115 CallingConv::ID CallConv, bool isVarArg,
117 const SmallVectorImpl<ISD::OutputArg> &Outs,
118 const SmallVectorImpl<ISD::InputArg> &Ins,
119 DebugLoc dl, SelectionDAG &DAG,
120 SmallVectorImpl<SDValue> &InVals);
121 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
122 CallingConv::ID CallConv, bool isVarArg,
123 const SmallVectorImpl<ISD::InputArg> &Ins,
124 DebugLoc dl, SelectionDAG &DAG,
125 SmallVectorImpl<SDValue> &InVals);
126 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG);
127 SDValue getGlobalAddressWrapper(SDValue GA, GlobalValue *GV,
130 // Lower Operand specifics
131 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG);
132 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG);
133 SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG);
134 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG);
135 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG);
136 SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG);
137 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG);
138 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG);
139 SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG);
140 SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG);
141 SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG);
142 SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG);
143 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG);
145 // Inline asm support
146 std::vector<unsigned>
147 getRegClassForInlineAsmConstraint(const std::string &Constraint,
151 SDValue TryExpandADDSUBWithMul(SDNode *Op, SelectionDAG &DAG);
152 SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG);
154 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
156 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
160 const SelectionDAG &DAG,
161 unsigned Depth = 0) const;
164 LowerFormalArguments(SDValue Chain,
165 CallingConv::ID CallConv,
167 const SmallVectorImpl<ISD::InputArg> &Ins,
168 DebugLoc dl, SelectionDAG &DAG,
169 SmallVectorImpl<SDValue> &InVals);
172 LowerCall(SDValue Chain, SDValue Callee,
173 CallingConv::ID CallConv, bool isVarArg,
175 const SmallVectorImpl<ISD::OutputArg> &Outs,
176 const SmallVectorImpl<ISD::InputArg> &Ins,
177 DebugLoc dl, SelectionDAG &DAG,
178 SmallVectorImpl<SDValue> &InVals);
181 LowerReturn(SDValue Chain,
182 CallingConv::ID CallConv, bool isVarArg,
183 const SmallVectorImpl<ISD::OutputArg> &Outs,
184 DebugLoc dl, SelectionDAG &DAG);
187 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
188 const SmallVectorImpl<EVT> &OutTys,
189 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
194 #endif // XCOREISELLOWERING_H