lib/Target/XCore/XCoreISelLowering.h

   1 //===-- XCoreISelLowering.h - XCore DAG Lowering Interface ------*- C++ -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file defines the interfaces that XCore uses to lower LLVM code into a
  11 // selection DAG.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 #ifndef XCOREISELLOWERING_H
  16 #define XCOREISELLOWERING_H
  17
  18 #include "XCore.h"
  19 #include "llvm/CodeGen/SelectionDAG.h"
  20 #include "llvm/Target/TargetLowering.h"
  21
  22 namespace llvm {
  23
  24   // Forward delcarations
  25   class XCoreSubtarget;
  26   class XCoreTargetMachine;
  27
  28   namespace XCoreISD {
  29     enum NodeType {
  30       // Start the numbering where the builtin ops and target ops leave off.
  31       FIRST_NUMBER = ISD::BUILTIN_OP_END,
  32
  33       // Branch and link (call)
  34       BL,
  35
  36       // pc relative address
  37       PCRelativeWrapper,
  38
  39       // dp relative address
  40       DPRelativeWrapper,
  41
  42       // cp relative address
  43       CPRelativeWrapper,
  44
  45       // Store word to stack
  46       STWSP,
  47
  48       // Corresponds to retsp instruction
  49       RETSP,
  50
  51       // Corresponds to LADD instruction
  52       LADD,
  53
  54       // Corresponds to LSUB instruction
  55       LSUB,
  56
  57       // Corresponds to LMUL instruction
  58       LMUL,
  59
  60       // Corresponds to MACCU instruction
  61       MACCU,
  62
  63       // Corresponds to MACCS instruction
  64       MACCS,
  65
  66       // Corresponds to CRC8 instruction
  67       CRC8,
  68
  69       // Jumptable branch.
  70       BR_JT,
  71
  72       // Jumptable branch using long branches for each entry.
  73       BR_JT32
  74     };
  75   }
  76
  77   //===--------------------------------------------------------------------===//
  78   // TargetLowering Implementation
  79   //===--------------------------------------------------------------------===//
  80   class XCoreTargetLowering : public TargetLowering
  81   {
  82   public:
  83
  84     explicit XCoreTargetLowering(XCoreTargetMachine &TM);
  85
  86     using TargetLowering::isZExtFree;
  87     virtual bool isZExtFree(SDValue Val, EVT VT2) const;
  88
  89
  90     virtual unsigned getJumpTableEncoding() const;
  91     virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i32; }
  92
  93     /// LowerOperation - Provide custom lowering hooks for some operations.
  94     virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
  95
  96     /// ReplaceNodeResults - Replace the results of node with an illegal result
  97     /// type with new values built out of custom code.
  98     ///
  99     virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
 100                                     SelectionDAG &DAG) const;
 101
 102     /// getTargetNodeName - This method returns the name of a target specific
 103     //  DAG node.
 104     virtual const char *getTargetNodeName(unsigned Opcode) const;
 105
 106     virtual MachineBasicBlock *
 107       EmitInstrWithCustomInserter(MachineInstr *MI,
 108                                   MachineBasicBlock *MBB) const;
 109
 110     virtual bool isLegalAddressingMode(const AddrMode &AM,
 111                                        Type *Ty) const;
 112
 113   private:
 114     const XCoreTargetMachine &TM;
 115     const XCoreSubtarget &Subtarget;
 116
 117     // Lower Operand helpers
 118     SDValue LowerCCCArguments(SDValue Chain,
 119                               CallingConv::ID CallConv,
 120                               bool isVarArg,
 121                               const SmallVectorImpl<ISD::InputArg> &Ins,
 122                               SDLoc dl, SelectionDAG &DAG,
 123                               SmallVectorImpl<SDValue> &InVals) const;
 124     SDValue LowerCCCCallTo(SDValue Chain, SDValue Callee,
 125                            CallingConv::ID CallConv, bool isVarArg,
 126                            bool isTailCall,
 127                            const SmallVectorImpl<ISD::OutputArg> &Outs,
 128                            const SmallVectorImpl<SDValue> &OutVals,
 129                            const SmallVectorImpl<ISD::InputArg> &Ins,
 130                            SDLoc dl, SelectionDAG &DAG,
 131                            SmallVectorImpl<SDValue> &InVals) const;
 132     SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
 133                             CallingConv::ID CallConv, bool isVarArg,
 134                             const SmallVectorImpl<ISD::InputArg> &Ins,
 135                             SDLoc dl, SelectionDAG &DAG,
 136                             SmallVectorImpl<SDValue> &InVals) const;
 137     SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
 138     SDValue getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
 139                                     SelectionDAG &DAG) const;
 140     SDValue lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain,
 141                                                    SDValue Base, int64_t Offset,
 142                                                    SelectionDAG &DAG) const;
 143
 144     // Lower Operand specifics
 145     SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
 146     SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
 147     SDValue LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const;
 148     SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
 149     SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
 150     SDValue LowerConstantPool(SDValue Op, SelectionDAG &DAG) const;
 151     SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
 152     SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
 153     SDValue LowerVAARG(SDValue Op, SelectionDAG &DAG) const;
 154     SDValue LowerVASTART(SDValue Op, SelectionDAG &DAG) const;
 155     SDValue LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
 156     SDValue LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
 157     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
 158     SDValue LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
 159     SDValue LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const;
 160     SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
 161
 162     // Inline asm support
 163     std::pair<unsigned, const TargetRegisterClass*>
 164     getRegForInlineAsmConstraint(const std::string &Constraint,
 165                                  MVT VT) const;
 166
 167     // Expand specifics
 168     SDValue TryExpandADDWithMul(SDNode *Op, SelectionDAG &DAG) const;
 169     SDValue ExpandADDSUB(SDNode *Op, SelectionDAG &DAG) const;
 170
 171     virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
 172
 173     virtual void computeMaskedBitsForTargetNode(const SDValue Op,
 174                                                 APInt &KnownZero,
 175                                                 APInt &KnownOne,
 176                                                 const SelectionDAG &DAG,
 177                                                 unsigned Depth = 0) const;
 178
 179     virtual SDValue
 180       LowerFormalArguments(SDValue Chain,
 181                            CallingConv::ID CallConv,
 182                            bool isVarArg,
 183                            const SmallVectorImpl<ISD::InputArg> &Ins,
 184                            SDLoc dl, SelectionDAG &DAG,
 185                            SmallVectorImpl<SDValue> &InVals) const;
 186
 187     virtual SDValue
 188       LowerCall(TargetLowering::CallLoweringInfo &CLI,
 189                 SmallVectorImpl<SDValue> &InVals) const;
 190
 191     virtual SDValue
 192       LowerReturn(SDValue Chain,
 193                   CallingConv::ID CallConv, bool isVarArg,
 194                   const SmallVectorImpl<ISD::OutputArg> &Outs,
 195                   const SmallVectorImpl<SDValue> &OutVals,
 196                   SDLoc dl, SelectionDAG &DAG) const;
 197
 198     virtual bool
 199       CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
 200                      bool isVarArg,
 201                      const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
 202                      LLVMContext &Context) const;
 203   };
 204 }
 205
 206 #endif // XCOREISELLOWERING_H