1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the XCoreTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "xcore-lower"
16 #include "XCoreISelLowering.h"
17 #include "XCoreMachineFunctionInfo.h"
19 #include "XCoreTargetObjectFile.h"
20 #include "XCoreTargetMachine.h"
21 #include "XCoreSubtarget.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/GlobalAlias.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAGISel.h"
35 #include "llvm/CodeGen/ValueTypes.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/ADT/VectorExtras.h"
44 const char *XCoreTargetLowering::
45 getTargetNodeName(unsigned Opcode) const
49 case XCoreISD::BL : return "XCoreISD::BL";
50 case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
51 case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
52 case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper";
53 case XCoreISD::STWSP : return "XCoreISD::STWSP";
54 case XCoreISD::RETSP : return "XCoreISD::RETSP";
55 case XCoreISD::LADD : return "XCoreISD::LADD";
56 case XCoreISD::LSUB : return "XCoreISD::LSUB";
57 case XCoreISD::LMUL : return "XCoreISD::LMUL";
58 case XCoreISD::MACCU : return "XCoreISD::MACCU";
59 case XCoreISD::MACCS : return "XCoreISD::MACCS";
60 case XCoreISD::BR_JT : return "XCoreISD::BR_JT";
61 case XCoreISD::BR_JT32 : return "XCoreISD::BR_JT32";
62 default : return NULL;
66 XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
67 : TargetLowering(XTM, new XCoreTargetObjectFile()),
69 Subtarget(*XTM.getSubtargetImpl()) {
71 // Set up the register classes.
72 addRegisterClass(MVT::i32, XCore::GRRegsRegisterClass);
74 // Compute derived properties from the register classes
75 computeRegisterProperties();
77 // Division is expensive
78 setIntDivIsCheap(false);
80 setStackPointerRegisterToSaveRestore(XCore::SP);
82 setSchedulingPreference(Sched::RegPressure);
84 // Use i32 for setcc operations results (slt, sgt, ...).
85 setBooleanContents(ZeroOrOneBooleanContent);
87 // XCore does not have the NodeTypes below.
88 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
89 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
90 setOperationAction(ISD::ADDC, MVT::i32, Expand);
91 setOperationAction(ISD::ADDE, MVT::i32, Expand);
92 setOperationAction(ISD::SUBC, MVT::i32, Expand);
93 setOperationAction(ISD::SUBE, MVT::i32, Expand);
95 // Stop the combiner recombining select and set_cc
96 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
99 setOperationAction(ISD::ADD, MVT::i64, Custom);
100 setOperationAction(ISD::SUB, MVT::i64, Custom);
101 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
102 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
103 setOperationAction(ISD::MULHS, MVT::i32, Expand);
104 setOperationAction(ISD::MULHU, MVT::i32, Expand);
105 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
106 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
107 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
110 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
111 setOperationAction(ISD::ROTL , MVT::i32, Expand);
112 setOperationAction(ISD::ROTR , MVT::i32, Expand);
114 setOperationAction(ISD::TRAP, MVT::Other, Legal);
117 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
119 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
120 setOperationAction(ISD::BlockAddress, MVT::i32 , Custom);
122 // Thread Local Storage
123 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
125 // Conversion of i64 -> double produces constantpool nodes
126 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
129 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
130 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
131 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
133 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
134 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
136 // Custom expand misaligned loads / stores.
137 setOperationAction(ISD::LOAD, MVT::i32, Custom);
138 setOperationAction(ISD::STORE, MVT::i32, Custom);
141 setOperationAction(ISD::VAEND, MVT::Other, Expand);
142 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
143 setOperationAction(ISD::VAARG, MVT::Other, Custom);
144 setOperationAction(ISD::VASTART, MVT::Other, Custom);
147 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
148 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
149 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
151 // TRAMPOLINE is custom lowered.
152 setOperationAction(ISD::TRAMPOLINE, MVT::Other, Custom);
154 maxStoresPerMemset = maxStoresPerMemsetOptSize = 4;
155 maxStoresPerMemmove = maxStoresPerMemmoveOptSize
156 = maxStoresPerMemcpy = maxStoresPerMemcpyOptSize = 2;
158 // We have target-specific dag combine patterns for the following nodes:
159 setTargetDAGCombine(ISD::STORE);
160 setTargetDAGCombine(ISD::ADD);
163 SDValue XCoreTargetLowering::
164 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
165 switch (Op.getOpcode())
167 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
168 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
169 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
170 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
171 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
172 case ISD::LOAD: return LowerLOAD(Op, DAG);
173 case ISD::STORE: return LowerSTORE(Op, DAG);
174 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
175 case ISD::VAARG: return LowerVAARG(Op, DAG);
176 case ISD::VASTART: return LowerVASTART(Op, DAG);
177 case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG);
178 case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG);
179 // FIXME: Remove these when LegalizeDAGTypes lands.
181 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
182 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
183 case ISD::TRAMPOLINE: return LowerTRAMPOLINE(Op, DAG);
185 llvm_unreachable("unimplemented operand");
190 /// ReplaceNodeResults - Replace the results of node with an illegal result
191 /// type with new values built out of custom code.
192 void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
193 SmallVectorImpl<SDValue>&Results,
194 SelectionDAG &DAG) const {
195 switch (N->getOpcode()) {
197 llvm_unreachable("Don't know how to custom expand this!");
201 Results.push_back(ExpandADDSUB(N, DAG));
206 /// getFunctionAlignment - Return the Log2 alignment of this function.
207 unsigned XCoreTargetLowering::
208 getFunctionAlignment(const Function *) const {
212 //===----------------------------------------------------------------------===//
213 // Misc Lower Operation implementation
214 //===----------------------------------------------------------------------===//
216 SDValue XCoreTargetLowering::
217 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
219 DebugLoc dl = Op.getDebugLoc();
220 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),
221 Op.getOperand(3), Op.getOperand(4));
222 return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0),
226 SDValue XCoreTargetLowering::
227 getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
228 SelectionDAG &DAG) const
230 // FIXME there is no actual debug info here
231 DebugLoc dl = GA.getDebugLoc();
232 if (isa<Function>(GV)) {
233 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
235 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
237 // If GV is an alias then use the aliasee to determine constness
238 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
239 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
241 bool isConst = GVar && GVar->isConstant();
243 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
245 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
248 SDValue XCoreTargetLowering::
249 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
251 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
252 SDValue GA = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), MVT::i32);
253 // If it's a debug information descriptor, don't mess with it.
254 if (DAG.isVerifiedDebugInfoDesc(Op))
256 return getGlobalAddressWrapper(GA, GV, DAG);
259 static inline SDValue BuildGetId(SelectionDAG &DAG, DebugLoc dl) {
260 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
261 DAG.getConstant(Intrinsic::xcore_getid, MVT::i32));
264 static inline bool isZeroLengthArray(const Type *Ty) {
265 const ArrayType *AT = dyn_cast_or_null<ArrayType>(Ty);
266 return AT && (AT->getNumElements() == 0);
269 SDValue XCoreTargetLowering::
270 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
272 // FIXME there isn't really debug info here
273 DebugLoc dl = Op.getDebugLoc();
274 // transform to label + getid() * size
275 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
276 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32);
277 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
279 // If GV is an alias then use the aliasee to determine size
280 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
281 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
284 llvm_unreachable("Thread local object not a GlobalVariable?");
287 const Type *Ty = cast<PointerType>(GV->getType())->getElementType();
288 if (!Ty->isSized() || isZeroLengthArray(Ty)) {
290 errs() << "Size of thread local object " << GVar->getName()
295 SDValue base = getGlobalAddressWrapper(GA, GV, DAG);
296 const TargetData *TD = TM.getTargetData();
297 unsigned Size = TD->getTypeAllocSize(Ty);
298 SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl),
299 DAG.getConstant(Size, MVT::i32));
300 return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset);
303 SDValue XCoreTargetLowering::
304 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
306 DebugLoc DL = Op.getDebugLoc();
308 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
309 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true);
311 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result);
314 SDValue XCoreTargetLowering::
315 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
317 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
318 // FIXME there isn't really debug info here
319 DebugLoc dl = CP->getDebugLoc();
320 EVT PtrVT = Op.getValueType();
322 if (CP->isMachineConstantPoolEntry()) {
323 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
326 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
329 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
332 unsigned XCoreTargetLowering::getJumpTableEncoding() const {
333 return MachineJumpTableInfo::EK_Inline;
336 SDValue XCoreTargetLowering::
337 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
339 SDValue Chain = Op.getOperand(0);
340 SDValue Table = Op.getOperand(1);
341 SDValue Index = Op.getOperand(2);
342 DebugLoc dl = Op.getDebugLoc();
343 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
344 unsigned JTI = JT->getIndex();
345 MachineFunction &MF = DAG.getMachineFunction();
346 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
347 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
349 unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size();
350 if (NumEntries <= 32) {
351 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index);
353 assert((NumEntries >> 31) == 0);
354 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
355 DAG.getConstant(1, MVT::i32));
356 return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT,
361 IsWordAlignedBasePlusConstantOffset(SDValue Addr, SDValue &AlignedBase,
364 if (Addr.getOpcode() != ISD::ADD) {
367 ConstantSDNode *CN = 0;
368 if (!(CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
371 int64_t off = CN->getSExtValue();
372 const SDValue &Base = Addr.getOperand(0);
373 const SDValue *Root = &Base;
374 if (Base.getOpcode() == ISD::ADD &&
375 Base.getOperand(1).getOpcode() == ISD::SHL) {
376 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Base.getOperand(1)
378 if (CN && (CN->getSExtValue() >= 2)) {
379 Root = &Base.getOperand(0);
382 if (isa<FrameIndexSDNode>(*Root)) {
383 // All frame indicies are word aligned
388 if (Root->getOpcode() == XCoreISD::DPRelativeWrapper ||
389 Root->getOpcode() == XCoreISD::CPRelativeWrapper) {
390 // All dp / cp relative addresses are word aligned
398 SDValue XCoreTargetLowering::
399 LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
400 LoadSDNode *LD = cast<LoadSDNode>(Op);
401 assert(LD->getExtensionType() == ISD::NON_EXTLOAD &&
402 "Unexpected extension type");
403 assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT");
404 if (allowsUnalignedMemoryAccesses(LD->getMemoryVT()))
407 unsigned ABIAlignment = getTargetData()->
408 getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
409 // Leave aligned load alone.
410 if (LD->getAlignment() >= ABIAlignment)
413 SDValue Chain = LD->getChain();
414 SDValue BasePtr = LD->getBasePtr();
415 DebugLoc DL = Op.getDebugLoc();
419 if (!LD->isVolatile() &&
420 IsWordAlignedBasePlusConstantOffset(BasePtr, Base, Offset)) {
421 if (Offset % 4 == 0) {
422 // We've managed to infer better alignment information than the load
423 // already has. Use an aligned load.
425 return DAG.getLoad(getPointerTy(), DL, Chain, BasePtr,
426 MachinePointerInfo(),
430 // ldw low, base[offset >> 2]
431 // ldw high, base[(offset >> 2) + 1]
432 // shr low_shifted, low, (offset & 0x3) * 8
433 // shl high_shifted, high, 32 - (offset & 0x3) * 8
434 // or result, low_shifted, high_shifted
435 SDValue LowOffset = DAG.getConstant(Offset & ~0x3, MVT::i32);
436 SDValue HighOffset = DAG.getConstant((Offset & ~0x3) + 4, MVT::i32);
437 SDValue LowShift = DAG.getConstant((Offset & 0x3) * 8, MVT::i32);
438 SDValue HighShift = DAG.getConstant(32 - (Offset & 0x3) * 8, MVT::i32);
440 SDValue LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, LowOffset);
441 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base, HighOffset);
443 SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain,
444 LowAddr, MachinePointerInfo(), false, false, 0);
445 SDValue High = DAG.getLoad(getPointerTy(), DL, Chain,
446 HighAddr, MachinePointerInfo(), false, false, 0);
447 SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
448 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift);
449 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted);
450 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
452 SDValue Ops[] = { Result, Chain };
453 return DAG.getMergeValues(Ops, 2, DL);
456 if (LD->getAlignment() == 2) {
457 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain,
458 BasePtr, LD->getPointerInfo(), MVT::i16,
459 LD->isVolatile(), LD->isNonTemporal(), 2);
460 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
461 DAG.getConstant(2, MVT::i32));
462 SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
464 LD->getPointerInfo().getWithOffset(2),
465 MVT::i16, LD->isVolatile(),
466 LD->isNonTemporal(), 2);
467 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
468 DAG.getConstant(16, MVT::i32));
469 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);
470 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
472 SDValue Ops[] = { Result, Chain };
473 return DAG.getMergeValues(Ops, 2, DL);
476 // Lower to a call to __misaligned_load(BasePtr).
477 const Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext());
478 TargetLowering::ArgListTy Args;
479 TargetLowering::ArgListEntry Entry;
482 Entry.Node = BasePtr;
483 Args.push_back(Entry);
485 std::pair<SDValue, SDValue> CallResult =
486 LowerCallTo(Chain, IntPtrTy, false, false,
487 false, false, 0, CallingConv::C, false,
488 /*isReturnValueUsed=*/true,
489 DAG.getExternalSymbol("__misaligned_load", getPointerTy()),
493 { CallResult.first, CallResult.second };
495 return DAG.getMergeValues(Ops, 2, DL);
498 SDValue XCoreTargetLowering::
499 LowerSTORE(SDValue Op, SelectionDAG &DAG) const
501 StoreSDNode *ST = cast<StoreSDNode>(Op);
502 assert(!ST->isTruncatingStore() && "Unexpected store type");
503 assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT");
504 if (allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
507 unsigned ABIAlignment = getTargetData()->
508 getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext()));
509 // Leave aligned store alone.
510 if (ST->getAlignment() >= ABIAlignment) {
513 SDValue Chain = ST->getChain();
514 SDValue BasePtr = ST->getBasePtr();
515 SDValue Value = ST->getValue();
516 DebugLoc dl = Op.getDebugLoc();
518 if (ST->getAlignment() == 2) {
520 SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
521 DAG.getConstant(16, MVT::i32));
522 SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,
523 ST->getPointerInfo(), MVT::i16,
524 ST->isVolatile(), ST->isNonTemporal(),
526 SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
527 DAG.getConstant(2, MVT::i32));
528 SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr,
529 ST->getPointerInfo().getWithOffset(2),
530 MVT::i16, ST->isVolatile(),
531 ST->isNonTemporal(), 2);
532 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh);
535 // Lower to a call to __misaligned_store(BasePtr, Value).
536 const Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext());
537 TargetLowering::ArgListTy Args;
538 TargetLowering::ArgListEntry Entry;
541 Entry.Node = BasePtr;
542 Args.push_back(Entry);
545 Args.push_back(Entry);
547 std::pair<SDValue, SDValue> CallResult =
548 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), false, false,
549 false, false, 0, CallingConv::C, false,
550 /*isReturnValueUsed=*/true,
551 DAG.getExternalSymbol("__misaligned_store", getPointerTy()),
554 return CallResult.second;
557 SDValue XCoreTargetLowering::
558 LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
560 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&
561 "Unexpected operand to lower!");
562 DebugLoc dl = Op.getDebugLoc();
563 SDValue LHS = Op.getOperand(0);
564 SDValue RHS = Op.getOperand(1);
565 SDValue Zero = DAG.getConstant(0, MVT::i32);
566 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
567 DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
569 SDValue Lo(Hi.getNode(), 1);
570 SDValue Ops[] = { Lo, Hi };
571 return DAG.getMergeValues(Ops, 2, dl);
574 SDValue XCoreTargetLowering::
575 LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
577 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI &&
578 "Unexpected operand to lower!");
579 DebugLoc dl = Op.getDebugLoc();
580 SDValue LHS = Op.getOperand(0);
581 SDValue RHS = Op.getOperand(1);
582 SDValue Zero = DAG.getConstant(0, MVT::i32);
583 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
584 DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
586 SDValue Lo(Hi.getNode(), 1);
587 SDValue Ops[] = { Lo, Hi };
588 return DAG.getMergeValues(Ops, 2, dl);
591 /// isADDADDMUL - Return whether Op is in a form that is equivalent to
592 /// add(add(mul(x,y),a),b). If requireIntermediatesHaveOneUse is true then
593 /// each intermediate result in the calculation must also have a single use.
594 /// If the Op is in the correct form the constituent parts are written to Mul0,
595 /// Mul1, Addend0 and Addend1.
597 isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0,
598 SDValue &Addend1, bool requireIntermediatesHaveOneUse)
600 if (Op.getOpcode() != ISD::ADD)
602 SDValue N0 = Op.getOperand(0);
603 SDValue N1 = Op.getOperand(1);
606 if (N0.getOpcode() == ISD::ADD) {
609 } else if (N1.getOpcode() == ISD::ADD) {
615 if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse())
617 if (OtherOp.getOpcode() == ISD::MUL) {
618 // add(add(a,b),mul(x,y))
619 if (requireIntermediatesHaveOneUse && !OtherOp.hasOneUse())
621 Mul0 = OtherOp.getOperand(0);
622 Mul1 = OtherOp.getOperand(1);
623 Addend0 = AddOp.getOperand(0);
624 Addend1 = AddOp.getOperand(1);
627 if (AddOp.getOperand(0).getOpcode() == ISD::MUL) {
628 // add(add(mul(x,y),a),b)
629 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(0).hasOneUse())
631 Mul0 = AddOp.getOperand(0).getOperand(0);
632 Mul1 = AddOp.getOperand(0).getOperand(1);
633 Addend0 = AddOp.getOperand(1);
637 if (AddOp.getOperand(1).getOpcode() == ISD::MUL) {
638 // add(add(a,mul(x,y)),b)
639 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(1).hasOneUse())
641 Mul0 = AddOp.getOperand(1).getOperand(0);
642 Mul1 = AddOp.getOperand(1).getOperand(1);
643 Addend0 = AddOp.getOperand(0);
650 SDValue XCoreTargetLowering::
651 TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
655 if (N->getOperand(0).getOpcode() == ISD::MUL) {
656 Mul = N->getOperand(0);
657 Other = N->getOperand(1);
658 } else if (N->getOperand(1).getOpcode() == ISD::MUL) {
659 Mul = N->getOperand(1);
660 Other = N->getOperand(0);
664 DebugLoc dl = N->getDebugLoc();
665 SDValue LL, RL, AddendL, AddendH;
666 LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
667 Mul.getOperand(0), DAG.getConstant(0, MVT::i32));
668 RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
669 Mul.getOperand(1), DAG.getConstant(0, MVT::i32));
670 AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
671 Other, DAG.getConstant(0, MVT::i32));
672 AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
673 Other, DAG.getConstant(1, MVT::i32));
674 APInt HighMask = APInt::getHighBitsSet(64, 32);
675 unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0));
676 unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1));
677 if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) &&
678 DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) {
679 // The inputs are both zero-extended.
680 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
681 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
683 SDValue Lo(Hi.getNode(), 1);
684 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
686 if (LHSSB > 32 && RHSSB > 32) {
687 // The inputs are both sign-extended.
688 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
689 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
691 SDValue Lo(Hi.getNode(), 1);
692 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
695 LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
696 Mul.getOperand(0), DAG.getConstant(1, MVT::i32));
697 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
698 Mul.getOperand(1), DAG.getConstant(1, MVT::i32));
699 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
700 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
702 SDValue Lo(Hi.getNode(), 1);
703 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH);
704 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL);
705 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH);
706 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH);
707 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
710 SDValue XCoreTargetLowering::
711 ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
713 assert(N->getValueType(0) == MVT::i64 &&
714 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
715 "Unknown operand to lower!");
717 if (N->getOpcode() == ISD::ADD) {
718 SDValue Result = TryExpandADDWithMul(N, DAG);
719 if (Result.getNode() != 0)
723 DebugLoc dl = N->getDebugLoc();
725 // Extract components
726 SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
727 N->getOperand(0), DAG.getConstant(0, MVT::i32));
728 SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
729 N->getOperand(0), DAG.getConstant(1, MVT::i32));
730 SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
731 N->getOperand(1), DAG.getConstant(0, MVT::i32));
732 SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
733 N->getOperand(1), DAG.getConstant(1, MVT::i32));
736 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
738 SDValue Zero = DAG.getConstant(0, MVT::i32);
739 SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
741 SDValue Lo(Carry.getNode(), 1);
743 SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
745 SDValue Hi(Ignored.getNode(), 1);
747 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
750 SDValue XCoreTargetLowering::
751 LowerVAARG(SDValue Op, SelectionDAG &DAG) const
753 llvm_unreachable("unimplemented");
754 // FIX Arguments passed by reference need a extra dereference.
755 SDNode *Node = Op.getNode();
756 DebugLoc dl = Node->getDebugLoc();
757 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
758 EVT VT = Node->getValueType(0);
759 SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0),
760 Node->getOperand(1), MachinePointerInfo(V),
762 // Increment the pointer, VAList, to the next vararg
763 SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList,
764 DAG.getConstant(VT.getSizeInBits(),
766 // Store the incremented VAList to the legalized pointer
767 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1),
768 MachinePointerInfo(V), false, false, 0);
769 // Load the actual argument out of the pointer VAList
770 return DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(),
774 SDValue XCoreTargetLowering::
775 LowerVASTART(SDValue Op, SelectionDAG &DAG) const
777 DebugLoc dl = Op.getDebugLoc();
778 // vastart stores the address of the VarArgsFrameIndex slot into the
779 // memory location argument
780 MachineFunction &MF = DAG.getMachineFunction();
781 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
782 SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32);
783 return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1),
784 MachinePointerInfo(), false, false, 0);
787 SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op,
788 SelectionDAG &DAG) const {
789 DebugLoc dl = Op.getDebugLoc();
790 // Depths > 0 not supported yet!
791 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
794 MachineFunction &MF = DAG.getMachineFunction();
795 const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo();
796 return DAG.getCopyFromReg(DAG.getEntryNode(), dl,
797 RegInfo->getFrameRegister(MF), MVT::i32);
800 SDValue XCoreTargetLowering::
801 LowerTRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
802 SDValue Chain = Op.getOperand(0);
803 SDValue Trmp = Op.getOperand(1); // trampoline
804 SDValue FPtr = Op.getOperand(2); // nested function
805 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
807 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
810 // LDAPF_u10 r11, nest
811 // LDW_2rus r11, r11[0]
812 // STWSP_ru6 r11, sp[0]
813 // LDAPF_u10 r11, fptr
814 // LDW_2rus r11, r11[0]
820 SDValue OutChains[5];
824 DebugLoc dl = Op.getDebugLoc();
825 OutChains[0] = DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, MVT::i32),
826 Addr, MachinePointerInfo(TrmpAddr), false, false,
829 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
830 DAG.getConstant(4, MVT::i32));
831 OutChains[1] = DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, MVT::i32),
832 Addr, MachinePointerInfo(TrmpAddr, 4), false,
835 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
836 DAG.getConstant(8, MVT::i32));
837 OutChains[2] = DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, MVT::i32),
838 Addr, MachinePointerInfo(TrmpAddr, 8), false,
841 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
842 DAG.getConstant(12, MVT::i32));
843 OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr,
844 MachinePointerInfo(TrmpAddr, 12), false, false,
847 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
848 DAG.getConstant(16, MVT::i32));
849 OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr,
850 MachinePointerInfo(TrmpAddr, 16), false, false,
854 { Trmp, DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 5) };
855 return DAG.getMergeValues(Ops, 2, dl);
858 //===----------------------------------------------------------------------===//
859 // Calling Convention Implementation
860 //===----------------------------------------------------------------------===//
862 #include "XCoreGenCallingConv.inc"
864 //===----------------------------------------------------------------------===//
865 // Call Calling Convention Implementation
866 //===----------------------------------------------------------------------===//
868 /// XCore call implementation
870 XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
871 CallingConv::ID CallConv, bool isVarArg,
873 const SmallVectorImpl<ISD::OutputArg> &Outs,
874 const SmallVectorImpl<SDValue> &OutVals,
875 const SmallVectorImpl<ISD::InputArg> &Ins,
876 DebugLoc dl, SelectionDAG &DAG,
877 SmallVectorImpl<SDValue> &InVals) const {
878 // XCore target does not yet support tail call optimization.
881 // For now, only CallingConv::C implemented
885 llvm_unreachable("Unsupported calling convention");
886 case CallingConv::Fast:
888 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
889 Outs, OutVals, Ins, dl, DAG, InVals);
893 /// LowerCCCCallTo - functions arguments are copied from virtual
894 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
895 /// CALLSEQ_END are emitted.
896 /// TODO: isTailCall, sret.
898 XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
899 CallingConv::ID CallConv, bool isVarArg,
901 const SmallVectorImpl<ISD::OutputArg> &Outs,
902 const SmallVectorImpl<SDValue> &OutVals,
903 const SmallVectorImpl<ISD::InputArg> &Ins,
904 DebugLoc dl, SelectionDAG &DAG,
905 SmallVectorImpl<SDValue> &InVals) const {
907 // Analyze operands of the call, assigning locations to each operand.
908 SmallVector<CCValAssign, 16> ArgLocs;
909 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
910 ArgLocs, *DAG.getContext());
912 // The ABI dictates there should be one stack slot available to the callee
913 // on function entry (for saving lr).
914 CCInfo.AllocateStack(4, 4);
916 CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
918 // Get a count of how many bytes are to be pushed on the stack.
919 unsigned NumBytes = CCInfo.getNextStackOffset();
921 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
922 getPointerTy(), true));
924 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
925 SmallVector<SDValue, 12> MemOpChains;
927 // Walk the register/memloc assignments, inserting copies/loads.
928 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
929 CCValAssign &VA = ArgLocs[i];
930 SDValue Arg = OutVals[i];
932 // Promote the value if needed.
933 switch (VA.getLocInfo()) {
934 default: llvm_unreachable("Unknown loc info!");
935 case CCValAssign::Full: break;
936 case CCValAssign::SExt:
937 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
939 case CCValAssign::ZExt:
940 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
942 case CCValAssign::AExt:
943 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
947 // Arguments that can be passed on register must be kept at
950 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
952 assert(VA.isMemLoc());
954 int Offset = VA.getLocMemOffset();
956 MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
958 DAG.getConstant(Offset/4, MVT::i32)));
962 // Transform all store nodes into one single node because
963 // all store nodes are independent of each other.
964 if (!MemOpChains.empty())
965 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
966 &MemOpChains[0], MemOpChains.size());
968 // Build a sequence of copy-to-reg nodes chained together with token
969 // chain and flag operands which copy the outgoing args into registers.
970 // The InFlag in necessary since all emited instructions must be
973 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
974 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
975 RegsToPass[i].second, InFlag);
976 InFlag = Chain.getValue(1);
979 // If the callee is a GlobalAddress node (quite common, every direct call is)
980 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
981 // Likewise ExternalSymbol -> TargetExternalSymbol.
982 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
983 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
984 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
985 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
987 // XCoreBranchLink = #chain, #target_address, #opt_in_flags...
988 // = Chain, Callee, Reg#1, Reg#2, ...
990 // Returns a chain & a flag for retval copy to use.
991 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
992 SmallVector<SDValue, 8> Ops;
993 Ops.push_back(Chain);
994 Ops.push_back(Callee);
996 // Add argument registers to the end of the list so that they are
997 // known live into the call.
998 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
999 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1000 RegsToPass[i].second.getValueType()));
1002 if (InFlag.getNode())
1003 Ops.push_back(InFlag);
1005 Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, &Ops[0], Ops.size());
1006 InFlag = Chain.getValue(1);
1008 // Create the CALLSEQ_END node.
1009 Chain = DAG.getCALLSEQ_END(Chain,
1010 DAG.getConstant(NumBytes, getPointerTy(), true),
1011 DAG.getConstant(0, getPointerTy(), true),
1013 InFlag = Chain.getValue(1);
1015 // Handle result values, copying them out of physregs into vregs that we
1017 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
1018 Ins, dl, DAG, InVals);
1021 /// LowerCallResult - Lower the result values of a call into the
1022 /// appropriate copies out of appropriate physical registers.
1024 XCoreTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
1025 CallingConv::ID CallConv, bool isVarArg,
1026 const SmallVectorImpl<ISD::InputArg> &Ins,
1027 DebugLoc dl, SelectionDAG &DAG,
1028 SmallVectorImpl<SDValue> &InVals) const {
1030 // Assign locations to each value returned by this call.
1031 SmallVector<CCValAssign, 16> RVLocs;
1032 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1033 RVLocs, *DAG.getContext());
1035 CCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
1037 // Copy all of the result registers out of their specified physreg.
1038 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1039 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
1040 RVLocs[i].getValVT(), InFlag).getValue(1);
1041 InFlag = Chain.getValue(2);
1042 InVals.push_back(Chain.getValue(0));
1048 //===----------------------------------------------------------------------===//
1049 // Formal Arguments Calling Convention Implementation
1050 //===----------------------------------------------------------------------===//
1052 /// XCore formal arguments implementation
1054 XCoreTargetLowering::LowerFormalArguments(SDValue Chain,
1055 CallingConv::ID CallConv,
1057 const SmallVectorImpl<ISD::InputArg> &Ins,
1060 SmallVectorImpl<SDValue> &InVals)
1065 llvm_unreachable("Unsupported calling convention");
1066 case CallingConv::C:
1067 case CallingConv::Fast:
1068 return LowerCCCArguments(Chain, CallConv, isVarArg,
1069 Ins, dl, DAG, InVals);
1073 /// LowerCCCArguments - transform physical registers into
1074 /// virtual registers and generate load operations for
1075 /// arguments places on the stack.
1078 XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
1079 CallingConv::ID CallConv,
1081 const SmallVectorImpl<ISD::InputArg>
1085 SmallVectorImpl<SDValue> &InVals) const {
1086 MachineFunction &MF = DAG.getMachineFunction();
1087 MachineFrameInfo *MFI = MF.getFrameInfo();
1088 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1090 // Assign locations to all of the incoming arguments.
1091 SmallVector<CCValAssign, 16> ArgLocs;
1092 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1093 ArgLocs, *DAG.getContext());
1095 CCInfo.AnalyzeFormalArguments(Ins, CC_XCore);
1097 unsigned StackSlotSize = XCoreFrameLowering::stackSlotSize();
1099 unsigned LRSaveSize = StackSlotSize;
1101 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1103 CCValAssign &VA = ArgLocs[i];
1105 if (VA.isRegLoc()) {
1106 // Arguments passed in registers
1107 EVT RegVT = VA.getLocVT();
1108 switch (RegVT.getSimpleVT().SimpleTy) {
1112 errs() << "LowerFormalArguments Unhandled argument type: "
1113 << RegVT.getSimpleVT().SimpleTy << "\n";
1115 llvm_unreachable(0);
1118 unsigned VReg = RegInfo.createVirtualRegister(
1119 XCore::GRRegsRegisterClass);
1120 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1121 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1125 assert(VA.isMemLoc());
1126 // Load the argument to a virtual register
1127 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
1128 if (ObjSize > StackSlotSize) {
1129 errs() << "LowerFormalArguments Unhandled argument type: "
1130 << EVT(VA.getLocVT()).getEVTString()
1133 // Create the frame index object for this incoming parameter...
1134 int FI = MFI->CreateFixedObject(ObjSize,
1135 LRSaveSize + VA.getLocMemOffset(),
1138 // Create the SelectionDAG nodes corresponding to a load
1139 //from this parameter
1140 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1141 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
1142 MachinePointerInfo::getFixedStack(FI),
1148 /* Argument registers */
1149 static const unsigned ArgRegs[] = {
1150 XCore::R0, XCore::R1, XCore::R2, XCore::R3
1152 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
1153 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs,
1154 array_lengthof(ArgRegs));
1155 if (FirstVAReg < array_lengthof(ArgRegs)) {
1156 SmallVector<SDValue, 4> MemOps;
1158 // Save remaining registers, storing higher register numbers at a higher
1160 for (unsigned i = array_lengthof(ArgRegs) - 1; i >= FirstVAReg; --i) {
1161 // Create a stack slot
1162 int FI = MFI->CreateFixedObject(4, offset, true);
1163 if (i == FirstVAReg) {
1164 XFI->setVarArgsFrameIndex(FI);
1166 offset -= StackSlotSize;
1167 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1168 // Move argument from phys reg -> virt reg
1169 unsigned VReg = RegInfo.createVirtualRegister(
1170 XCore::GRRegsRegisterClass);
1171 RegInfo.addLiveIn(ArgRegs[i], VReg);
1172 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1173 // Move argument from virt reg -> stack
1174 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1175 MachinePointerInfo(), false, false, 0);
1176 MemOps.push_back(Store);
1178 if (!MemOps.empty())
1179 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1180 &MemOps[0], MemOps.size());
1182 // This will point to the next argument passed via stack.
1183 XFI->setVarArgsFrameIndex(
1184 MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(),
1192 //===----------------------------------------------------------------------===//
1193 // Return Value Calling Convention Implementation
1194 //===----------------------------------------------------------------------===//
1196 bool XCoreTargetLowering::
1197 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1198 const SmallVectorImpl<ISD::OutputArg> &Outs,
1199 LLVMContext &Context) const {
1200 SmallVector<CCValAssign, 16> RVLocs;
1201 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1203 return CCInfo.CheckReturn(Outs, RetCC_XCore);
1207 XCoreTargetLowering::LowerReturn(SDValue Chain,
1208 CallingConv::ID CallConv, bool isVarArg,
1209 const SmallVectorImpl<ISD::OutputArg> &Outs,
1210 const SmallVectorImpl<SDValue> &OutVals,
1211 DebugLoc dl, SelectionDAG &DAG) const {
1213 // CCValAssign - represent the assignment of
1214 // the return value to a location
1215 SmallVector<CCValAssign, 16> RVLocs;
1217 // CCState - Info about the registers and stack slot.
1218 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1219 RVLocs, *DAG.getContext());
1221 // Analize return values.
1222 CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
1224 // If this is the first return lowered for this function, add
1225 // the regs to the liveout set for the function.
1226 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1227 for (unsigned i = 0; i != RVLocs.size(); ++i)
1228 if (RVLocs[i].isRegLoc())
1229 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1234 // Copy the result values into the output registers.
1235 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1236 CCValAssign &VA = RVLocs[i];
1237 assert(VA.isRegLoc() && "Can only return in registers!");
1239 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1242 // guarantee that all emitted copies are
1243 // stuck together, avoiding something bad
1244 Flag = Chain.getValue(1);
1247 // Return on XCore is always a "retsp 0"
1249 return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
1250 Chain, DAG.getConstant(0, MVT::i32), Flag);
1252 return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
1253 Chain, DAG.getConstant(0, MVT::i32));
1256 //===----------------------------------------------------------------------===//
1257 // Other Lowering Code
1258 //===----------------------------------------------------------------------===//
1261 XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1262 MachineBasicBlock *BB) const {
1263 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1264 DebugLoc dl = MI->getDebugLoc();
1265 assert((MI->getOpcode() == XCore::SELECT_CC) &&
1266 "Unexpected instr type to insert");
1268 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1269 // control-flow pattern. The incoming instruction knows the destination vreg
1270 // to set, the condition code register to branch on, the true/false values to
1271 // select between, and a branch opcode to use.
1272 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1273 MachineFunction::iterator It = BB;
1279 // cmpTY ccX, r1, r2
1281 // fallthrough --> copy0MBB
1282 MachineBasicBlock *thisMBB = BB;
1283 MachineFunction *F = BB->getParent();
1284 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1285 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1286 F->insert(It, copy0MBB);
1287 F->insert(It, sinkMBB);
1289 // Transfer the remainder of BB and its successor edges to sinkMBB.
1290 sinkMBB->splice(sinkMBB->begin(), BB,
1291 llvm::next(MachineBasicBlock::iterator(MI)),
1293 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1295 // Next, add the true and fallthrough blocks as its successors.
1296 BB->addSuccessor(copy0MBB);
1297 BB->addSuccessor(sinkMBB);
1299 BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
1300 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
1303 // %FalseValue = ...
1304 // # fallthrough to sinkMBB
1307 // Update machine-CFG edges
1308 BB->addSuccessor(sinkMBB);
1311 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1314 BuildMI(*BB, BB->begin(), dl,
1315 TII.get(XCore::PHI), MI->getOperand(0).getReg())
1316 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
1317 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1319 MI->eraseFromParent(); // The pseudo instruction is gone now.
1323 //===----------------------------------------------------------------------===//
1324 // Target Optimization Hooks
1325 //===----------------------------------------------------------------------===//
1327 SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
1328 DAGCombinerInfo &DCI) const {
1329 SelectionDAG &DAG = DCI.DAG;
1330 DebugLoc dl = N->getDebugLoc();
1331 switch (N->getOpcode()) {
1333 case XCoreISD::LADD: {
1334 SDValue N0 = N->getOperand(0);
1335 SDValue N1 = N->getOperand(1);
1336 SDValue N2 = N->getOperand(2);
1337 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1338 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1339 EVT VT = N0.getValueType();
1341 // canonicalize constant to RHS
1343 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2);
1345 // fold (ladd 0, 0, x) -> 0, x & 1
1346 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1347 SDValue Carry = DAG.getConstant(0, VT);
1348 SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
1349 DAG.getConstant(1, VT));
1350 SDValue Ops [] = { Carry, Result };
1351 return DAG.getMergeValues(Ops, 2, dl);
1354 // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the
1356 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 0)) {
1357 APInt KnownZero, KnownOne;
1358 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1359 VT.getSizeInBits() - 1);
1360 DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne);
1361 if (KnownZero == Mask) {
1362 SDValue Carry = DAG.getConstant(0, VT);
1363 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
1364 SDValue Ops [] = { Carry, Result };
1365 return DAG.getMergeValues(Ops, 2, dl);
1370 case XCoreISD::LSUB: {
1371 SDValue N0 = N->getOperand(0);
1372 SDValue N1 = N->getOperand(1);
1373 SDValue N2 = N->getOperand(2);
1374 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1375 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1376 EVT VT = N0.getValueType();
1378 // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set
1379 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1380 APInt KnownZero, KnownOne;
1381 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1382 VT.getSizeInBits() - 1);
1383 DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne);
1384 if (KnownZero == Mask) {
1385 SDValue Borrow = N2;
1386 SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
1387 DAG.getConstant(0, VT), N2);
1388 SDValue Ops [] = { Borrow, Result };
1389 return DAG.getMergeValues(Ops, 2, dl);
1393 // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the
1395 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 0)) {
1396 APInt KnownZero, KnownOne;
1397 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1398 VT.getSizeInBits() - 1);
1399 DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne);
1400 if (KnownZero == Mask) {
1401 SDValue Borrow = DAG.getConstant(0, VT);
1402 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
1403 SDValue Ops [] = { Borrow, Result };
1404 return DAG.getMergeValues(Ops, 2, dl);
1409 case XCoreISD::LMUL: {
1410 SDValue N0 = N->getOperand(0);
1411 SDValue N1 = N->getOperand(1);
1412 SDValue N2 = N->getOperand(2);
1413 SDValue N3 = N->getOperand(3);
1414 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1415 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1416 EVT VT = N0.getValueType();
1417 // Canonicalize multiplicative constant to RHS. If both multiplicative
1418 // operands are constant canonicalize smallest to RHS.
1419 if ((N0C && !N1C) ||
1420 (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue()))
1421 return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT), N1, N0, N2, N3);
1424 if (N1C && N1C->isNullValue()) {
1425 // If the high result is unused fold to add(a, b)
1426 if (N->hasNUsesOfValue(0, 0)) {
1427 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3);
1428 SDValue Ops [] = { Lo, Lo };
1429 return DAG.getMergeValues(Ops, 2, dl);
1431 // Otherwise fold to ladd(a, b, 0)
1432 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1);
1437 // Fold 32 bit expressions such as add(add(mul(x,y),a),b) ->
1438 // lmul(x, y, a, b). The high result of lmul will be ignored.
1439 // This is only profitable if the intermediate results are unused
1441 SDValue Mul0, Mul1, Addend0, Addend1;
1442 if (N->getValueType(0) == MVT::i32 &&
1443 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) {
1444 SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl,
1445 DAG.getVTList(MVT::i32, MVT::i32), Mul0,
1446 Mul1, Addend0, Addend1);
1447 SDValue Result(Ignored.getNode(), 1);
1450 APInt HighMask = APInt::getHighBitsSet(64, 32);
1451 // Fold 64 bit expression such as add(add(mul(x,y),a),b) ->
1452 // lmul(x, y, a, b) if all operands are zero-extended. We do this
1453 // before type legalization as it is messy to match the operands after
1455 if (N->getValueType(0) == MVT::i64 &&
1456 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) &&
1457 DAG.MaskedValueIsZero(Mul0, HighMask) &&
1458 DAG.MaskedValueIsZero(Mul1, HighMask) &&
1459 DAG.MaskedValueIsZero(Addend0, HighMask) &&
1460 DAG.MaskedValueIsZero(Addend1, HighMask)) {
1461 SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1462 Mul0, DAG.getConstant(0, MVT::i32));
1463 SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1464 Mul1, DAG.getConstant(0, MVT::i32));
1465 SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1466 Addend0, DAG.getConstant(0, MVT::i32));
1467 SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1468 Addend1, DAG.getConstant(0, MVT::i32));
1469 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
1470 DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,
1471 Addend0L, Addend1L);
1472 SDValue Lo(Hi.getNode(), 1);
1473 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1478 // Replace unaligned store of unaligned load with memmove.
1479 StoreSDNode *ST = cast<StoreSDNode>(N);
1480 if (!DCI.isBeforeLegalize() ||
1481 allowsUnalignedMemoryAccesses(ST->getMemoryVT()) ||
1482 ST->isVolatile() || ST->isIndexed()) {
1485 SDValue Chain = ST->getChain();
1487 unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits();
1488 if (StoreBits % 8) {
1491 unsigned ABIAlignment = getTargetData()->getABITypeAlignment(
1492 ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext()));
1493 unsigned Alignment = ST->getAlignment();
1494 if (Alignment >= ABIAlignment) {
1498 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(ST->getValue())) {
1499 if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() &&
1500 LD->getAlignment() == Alignment &&
1501 !LD->isVolatile() && !LD->isIndexed() &&
1502 Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) {
1503 return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
1505 DAG.getConstant(StoreBits/8, MVT::i32),
1506 Alignment, false, ST->getPointerInfo(),
1507 LD->getPointerInfo());
1516 void XCoreTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1520 const SelectionDAG &DAG,
1521 unsigned Depth) const {
1522 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1523 switch (Op.getOpcode()) {
1525 case XCoreISD::LADD:
1526 case XCoreISD::LSUB:
1527 if (Op.getResNo() == 0) {
1528 // Top bits of carry / borrow are clear.
1529 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
1530 Mask.getBitWidth() - 1);
1537 //===----------------------------------------------------------------------===//
1538 // Addressing mode description hooks
1539 //===----------------------------------------------------------------------===//
1541 static inline bool isImmUs(int64_t val)
1543 return (val >= 0 && val <= 11);
1546 static inline bool isImmUs2(int64_t val)
1548 return (val%2 == 0 && isImmUs(val/2));
1551 static inline bool isImmUs4(int64_t val)
1553 return (val%4 == 0 && isImmUs(val/4));
1556 /// isLegalAddressingMode - Return true if the addressing mode represented
1557 /// by AM is legal for this target, for a load/store of the specified type.
1559 XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1560 const Type *Ty) const {
1561 if (Ty->getTypeID() == Type::VoidTyID)
1562 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
1564 const TargetData *TD = TM.getTargetData();
1565 unsigned Size = TD->getTypeAllocSize(Ty);
1567 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
1574 if (AM.Scale == 0) {
1575 return isImmUs(AM.BaseOffs);
1578 return AM.Scale == 1 && AM.BaseOffs == 0;
1582 if (AM.Scale == 0) {
1583 return isImmUs2(AM.BaseOffs);
1586 return AM.Scale == 2 && AM.BaseOffs == 0;
1589 if (AM.Scale == 0) {
1590 return isImmUs4(AM.BaseOffs);
1593 return AM.Scale == 4 && AM.BaseOffs == 0;
1599 //===----------------------------------------------------------------------===//
1600 // XCore Inline Assembly Support
1601 //===----------------------------------------------------------------------===//
1603 std::vector<unsigned> XCoreTargetLowering::
1604 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1607 if (Constraint.size() != 1)
1608 return std::vector<unsigned>();
1610 switch (Constraint[0]) {
1613 return make_vector<unsigned>(XCore::R0, XCore::R1, XCore::R2,
1614 XCore::R3, XCore::R4, XCore::R5,
1615 XCore::R6, XCore::R7, XCore::R8,
1616 XCore::R9, XCore::R10, XCore::R11, 0);
1619 return std::vector<unsigned>();