1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the XCoreTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "XCoreISelLowering.h"
16 #include "XCoreMachineFunctionInfo.h"
17 #include "XCoreSubtarget.h"
18 #include "XCoreTargetMachine.h"
19 #include "XCoreTargetObjectFile.h"
20 #include "llvm/CodeGen/CallingConvLower.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineJumpTableInfo.h"
25 #include "llvm/CodeGen/MachineRegisterInfo.h"
26 #include "llvm/CodeGen/SelectionDAGISel.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/IR/CallingConv.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/DerivedTypes.h"
31 #include "llvm/IR/Function.h"
32 #include "llvm/IR/GlobalAlias.h"
33 #include "llvm/IR/GlobalVariable.h"
34 #include "llvm/IR/Intrinsics.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/ErrorHandling.h"
37 #include "llvm/Support/raw_ostream.h"
42 #define DEBUG_TYPE "xcore-lower"
44 const char *XCoreTargetLowering::
45 getTargetNodeName(unsigned Opcode) const
49 case XCoreISD::BL : return "XCoreISD::BL";
50 case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
51 case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
52 case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper";
53 case XCoreISD::LDWSP : return "XCoreISD::LDWSP";
54 case XCoreISD::STWSP : return "XCoreISD::STWSP";
55 case XCoreISD::RETSP : return "XCoreISD::RETSP";
56 case XCoreISD::LADD : return "XCoreISD::LADD";
57 case XCoreISD::LSUB : return "XCoreISD::LSUB";
58 case XCoreISD::LMUL : return "XCoreISD::LMUL";
59 case XCoreISD::MACCU : return "XCoreISD::MACCU";
60 case XCoreISD::MACCS : return "XCoreISD::MACCS";
61 case XCoreISD::CRC8 : return "XCoreISD::CRC8";
62 case XCoreISD::BR_JT : return "XCoreISD::BR_JT";
63 case XCoreISD::BR_JT32 : return "XCoreISD::BR_JT32";
64 case XCoreISD::FRAME_TO_ARGS_OFFSET : return "XCoreISD::FRAME_TO_ARGS_OFFSET";
65 case XCoreISD::EH_RETURN : return "XCoreISD::EH_RETURN";
66 case XCoreISD::MEMBARRIER : return "XCoreISD::MEMBARRIER";
67 default : return nullptr;
71 XCoreTargetLowering::XCoreTargetLowering(const TargetMachine &TM,
72 const XCoreSubtarget &Subtarget)
73 : TargetLowering(TM), TM(TM), Subtarget(Subtarget) {
75 // Set up the register classes.
76 addRegisterClass(MVT::i32, &XCore::GRRegsRegClass);
78 // Compute derived properties from the register classes
79 computeRegisterProperties();
81 // Division is expensive
82 setIntDivIsCheap(false);
84 setStackPointerRegisterToSaveRestore(XCore::SP);
86 setSchedulingPreference(Sched::Source);
88 // Use i32 for setcc operations results (slt, sgt, ...).
89 setBooleanContents(ZeroOrOneBooleanContent);
90 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
92 // XCore does not have the NodeTypes below.
93 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
94 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
95 setOperationAction(ISD::ADDC, MVT::i32, Expand);
96 setOperationAction(ISD::ADDE, MVT::i32, Expand);
97 setOperationAction(ISD::SUBC, MVT::i32, Expand);
98 setOperationAction(ISD::SUBE, MVT::i32, Expand);
101 setOperationAction(ISD::ADD, MVT::i64, Custom);
102 setOperationAction(ISD::SUB, MVT::i64, Custom);
103 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
104 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
105 setOperationAction(ISD::MULHS, MVT::i32, Expand);
106 setOperationAction(ISD::MULHU, MVT::i32, Expand);
107 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
108 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
109 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
112 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
113 setOperationAction(ISD::ROTL , MVT::i32, Expand);
114 setOperationAction(ISD::ROTR , MVT::i32, Expand);
115 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
116 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Expand);
118 setOperationAction(ISD::TRAP, MVT::Other, Legal);
121 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
123 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
124 setOperationAction(ISD::BlockAddress, MVT::i32 , Custom);
126 // Conversion of i64 -> double produces constantpool nodes
127 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
130 for (MVT VT : MVT::integer_valuetypes()) {
131 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
132 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
133 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
135 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i8, Expand);
136 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand);
139 // Custom expand misaligned loads / stores.
140 setOperationAction(ISD::LOAD, MVT::i32, Custom);
141 setOperationAction(ISD::STORE, MVT::i32, Custom);
144 setOperationAction(ISD::VAEND, MVT::Other, Expand);
145 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
146 setOperationAction(ISD::VAARG, MVT::Other, Custom);
147 setOperationAction(ISD::VASTART, MVT::Other, Custom);
150 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
151 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
152 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
154 // Exception handling
155 setOperationAction(ISD::EH_RETURN, MVT::Other, Custom);
156 setExceptionPointerRegister(XCore::R0);
157 setExceptionSelectorRegister(XCore::R1);
158 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom);
161 // We request a fence for ATOMIC_* instructions, to reduce them to Monotonic.
162 // As we are always Sequential Consistent, an ATOMIC_FENCE becomes a no OP.
163 setInsertFencesForAtomic(true);
164 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
165 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Custom);
166 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Custom);
168 // TRAMPOLINE is custom lowered.
169 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom);
170 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom);
172 // We want to custom lower some of our intrinsics.
173 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
175 MaxStoresPerMemset = MaxStoresPerMemsetOptSize = 4;
176 MaxStoresPerMemmove = MaxStoresPerMemmoveOptSize
177 = MaxStoresPerMemcpy = MaxStoresPerMemcpyOptSize = 2;
179 // We have target-specific dag combine patterns for the following nodes:
180 setTargetDAGCombine(ISD::STORE);
181 setTargetDAGCombine(ISD::ADD);
182 setTargetDAGCombine(ISD::INTRINSIC_VOID);
183 setTargetDAGCombine(ISD::INTRINSIC_W_CHAIN);
185 setMinFunctionAlignment(1);
186 setPrefFunctionAlignment(2);
189 bool XCoreTargetLowering::isZExtFree(SDValue Val, EVT VT2) const {
190 if (Val.getOpcode() != ISD::LOAD)
193 EVT VT1 = Val.getValueType();
194 if (!VT1.isSimple() || !VT1.isInteger() ||
195 !VT2.isSimple() || !VT2.isInteger())
198 switch (VT1.getSimpleVT().SimpleTy) {
207 SDValue XCoreTargetLowering::
208 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
209 switch (Op.getOpcode())
211 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG);
212 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
213 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
214 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
215 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
216 case ISD::LOAD: return LowerLOAD(Op, DAG);
217 case ISD::STORE: return LowerSTORE(Op, DAG);
218 case ISD::VAARG: return LowerVAARG(Op, DAG);
219 case ISD::VASTART: return LowerVASTART(Op, DAG);
220 case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG);
221 case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG);
222 // FIXME: Remove these when LegalizeDAGTypes lands.
224 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
225 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
226 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG);
227 case ISD::FRAME_TO_ARGS_OFFSET: return LowerFRAME_TO_ARGS_OFFSET(Op, DAG);
228 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG);
229 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG);
230 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
231 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG);
232 case ISD::ATOMIC_LOAD: return LowerATOMIC_LOAD(Op, DAG);
233 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op, DAG);
235 llvm_unreachable("unimplemented operand");
239 /// ReplaceNodeResults - Replace the results of node with an illegal result
240 /// type with new values built out of custom code.
241 void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
242 SmallVectorImpl<SDValue>&Results,
243 SelectionDAG &DAG) const {
244 switch (N->getOpcode()) {
246 llvm_unreachable("Don't know how to custom expand this!");
249 Results.push_back(ExpandADDSUB(N, DAG));
254 //===----------------------------------------------------------------------===//
255 // Misc Lower Operation implementation
256 //===----------------------------------------------------------------------===//
258 SDValue XCoreTargetLowering::getGlobalAddressWrapper(SDValue GA,
259 const GlobalValue *GV,
260 SelectionDAG &DAG) const {
261 // FIXME there is no actual debug info here
264 if (GV->getType()->getElementType()->isFunctionTy())
265 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
267 const auto *GVar = dyn_cast<GlobalVariable>(GV);
268 if ((GV->hasSection() && StringRef(GV->getSection()).startswith(".cp.")) ||
269 (GVar && GVar->isConstant() && GV->hasLocalLinkage()))
270 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
272 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
275 static bool IsSmallObject(const GlobalValue *GV, const XCoreTargetLowering &XTL) {
276 if (XTL.getTargetMachine().getCodeModel() == CodeModel::Small)
279 Type *ObjType = GV->getType()->getPointerElementType();
280 if (!ObjType->isSized())
283 unsigned ObjSize = XTL.getDataLayout()->getTypeAllocSize(ObjType);
284 return ObjSize < CodeModelLargeSize && ObjSize != 0;
287 SDValue XCoreTargetLowering::
288 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
290 const GlobalAddressSDNode *GN = cast<GlobalAddressSDNode>(Op);
291 const GlobalValue *GV = GN->getGlobal();
293 int64_t Offset = GN->getOffset();
294 if (IsSmallObject(GV, *this)) {
295 // We can only fold positive offsets that are a multiple of the word size.
296 int64_t FoldedOffset = std::max(Offset & ~3, (int64_t)0);
297 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, FoldedOffset);
298 GA = getGlobalAddressWrapper(GA, GV, DAG);
299 // Handle the rest of the offset.
300 if (Offset != FoldedOffset) {
301 SDValue Remaining = DAG.getConstant(Offset - FoldedOffset, MVT::i32);
302 GA = DAG.getNode(ISD::ADD, DL, MVT::i32, GA, Remaining);
306 // Ideally we would not fold in offset with an index <= 11.
307 Type *Ty = Type::getInt8PtrTy(*DAG.getContext());
308 Constant *GA = ConstantExpr::getBitCast(const_cast<GlobalValue*>(GV), Ty);
309 Ty = Type::getInt32Ty(*DAG.getContext());
310 Constant *Idx = ConstantInt::get(Ty, Offset);
311 Constant *GAI = ConstantExpr::getGetElementPtr(GA, Idx);
312 SDValue CP = DAG.getConstantPool(GAI, MVT::i32);
313 return DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), CP,
314 MachinePointerInfo(), false, false, false, 0);
318 SDValue XCoreTargetLowering::
319 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
323 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
324 SDValue Result = DAG.getTargetBlockAddress(BA, getPointerTy());
326 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result);
329 SDValue XCoreTargetLowering::
330 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
332 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
333 // FIXME there isn't really debug info here
335 EVT PtrVT = Op.getValueType();
337 if (CP->isMachineConstantPoolEntry()) {
338 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
339 CP->getAlignment(), CP->getOffset());
341 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
342 CP->getAlignment(), CP->getOffset());
344 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
347 unsigned XCoreTargetLowering::getJumpTableEncoding() const {
348 return MachineJumpTableInfo::EK_Inline;
351 SDValue XCoreTargetLowering::
352 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
354 SDValue Chain = Op.getOperand(0);
355 SDValue Table = Op.getOperand(1);
356 SDValue Index = Op.getOperand(2);
358 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
359 unsigned JTI = JT->getIndex();
360 MachineFunction &MF = DAG.getMachineFunction();
361 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
362 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
364 unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size();
365 if (NumEntries <= 32) {
366 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index);
368 assert((NumEntries >> 31) == 0);
369 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
370 DAG.getConstant(1, MVT::i32));
371 return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT,
375 SDValue XCoreTargetLowering::
376 lowerLoadWordFromAlignedBasePlusOffset(SDLoc DL, SDValue Chain, SDValue Base,
377 int64_t Offset, SelectionDAG &DAG) const
379 if ((Offset & 0x3) == 0) {
380 return DAG.getLoad(getPointerTy(), DL, Chain, Base, MachinePointerInfo(),
381 false, false, false, 0);
383 // Lower to pair of consecutive word aligned loads plus some bit shifting.
384 int32_t HighOffset = RoundUpToAlignment(Offset, 4);
385 int32_t LowOffset = HighOffset - 4;
386 SDValue LowAddr, HighAddr;
387 if (GlobalAddressSDNode *GASD =
388 dyn_cast<GlobalAddressSDNode>(Base.getNode())) {
389 LowAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(),
391 HighAddr = DAG.getGlobalAddress(GASD->getGlobal(), DL, Base.getValueType(),
394 LowAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
395 DAG.getConstant(LowOffset, MVT::i32));
396 HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, Base,
397 DAG.getConstant(HighOffset, MVT::i32));
399 SDValue LowShift = DAG.getConstant((Offset - LowOffset) * 8, MVT::i32);
400 SDValue HighShift = DAG.getConstant((HighOffset - Offset) * 8, MVT::i32);
402 SDValue Low = DAG.getLoad(getPointerTy(), DL, Chain,
403 LowAddr, MachinePointerInfo(),
404 false, false, false, 0);
405 SDValue High = DAG.getLoad(getPointerTy(), DL, Chain,
406 HighAddr, MachinePointerInfo(),
407 false, false, false, 0);
408 SDValue LowShifted = DAG.getNode(ISD::SRL, DL, MVT::i32, Low, LowShift);
409 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High, HighShift);
410 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, LowShifted, HighShifted);
411 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
413 SDValue Ops[] = { Result, Chain };
414 return DAG.getMergeValues(Ops, DL);
417 static bool isWordAligned(SDValue Value, SelectionDAG &DAG)
419 APInt KnownZero, KnownOne;
420 DAG.computeKnownBits(Value, KnownZero, KnownOne);
421 return KnownZero.countTrailingOnes() >= 2;
424 SDValue XCoreTargetLowering::
425 LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
426 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
427 LoadSDNode *LD = cast<LoadSDNode>(Op);
428 assert(LD->getExtensionType() == ISD::NON_EXTLOAD &&
429 "Unexpected extension type");
430 assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT");
431 if (allowsMisalignedMemoryAccesses(LD->getMemoryVT(),
432 LD->getAddressSpace(),
436 unsigned ABIAlignment = getDataLayout()->
437 getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
438 // Leave aligned load alone.
439 if (LD->getAlignment() >= ABIAlignment)
442 SDValue Chain = LD->getChain();
443 SDValue BasePtr = LD->getBasePtr();
446 if (!LD->isVolatile()) {
447 const GlobalValue *GV;
449 if (DAG.isBaseWithConstantOffset(BasePtr) &&
450 isWordAligned(BasePtr->getOperand(0), DAG)) {
451 SDValue NewBasePtr = BasePtr->getOperand(0);
452 Offset = cast<ConstantSDNode>(BasePtr->getOperand(1))->getSExtValue();
453 return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr,
456 if (TLI.isGAPlusOffset(BasePtr.getNode(), GV, Offset) &&
457 MinAlign(GV->getAlignment(), 4) == 4) {
458 SDValue NewBasePtr = DAG.getGlobalAddress(GV, DL,
459 BasePtr->getValueType(0));
460 return lowerLoadWordFromAlignedBasePlusOffset(DL, Chain, NewBasePtr,
465 if (LD->getAlignment() == 2) {
466 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain,
467 BasePtr, LD->getPointerInfo(), MVT::i16,
468 LD->isVolatile(), LD->isNonTemporal(),
469 LD->isInvariant(), 2);
470 SDValue HighAddr = DAG.getNode(ISD::ADD, DL, MVT::i32, BasePtr,
471 DAG.getConstant(2, MVT::i32));
472 SDValue High = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
474 LD->getPointerInfo().getWithOffset(2),
475 MVT::i16, LD->isVolatile(),
476 LD->isNonTemporal(), LD->isInvariant(), 2);
477 SDValue HighShifted = DAG.getNode(ISD::SHL, DL, MVT::i32, High,
478 DAG.getConstant(16, MVT::i32));
479 SDValue Result = DAG.getNode(ISD::OR, DL, MVT::i32, Low, HighShifted);
480 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Low.getValue(1),
482 SDValue Ops[] = { Result, Chain };
483 return DAG.getMergeValues(Ops, DL);
486 // Lower to a call to __misaligned_load(BasePtr).
487 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
488 TargetLowering::ArgListTy Args;
489 TargetLowering::ArgListEntry Entry;
492 Entry.Node = BasePtr;
493 Args.push_back(Entry);
495 TargetLowering::CallLoweringInfo CLI(DAG);
496 CLI.setDebugLoc(DL).setChain(Chain)
497 .setCallee(CallingConv::C, IntPtrTy,
498 DAG.getExternalSymbol("__misaligned_load", getPointerTy()),
501 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
502 SDValue Ops[] = { CallResult.first, CallResult.second };
503 return DAG.getMergeValues(Ops, DL);
506 SDValue XCoreTargetLowering::
507 LowerSTORE(SDValue Op, SelectionDAG &DAG) const
509 StoreSDNode *ST = cast<StoreSDNode>(Op);
510 assert(!ST->isTruncatingStore() && "Unexpected store type");
511 assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT");
512 if (allowsMisalignedMemoryAccesses(ST->getMemoryVT(),
513 ST->getAddressSpace(),
514 ST->getAlignment())) {
517 unsigned ABIAlignment = getDataLayout()->
518 getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext()));
519 // Leave aligned store alone.
520 if (ST->getAlignment() >= ABIAlignment) {
523 SDValue Chain = ST->getChain();
524 SDValue BasePtr = ST->getBasePtr();
525 SDValue Value = ST->getValue();
528 if (ST->getAlignment() == 2) {
530 SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
531 DAG.getConstant(16, MVT::i32));
532 SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,
533 ST->getPointerInfo(), MVT::i16,
534 ST->isVolatile(), ST->isNonTemporal(),
536 SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
537 DAG.getConstant(2, MVT::i32));
538 SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr,
539 ST->getPointerInfo().getWithOffset(2),
540 MVT::i16, ST->isVolatile(),
541 ST->isNonTemporal(), 2);
542 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh);
545 // Lower to a call to __misaligned_store(BasePtr, Value).
546 Type *IntPtrTy = getDataLayout()->getIntPtrType(*DAG.getContext());
547 TargetLowering::ArgListTy Args;
548 TargetLowering::ArgListEntry Entry;
551 Entry.Node = BasePtr;
552 Args.push_back(Entry);
555 Args.push_back(Entry);
557 TargetLowering::CallLoweringInfo CLI(DAG);
558 CLI.setDebugLoc(dl).setChain(Chain)
559 .setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
560 DAG.getExternalSymbol("__misaligned_store", getPointerTy()),
563 std::pair<SDValue, SDValue> CallResult = LowerCallTo(CLI);
564 return CallResult.second;
567 SDValue XCoreTargetLowering::
568 LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
570 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&
571 "Unexpected operand to lower!");
573 SDValue LHS = Op.getOperand(0);
574 SDValue RHS = Op.getOperand(1);
575 SDValue Zero = DAG.getConstant(0, MVT::i32);
576 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
577 DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
579 SDValue Lo(Hi.getNode(), 1);
580 SDValue Ops[] = { Lo, Hi };
581 return DAG.getMergeValues(Ops, dl);
584 SDValue XCoreTargetLowering::
585 LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
587 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI &&
588 "Unexpected operand to lower!");
590 SDValue LHS = Op.getOperand(0);
591 SDValue RHS = Op.getOperand(1);
592 SDValue Zero = DAG.getConstant(0, MVT::i32);
593 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
594 DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
596 SDValue Lo(Hi.getNode(), 1);
597 SDValue Ops[] = { Lo, Hi };
598 return DAG.getMergeValues(Ops, dl);
601 /// isADDADDMUL - Return whether Op is in a form that is equivalent to
602 /// add(add(mul(x,y),a),b). If requireIntermediatesHaveOneUse is true then
603 /// each intermediate result in the calculation must also have a single use.
604 /// If the Op is in the correct form the constituent parts are written to Mul0,
605 /// Mul1, Addend0 and Addend1.
607 isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0,
608 SDValue &Addend1, bool requireIntermediatesHaveOneUse)
610 if (Op.getOpcode() != ISD::ADD)
612 SDValue N0 = Op.getOperand(0);
613 SDValue N1 = Op.getOperand(1);
616 if (N0.getOpcode() == ISD::ADD) {
619 } else if (N1.getOpcode() == ISD::ADD) {
625 if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse())
627 if (OtherOp.getOpcode() == ISD::MUL) {
628 // add(add(a,b),mul(x,y))
629 if (requireIntermediatesHaveOneUse && !OtherOp.hasOneUse())
631 Mul0 = OtherOp.getOperand(0);
632 Mul1 = OtherOp.getOperand(1);
633 Addend0 = AddOp.getOperand(0);
634 Addend1 = AddOp.getOperand(1);
637 if (AddOp.getOperand(0).getOpcode() == ISD::MUL) {
638 // add(add(mul(x,y),a),b)
639 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(0).hasOneUse())
641 Mul0 = AddOp.getOperand(0).getOperand(0);
642 Mul1 = AddOp.getOperand(0).getOperand(1);
643 Addend0 = AddOp.getOperand(1);
647 if (AddOp.getOperand(1).getOpcode() == ISD::MUL) {
648 // add(add(a,mul(x,y)),b)
649 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(1).hasOneUse())
651 Mul0 = AddOp.getOperand(1).getOperand(0);
652 Mul1 = AddOp.getOperand(1).getOperand(1);
653 Addend0 = AddOp.getOperand(0);
660 SDValue XCoreTargetLowering::
661 TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
665 if (N->getOperand(0).getOpcode() == ISD::MUL) {
666 Mul = N->getOperand(0);
667 Other = N->getOperand(1);
668 } else if (N->getOperand(1).getOpcode() == ISD::MUL) {
669 Mul = N->getOperand(1);
670 Other = N->getOperand(0);
675 SDValue LL, RL, AddendL, AddendH;
676 LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
677 Mul.getOperand(0), DAG.getConstant(0, MVT::i32));
678 RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
679 Mul.getOperand(1), DAG.getConstant(0, MVT::i32));
680 AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
681 Other, DAG.getConstant(0, MVT::i32));
682 AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
683 Other, DAG.getConstant(1, MVT::i32));
684 APInt HighMask = APInt::getHighBitsSet(64, 32);
685 unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0));
686 unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1));
687 if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) &&
688 DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) {
689 // The inputs are both zero-extended.
690 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
691 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
693 SDValue Lo(Hi.getNode(), 1);
694 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
696 if (LHSSB > 32 && RHSSB > 32) {
697 // The inputs are both sign-extended.
698 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
699 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
701 SDValue Lo(Hi.getNode(), 1);
702 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
705 LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
706 Mul.getOperand(0), DAG.getConstant(1, MVT::i32));
707 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
708 Mul.getOperand(1), DAG.getConstant(1, MVT::i32));
709 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
710 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
712 SDValue Lo(Hi.getNode(), 1);
713 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH);
714 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL);
715 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH);
716 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH);
717 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
720 SDValue XCoreTargetLowering::
721 ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
723 assert(N->getValueType(0) == MVT::i64 &&
724 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
725 "Unknown operand to lower!");
727 if (N->getOpcode() == ISD::ADD) {
728 SDValue Result = TryExpandADDWithMul(N, DAG);
729 if (Result.getNode())
735 // Extract components
736 SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
737 N->getOperand(0), DAG.getConstant(0, MVT::i32));
738 SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
739 N->getOperand(0), DAG.getConstant(1, MVT::i32));
740 SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
741 N->getOperand(1), DAG.getConstant(0, MVT::i32));
742 SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
743 N->getOperand(1), DAG.getConstant(1, MVT::i32));
746 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
748 SDValue Zero = DAG.getConstant(0, MVT::i32);
749 SDValue Lo = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
751 SDValue Carry(Lo.getNode(), 1);
753 SDValue Hi = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
755 SDValue Ignored(Hi.getNode(), 1);
757 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
760 SDValue XCoreTargetLowering::
761 LowerVAARG(SDValue Op, SelectionDAG &DAG) const
763 // Whist llvm does not support aggregate varargs we can ignore
764 // the possibility of the ValueType being an implicit byVal vararg.
765 SDNode *Node = Op.getNode();
766 EVT VT = Node->getValueType(0); // not an aggregate
767 SDValue InChain = Node->getOperand(0);
768 SDValue VAListPtr = Node->getOperand(1);
769 EVT PtrVT = VAListPtr.getValueType();
770 const Value *SV = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
772 SDValue VAList = DAG.getLoad(PtrVT, dl, InChain,
773 VAListPtr, MachinePointerInfo(SV),
774 false, false, false, 0);
775 // Increment the pointer, VAList, to the next vararg
776 SDValue nextPtr = DAG.getNode(ISD::ADD, dl, PtrVT, VAList,
777 DAG.getIntPtrConstant(VT.getSizeInBits() / 8));
778 // Store the incremented VAList to the legalized pointer
779 InChain = DAG.getStore(VAList.getValue(1), dl, nextPtr, VAListPtr,
780 MachinePointerInfo(SV), false, false, 0);
781 // Load the actual argument out of the pointer VAList
782 return DAG.getLoad(VT, dl, InChain, VAList, MachinePointerInfo(),
783 false, false, false, 0);
786 SDValue XCoreTargetLowering::
787 LowerVASTART(SDValue Op, SelectionDAG &DAG) const
790 // vastart stores the address of the VarArgsFrameIndex slot into the
791 // memory location argument
792 MachineFunction &MF = DAG.getMachineFunction();
793 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
794 SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32);
795 return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1),
796 MachinePointerInfo(), false, false, 0);
799 SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op,
800 SelectionDAG &DAG) const {
801 // This nodes represent llvm.frameaddress on the DAG.
802 // It takes one operand, the index of the frame address to return.
803 // An index of zero corresponds to the current function's frame address.
804 // An index of one to the parent's frame address, and so on.
805 // Depths > 0 not supported yet!
806 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
809 MachineFunction &MF = DAG.getMachineFunction();
810 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
811 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(Op),
812 RegInfo->getFrameRegister(MF), MVT::i32);
815 SDValue XCoreTargetLowering::
816 LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const {
817 // This nodes represent llvm.returnaddress on the DAG.
818 // It takes one operand, the index of the return address to return.
819 // An index of zero corresponds to the current function's return address.
820 // An index of one to the parent's return address, and so on.
821 // Depths > 0 not supported yet!
822 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
825 MachineFunction &MF = DAG.getMachineFunction();
826 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
827 int FI = XFI->createLRSpillSlot(MF);
828 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
829 return DAG.getLoad(getPointerTy(), SDLoc(Op), DAG.getEntryNode(), FIN,
830 MachinePointerInfo::getFixedStack(FI), false, false,
834 SDValue XCoreTargetLowering::
835 LowerFRAME_TO_ARGS_OFFSET(SDValue Op, SelectionDAG &DAG) const {
836 // This node represents offset from frame pointer to first on-stack argument.
837 // This is needed for correct stack adjustment during unwind.
838 // However, we don't know the offset until after the frame has be finalised.
839 // This is done during the XCoreFTAOElim pass.
840 return DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, SDLoc(Op), MVT::i32);
843 SDValue XCoreTargetLowering::
844 LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const {
845 // OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER)
846 // This node represents 'eh_return' gcc dwarf builtin, which is used to
847 // return from exception. The general meaning is: adjust stack by OFFSET and
848 // pass execution to HANDLER.
849 MachineFunction &MF = DAG.getMachineFunction();
850 SDValue Chain = Op.getOperand(0);
851 SDValue Offset = Op.getOperand(1);
852 SDValue Handler = Op.getOperand(2);
855 // Absolute SP = (FP + FrameToArgs) + Offset
856 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
857 SDValue Stack = DAG.getCopyFromReg(DAG.getEntryNode(), dl,
858 RegInfo->getFrameRegister(MF), MVT::i32);
859 SDValue FrameToArgs = DAG.getNode(XCoreISD::FRAME_TO_ARGS_OFFSET, dl,
861 Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, FrameToArgs);
862 Stack = DAG.getNode(ISD::ADD, dl, MVT::i32, Stack, Offset);
864 // R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
865 // which leaves 2 caller saved registers, R2 & R3 for us to use.
866 unsigned StackReg = XCore::R2;
867 unsigned HandlerReg = XCore::R3;
869 SDValue OutChains[] = {
870 DAG.getCopyToReg(Chain, dl, StackReg, Stack),
871 DAG.getCopyToReg(Chain, dl, HandlerReg, Handler)
874 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
876 return DAG.getNode(XCoreISD::EH_RETURN, dl, MVT::Other, Chain,
877 DAG.getRegister(StackReg, MVT::i32),
878 DAG.getRegister(HandlerReg, MVT::i32));
882 SDValue XCoreTargetLowering::
883 LowerADJUST_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
884 return Op.getOperand(0);
887 SDValue XCoreTargetLowering::
888 LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
889 SDValue Chain = Op.getOperand(0);
890 SDValue Trmp = Op.getOperand(1); // trampoline
891 SDValue FPtr = Op.getOperand(2); // nested function
892 SDValue Nest = Op.getOperand(3); // 'nest' parameter value
894 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
897 // LDAPF_u10 r11, nest
898 // LDW_2rus r11, r11[0]
899 // STWSP_ru6 r11, sp[0]
900 // LDAPF_u10 r11, fptr
901 // LDW_2rus r11, r11[0]
907 SDValue OutChains[5];
912 OutChains[0] = DAG.getStore(Chain, dl, DAG.getConstant(0x0a3cd805, MVT::i32),
913 Addr, MachinePointerInfo(TrmpAddr), false, false,
916 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
917 DAG.getConstant(4, MVT::i32));
918 OutChains[1] = DAG.getStore(Chain, dl, DAG.getConstant(0xd80456c0, MVT::i32),
919 Addr, MachinePointerInfo(TrmpAddr, 4), false,
922 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
923 DAG.getConstant(8, MVT::i32));
924 OutChains[2] = DAG.getStore(Chain, dl, DAG.getConstant(0x27fb0a3c, MVT::i32),
925 Addr, MachinePointerInfo(TrmpAddr, 8), false,
928 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
929 DAG.getConstant(12, MVT::i32));
930 OutChains[3] = DAG.getStore(Chain, dl, Nest, Addr,
931 MachinePointerInfo(TrmpAddr, 12), false, false,
934 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp,
935 DAG.getConstant(16, MVT::i32));
936 OutChains[4] = DAG.getStore(Chain, dl, FPtr, Addr,
937 MachinePointerInfo(TrmpAddr, 16), false, false,
940 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains);
943 SDValue XCoreTargetLowering::
944 LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const {
946 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
948 case Intrinsic::xcore_crc8:
949 EVT VT = Op.getValueType();
951 DAG.getNode(XCoreISD::CRC8, DL, DAG.getVTList(VT, VT),
952 Op.getOperand(1), Op.getOperand(2) , Op.getOperand(3));
953 SDValue Crc(Data.getNode(), 1);
954 SDValue Results[] = { Crc, Data };
955 return DAG.getMergeValues(Results, DL);
960 SDValue XCoreTargetLowering::
961 LowerATOMIC_FENCE(SDValue Op, SelectionDAG &DAG) const {
963 return DAG.getNode(XCoreISD::MEMBARRIER, DL, MVT::Other, Op.getOperand(0));
966 SDValue XCoreTargetLowering::
967 LowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const {
968 AtomicSDNode *N = cast<AtomicSDNode>(Op);
969 assert(N->getOpcode() == ISD::ATOMIC_LOAD && "Bad Atomic OP");
970 assert(N->getOrdering() <= Monotonic &&
971 "setInsertFencesForAtomic(true) and yet greater than Monotonic");
972 if (N->getMemoryVT() == MVT::i32) {
973 if (N->getAlignment() < 4)
974 report_fatal_error("atomic load must be aligned");
975 return DAG.getLoad(getPointerTy(), SDLoc(Op), N->getChain(),
976 N->getBasePtr(), N->getPointerInfo(),
977 N->isVolatile(), N->isNonTemporal(),
978 N->isInvariant(), N->getAlignment(),
979 N->getAAInfo(), N->getRanges());
981 if (N->getMemoryVT() == MVT::i16) {
982 if (N->getAlignment() < 2)
983 report_fatal_error("atomic load must be aligned");
984 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(),
985 N->getBasePtr(), N->getPointerInfo(), MVT::i16,
986 N->isVolatile(), N->isNonTemporal(),
987 N->isInvariant(), N->getAlignment(), N->getAAInfo());
989 if (N->getMemoryVT() == MVT::i8)
990 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), MVT::i32, N->getChain(),
991 N->getBasePtr(), N->getPointerInfo(), MVT::i8,
992 N->isVolatile(), N->isNonTemporal(),
993 N->isInvariant(), N->getAlignment(), N->getAAInfo());
997 SDValue XCoreTargetLowering::
998 LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const {
999 AtomicSDNode *N = cast<AtomicSDNode>(Op);
1000 assert(N->getOpcode() == ISD::ATOMIC_STORE && "Bad Atomic OP");
1001 assert(N->getOrdering() <= Monotonic &&
1002 "setInsertFencesForAtomic(true) and yet greater than Monotonic");
1003 if (N->getMemoryVT() == MVT::i32) {
1004 if (N->getAlignment() < 4)
1005 report_fatal_error("atomic store must be aligned");
1006 return DAG.getStore(N->getChain(), SDLoc(Op), N->getVal(),
1007 N->getBasePtr(), N->getPointerInfo(),
1008 N->isVolatile(), N->isNonTemporal(),
1009 N->getAlignment(), N->getAAInfo());
1011 if (N->getMemoryVT() == MVT::i16) {
1012 if (N->getAlignment() < 2)
1013 report_fatal_error("atomic store must be aligned");
1014 return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(),
1015 N->getBasePtr(), N->getPointerInfo(), MVT::i16,
1016 N->isVolatile(), N->isNonTemporal(),
1017 N->getAlignment(), N->getAAInfo());
1019 if (N->getMemoryVT() == MVT::i8)
1020 return DAG.getTruncStore(N->getChain(), SDLoc(Op), N->getVal(),
1021 N->getBasePtr(), N->getPointerInfo(), MVT::i8,
1022 N->isVolatile(), N->isNonTemporal(),
1023 N->getAlignment(), N->getAAInfo());
1027 //===----------------------------------------------------------------------===//
1028 // Calling Convention Implementation
1029 //===----------------------------------------------------------------------===//
1031 #include "XCoreGenCallingConv.inc"
1033 //===----------------------------------------------------------------------===//
1034 // Call Calling Convention Implementation
1035 //===----------------------------------------------------------------------===//
1037 /// XCore call implementation
1039 XCoreTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1040 SmallVectorImpl<SDValue> &InVals) const {
1041 SelectionDAG &DAG = CLI.DAG;
1043 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1044 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1045 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1046 SDValue Chain = CLI.Chain;
1047 SDValue Callee = CLI.Callee;
1048 bool &isTailCall = CLI.IsTailCall;
1049 CallingConv::ID CallConv = CLI.CallConv;
1050 bool isVarArg = CLI.IsVarArg;
1052 // XCore target does not yet support tail call optimization.
1055 // For now, only CallingConv::C implemented
1059 llvm_unreachable("Unsupported calling convention");
1060 case CallingConv::Fast:
1061 case CallingConv::C:
1062 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
1063 Outs, OutVals, Ins, dl, DAG, InVals);
1067 /// LowerCallResult - Lower the result values of a call into the
1068 /// appropriate copies out of appropriate physical registers / memory locations.
1070 LowerCallResult(SDValue Chain, SDValue InFlag,
1071 const SmallVectorImpl<CCValAssign> &RVLocs,
1072 SDLoc dl, SelectionDAG &DAG,
1073 SmallVectorImpl<SDValue> &InVals) {
1074 SmallVector<std::pair<int, unsigned>, 4> ResultMemLocs;
1075 // Copy results out of physical registers.
1076 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1077 const CCValAssign &VA = RVLocs[i];
1078 if (VA.isRegLoc()) {
1079 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), VA.getValVT(),
1080 InFlag).getValue(1);
1081 InFlag = Chain.getValue(2);
1082 InVals.push_back(Chain.getValue(0));
1084 assert(VA.isMemLoc());
1085 ResultMemLocs.push_back(std::make_pair(VA.getLocMemOffset(),
1087 // Reserve space for this result.
1088 InVals.push_back(SDValue());
1092 // Copy results out of memory.
1093 SmallVector<SDValue, 4> MemOpChains;
1094 for (unsigned i = 0, e = ResultMemLocs.size(); i != e; ++i) {
1095 int offset = ResultMemLocs[i].first;
1096 unsigned index = ResultMemLocs[i].second;
1097 SDVTList VTs = DAG.getVTList(MVT::i32, MVT::Other);
1098 SDValue Ops[] = { Chain, DAG.getConstant(offset / 4, MVT::i32) };
1099 SDValue load = DAG.getNode(XCoreISD::LDWSP, dl, VTs, Ops);
1100 InVals[index] = load;
1101 MemOpChains.push_back(load.getValue(1));
1104 // Transform all loads nodes into one single node because
1105 // all load nodes are independent of each other.
1106 if (!MemOpChains.empty())
1107 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1112 /// LowerCCCCallTo - functions arguments are copied from virtual
1113 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
1114 /// CALLSEQ_END are emitted.
1115 /// TODO: isTailCall, sret.
1117 XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
1118 CallingConv::ID CallConv, bool isVarArg,
1120 const SmallVectorImpl<ISD::OutputArg> &Outs,
1121 const SmallVectorImpl<SDValue> &OutVals,
1122 const SmallVectorImpl<ISD::InputArg> &Ins,
1123 SDLoc dl, SelectionDAG &DAG,
1124 SmallVectorImpl<SDValue> &InVals) const {
1126 // Analyze operands of the call, assigning locations to each operand.
1127 SmallVector<CCValAssign, 16> ArgLocs;
1128 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1131 // The ABI dictates there should be one stack slot available to the callee
1132 // on function entry (for saving lr).
1133 CCInfo.AllocateStack(4, 4);
1135 CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
1137 SmallVector<CCValAssign, 16> RVLocs;
1138 // Analyze return values to determine the number of bytes of stack required.
1139 CCState RetCCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1141 RetCCInfo.AllocateStack(CCInfo.getNextStackOffset(), 4);
1142 RetCCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
1144 // Get a count of how many bytes are to be pushed on the stack.
1145 unsigned NumBytes = RetCCInfo.getNextStackOffset();
1147 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
1148 getPointerTy(), true), dl);
1150 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
1151 SmallVector<SDValue, 12> MemOpChains;
1153 // Walk the register/memloc assignments, inserting copies/loads.
1154 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1155 CCValAssign &VA = ArgLocs[i];
1156 SDValue Arg = OutVals[i];
1158 // Promote the value if needed.
1159 switch (VA.getLocInfo()) {
1160 default: llvm_unreachable("Unknown loc info!");
1161 case CCValAssign::Full: break;
1162 case CCValAssign::SExt:
1163 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
1165 case CCValAssign::ZExt:
1166 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
1168 case CCValAssign::AExt:
1169 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
1173 // Arguments that can be passed on register must be kept at
1174 // RegsToPass vector
1175 if (VA.isRegLoc()) {
1176 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
1178 assert(VA.isMemLoc());
1180 int Offset = VA.getLocMemOffset();
1182 MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
1184 DAG.getConstant(Offset/4, MVT::i32)));
1188 // Transform all store nodes into one single node because
1189 // all store nodes are independent of each other.
1190 if (!MemOpChains.empty())
1191 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1193 // Build a sequence of copy-to-reg nodes chained together with token
1194 // chain and flag operands which copy the outgoing args into registers.
1195 // The InFlag in necessary since all emitted instructions must be
1198 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
1199 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
1200 RegsToPass[i].second, InFlag);
1201 InFlag = Chain.getValue(1);
1204 // If the callee is a GlobalAddress node (quite common, every direct call is)
1205 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
1206 // Likewise ExternalSymbol -> TargetExternalSymbol.
1207 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
1208 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, MVT::i32);
1209 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
1210 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
1212 // XCoreBranchLink = #chain, #target_address, #opt_in_flags...
1213 // = Chain, Callee, Reg#1, Reg#2, ...
1215 // Returns a chain & a flag for retval copy to use.
1216 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1217 SmallVector<SDValue, 8> Ops;
1218 Ops.push_back(Chain);
1219 Ops.push_back(Callee);
1221 // Add argument registers to the end of the list so that they are
1222 // known live into the call.
1223 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
1224 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
1225 RegsToPass[i].second.getValueType()));
1227 if (InFlag.getNode())
1228 Ops.push_back(InFlag);
1230 Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, Ops);
1231 InFlag = Chain.getValue(1);
1233 // Create the CALLSEQ_END node.
1234 Chain = DAG.getCALLSEQ_END(Chain,
1235 DAG.getConstant(NumBytes, getPointerTy(), true),
1236 DAG.getConstant(0, getPointerTy(), true),
1238 InFlag = Chain.getValue(1);
1240 // Handle result values, copying them out of physregs into vregs that we
1242 return LowerCallResult(Chain, InFlag, RVLocs, dl, DAG, InVals);
1245 //===----------------------------------------------------------------------===//
1246 // Formal Arguments Calling Convention Implementation
1247 //===----------------------------------------------------------------------===//
1250 struct ArgDataPair { SDValue SDV; ISD::ArgFlagsTy Flags; };
1253 /// XCore formal arguments implementation
1255 XCoreTargetLowering::LowerFormalArguments(SDValue Chain,
1256 CallingConv::ID CallConv,
1258 const SmallVectorImpl<ISD::InputArg> &Ins,
1261 SmallVectorImpl<SDValue> &InVals)
1266 llvm_unreachable("Unsupported calling convention");
1267 case CallingConv::C:
1268 case CallingConv::Fast:
1269 return LowerCCCArguments(Chain, CallConv, isVarArg,
1270 Ins, dl, DAG, InVals);
1274 /// LowerCCCArguments - transform physical registers into
1275 /// virtual registers and generate load operations for
1276 /// arguments places on the stack.
1279 XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
1280 CallingConv::ID CallConv,
1282 const SmallVectorImpl<ISD::InputArg>
1286 SmallVectorImpl<SDValue> &InVals) const {
1287 MachineFunction &MF = DAG.getMachineFunction();
1288 MachineFrameInfo *MFI = MF.getFrameInfo();
1289 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1290 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
1292 // Assign locations to all of the incoming arguments.
1293 SmallVector<CCValAssign, 16> ArgLocs;
1294 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
1297 CCInfo.AnalyzeFormalArguments(Ins, CC_XCore);
1299 unsigned StackSlotSize = XCoreFrameLowering::stackSlotSize();
1301 unsigned LRSaveSize = StackSlotSize;
1304 XFI->setReturnStackOffset(CCInfo.getNextStackOffset() + LRSaveSize);
1306 // All getCopyFromReg ops must precede any getMemcpys to prevent the
1307 // scheduler clobbering a register before it has been copied.
1309 // 1. CopyFromReg (and load) arg & vararg registers.
1310 // 2. Chain CopyFromReg nodes into a TokenFactor.
1311 // 3. Memcpy 'byVal' args & push final InVals.
1312 // 4. Chain mem ops nodes into a TokenFactor.
1313 SmallVector<SDValue, 4> CFRegNode;
1314 SmallVector<ArgDataPair, 4> ArgData;
1315 SmallVector<SDValue, 4> MemOps;
1317 // 1a. CopyFromReg (and load) arg registers.
1318 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1320 CCValAssign &VA = ArgLocs[i];
1323 if (VA.isRegLoc()) {
1324 // Arguments passed in registers
1325 EVT RegVT = VA.getLocVT();
1326 switch (RegVT.getSimpleVT().SimpleTy) {
1330 errs() << "LowerFormalArguments Unhandled argument type: "
1331 << RegVT.getSimpleVT().SimpleTy << "\n";
1333 llvm_unreachable(nullptr);
1336 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
1337 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1338 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
1339 CFRegNode.push_back(ArgIn.getValue(ArgIn->getNumValues() - 1));
1343 assert(VA.isMemLoc());
1344 // Load the argument to a virtual register
1345 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
1346 if (ObjSize > StackSlotSize) {
1347 errs() << "LowerFormalArguments Unhandled argument type: "
1348 << EVT(VA.getLocVT()).getEVTString()
1351 // Create the frame index object for this incoming parameter...
1352 int FI = MFI->CreateFixedObject(ObjSize,
1353 LRSaveSize + VA.getLocMemOffset(),
1356 // Create the SelectionDAG nodes corresponding to a load
1357 //from this parameter
1358 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1359 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN,
1360 MachinePointerInfo::getFixedStack(FI),
1361 false, false, false, 0);
1363 const ArgDataPair ADP = { ArgIn, Ins[i].Flags };
1364 ArgData.push_back(ADP);
1367 // 1b. CopyFromReg vararg registers.
1369 // Argument registers
1370 static const MCPhysReg ArgRegs[] = {
1371 XCore::R0, XCore::R1, XCore::R2, XCore::R3
1373 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
1374 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs,
1375 array_lengthof(ArgRegs));
1376 if (FirstVAReg < array_lengthof(ArgRegs)) {
1378 // Save remaining registers, storing higher register numbers at a higher
1380 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) {
1381 // Create a stack slot
1382 int FI = MFI->CreateFixedObject(4, offset, true);
1383 if (i == (int)FirstVAReg) {
1384 XFI->setVarArgsFrameIndex(FI);
1386 offset -= StackSlotSize;
1387 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1388 // Move argument from phys reg -> virt reg
1389 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass);
1390 RegInfo.addLiveIn(ArgRegs[i], VReg);
1391 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1392 CFRegNode.push_back(Val.getValue(Val->getNumValues() - 1));
1393 // Move argument from virt reg -> stack
1394 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
1395 MachinePointerInfo(), false, false, 0);
1396 MemOps.push_back(Store);
1399 // This will point to the next argument passed via stack.
1400 XFI->setVarArgsFrameIndex(
1401 MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(),
1406 // 2. chain CopyFromReg nodes into a TokenFactor.
1407 if (!CFRegNode.empty())
1408 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, CFRegNode);
1410 // 3. Memcpy 'byVal' args & push final InVals.
1411 // Aggregates passed "byVal" need to be copied by the callee.
1412 // The callee will use a pointer to this copy, rather than the original
1414 for (SmallVectorImpl<ArgDataPair>::const_iterator ArgDI = ArgData.begin(),
1415 ArgDE = ArgData.end();
1416 ArgDI != ArgDE; ++ArgDI) {
1417 if (ArgDI->Flags.isByVal() && ArgDI->Flags.getByValSize()) {
1418 unsigned Size = ArgDI->Flags.getByValSize();
1419 unsigned Align = std::max(StackSlotSize, ArgDI->Flags.getByValAlign());
1420 // Create a new object on the stack and copy the pointee into it.
1421 int FI = MFI->CreateStackObject(Size, Align, false);
1422 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1423 InVals.push_back(FIN);
1424 MemOps.push_back(DAG.getMemcpy(Chain, dl, FIN, ArgDI->SDV,
1425 DAG.getConstant(Size, MVT::i32),
1426 Align, false, false,
1427 MachinePointerInfo(),
1428 MachinePointerInfo()));
1430 InVals.push_back(ArgDI->SDV);
1434 // 4, chain mem ops nodes into a TokenFactor.
1435 if (!MemOps.empty()) {
1436 MemOps.push_back(Chain);
1437 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOps);
1443 //===----------------------------------------------------------------------===//
1444 // Return Value Calling Convention Implementation
1445 //===----------------------------------------------------------------------===//
1447 bool XCoreTargetLowering::
1448 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
1450 const SmallVectorImpl<ISD::OutputArg> &Outs,
1451 LLVMContext &Context) const {
1452 SmallVector<CCValAssign, 16> RVLocs;
1453 CCState CCInfo(CallConv, isVarArg, MF, RVLocs, Context);
1454 if (!CCInfo.CheckReturn(Outs, RetCC_XCore))
1456 if (CCInfo.getNextStackOffset() != 0 && isVarArg)
1462 XCoreTargetLowering::LowerReturn(SDValue Chain,
1463 CallingConv::ID CallConv, bool isVarArg,
1464 const SmallVectorImpl<ISD::OutputArg> &Outs,
1465 const SmallVectorImpl<SDValue> &OutVals,
1466 SDLoc dl, SelectionDAG &DAG) const {
1468 XCoreFunctionInfo *XFI =
1469 DAG.getMachineFunction().getInfo<XCoreFunctionInfo>();
1470 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
1472 // CCValAssign - represent the assignment of
1473 // the return value to a location
1474 SmallVector<CCValAssign, 16> RVLocs;
1476 // CCState - Info about the registers and stack slot.
1477 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1480 // Analyze return values.
1482 CCInfo.AllocateStack(XFI->getReturnStackOffset(), 4);
1484 CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
1487 SmallVector<SDValue, 4> RetOps(1, Chain);
1489 // Return on XCore is always a "retsp 0"
1490 RetOps.push_back(DAG.getConstant(0, MVT::i32));
1492 SmallVector<SDValue, 4> MemOpChains;
1493 // Handle return values that must be copied to memory.
1494 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1495 CCValAssign &VA = RVLocs[i];
1498 assert(VA.isMemLoc());
1500 report_fatal_error("Can't return value from vararg function in memory");
1503 int Offset = VA.getLocMemOffset();
1504 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8;
1505 // Create the frame index object for the memory location.
1506 int FI = MFI->CreateFixedObject(ObjSize, Offset, false);
1508 // Create a SelectionDAG node corresponding to a store
1509 // to this memory location.
1510 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1511 MemOpChains.push_back(DAG.getStore(Chain, dl, OutVals[i], FIN,
1512 MachinePointerInfo::getFixedStack(FI), false, false,
1516 // Transform all store nodes into one single node because
1517 // all stores are independent of each other.
1518 if (!MemOpChains.empty())
1519 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, MemOpChains);
1521 // Now handle return values copied to registers.
1522 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
1523 CCValAssign &VA = RVLocs[i];
1526 // Copy the result values into the output registers.
1527 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), OutVals[i], Flag);
1529 // guarantee that all emitted copies are
1530 // stuck together, avoiding something bad
1531 Flag = Chain.getValue(1);
1532 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1535 RetOps[0] = Chain; // Update chain.
1537 // Add the flag if we have it.
1539 RetOps.push_back(Flag);
1541 return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other, RetOps);
1544 //===----------------------------------------------------------------------===//
1545 // Other Lowering Code
1546 //===----------------------------------------------------------------------===//
1549 XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1550 MachineBasicBlock *BB) const {
1551 const TargetInstrInfo &TII = *Subtarget.getInstrInfo();
1552 DebugLoc dl = MI->getDebugLoc();
1553 assert((MI->getOpcode() == XCore::SELECT_CC) &&
1554 "Unexpected instr type to insert");
1556 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1557 // control-flow pattern. The incoming instruction knows the destination vreg
1558 // to set, the condition code register to branch on, the true/false values to
1559 // select between, and a branch opcode to use.
1560 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1561 MachineFunction::iterator It = BB;
1567 // cmpTY ccX, r1, r2
1569 // fallthrough --> copy0MBB
1570 MachineBasicBlock *thisMBB = BB;
1571 MachineFunction *F = BB->getParent();
1572 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1573 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1574 F->insert(It, copy0MBB);
1575 F->insert(It, sinkMBB);
1577 // Transfer the remainder of BB and its successor edges to sinkMBB.
1578 sinkMBB->splice(sinkMBB->begin(), BB,
1579 std::next(MachineBasicBlock::iterator(MI)), BB->end());
1580 sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
1582 // Next, add the true and fallthrough blocks as its successors.
1583 BB->addSuccessor(copy0MBB);
1584 BB->addSuccessor(sinkMBB);
1586 BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
1587 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
1590 // %FalseValue = ...
1591 // # fallthrough to sinkMBB
1594 // Update machine-CFG edges
1595 BB->addSuccessor(sinkMBB);
1598 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1601 BuildMI(*BB, BB->begin(), dl,
1602 TII.get(XCore::PHI), MI->getOperand(0).getReg())
1603 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
1604 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1606 MI->eraseFromParent(); // The pseudo instruction is gone now.
1610 //===----------------------------------------------------------------------===//
1611 // Target Optimization Hooks
1612 //===----------------------------------------------------------------------===//
1614 SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
1615 DAGCombinerInfo &DCI) const {
1616 SelectionDAG &DAG = DCI.DAG;
1618 switch (N->getOpcode()) {
1620 case ISD::INTRINSIC_VOID:
1621 switch (cast<ConstantSDNode>(N->getOperand(1))->getZExtValue()) {
1622 case Intrinsic::xcore_outt:
1623 case Intrinsic::xcore_outct:
1624 case Intrinsic::xcore_chkct: {
1625 SDValue OutVal = N->getOperand(3);
1626 // These instructions ignore the high bits.
1627 if (OutVal.hasOneUse()) {
1628 unsigned BitWidth = OutVal.getValueSizeInBits();
1629 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 8);
1630 APInt KnownZero, KnownOne;
1631 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1632 !DCI.isBeforeLegalizeOps());
1633 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1634 if (TLO.ShrinkDemandedConstant(OutVal, DemandedMask) ||
1635 TLI.SimplifyDemandedBits(OutVal, DemandedMask, KnownZero, KnownOne,
1637 DCI.CommitTargetLoweringOpt(TLO);
1641 case Intrinsic::xcore_setpt: {
1642 SDValue Time = N->getOperand(3);
1643 // This instruction ignores the high bits.
1644 if (Time.hasOneUse()) {
1645 unsigned BitWidth = Time.getValueSizeInBits();
1646 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, 16);
1647 APInt KnownZero, KnownOne;
1648 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
1649 !DCI.isBeforeLegalizeOps());
1650 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
1651 if (TLO.ShrinkDemandedConstant(Time, DemandedMask) ||
1652 TLI.SimplifyDemandedBits(Time, DemandedMask, KnownZero, KnownOne,
1654 DCI.CommitTargetLoweringOpt(TLO);
1660 case XCoreISD::LADD: {
1661 SDValue N0 = N->getOperand(0);
1662 SDValue N1 = N->getOperand(1);
1663 SDValue N2 = N->getOperand(2);
1664 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1665 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1666 EVT VT = N0.getValueType();
1668 // canonicalize constant to RHS
1670 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2);
1672 // fold (ladd 0, 0, x) -> 0, x & 1
1673 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1674 SDValue Carry = DAG.getConstant(0, VT);
1675 SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
1676 DAG.getConstant(1, VT));
1677 SDValue Ops[] = { Result, Carry };
1678 return DAG.getMergeValues(Ops, dl);
1681 // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the
1683 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) {
1684 APInt KnownZero, KnownOne;
1685 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1686 VT.getSizeInBits() - 1);
1687 DAG.computeKnownBits(N2, KnownZero, KnownOne);
1688 if ((KnownZero & Mask) == Mask) {
1689 SDValue Carry = DAG.getConstant(0, VT);
1690 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
1691 SDValue Ops[] = { Result, Carry };
1692 return DAG.getMergeValues(Ops, dl);
1697 case XCoreISD::LSUB: {
1698 SDValue N0 = N->getOperand(0);
1699 SDValue N1 = N->getOperand(1);
1700 SDValue N2 = N->getOperand(2);
1701 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1702 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1703 EVT VT = N0.getValueType();
1705 // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set
1706 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1707 APInt KnownZero, KnownOne;
1708 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1709 VT.getSizeInBits() - 1);
1710 DAG.computeKnownBits(N2, KnownZero, KnownOne);
1711 if ((KnownZero & Mask) == Mask) {
1712 SDValue Borrow = N2;
1713 SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
1714 DAG.getConstant(0, VT), N2);
1715 SDValue Ops[] = { Result, Borrow };
1716 return DAG.getMergeValues(Ops, dl);
1720 // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the
1722 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 1)) {
1723 APInt KnownZero, KnownOne;
1724 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1725 VT.getSizeInBits() - 1);
1726 DAG.computeKnownBits(N2, KnownZero, KnownOne);
1727 if ((KnownZero & Mask) == Mask) {
1728 SDValue Borrow = DAG.getConstant(0, VT);
1729 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
1730 SDValue Ops[] = { Result, Borrow };
1731 return DAG.getMergeValues(Ops, dl);
1736 case XCoreISD::LMUL: {
1737 SDValue N0 = N->getOperand(0);
1738 SDValue N1 = N->getOperand(1);
1739 SDValue N2 = N->getOperand(2);
1740 SDValue N3 = N->getOperand(3);
1741 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1742 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1743 EVT VT = N0.getValueType();
1744 // Canonicalize multiplicative constant to RHS. If both multiplicative
1745 // operands are constant canonicalize smallest to RHS.
1746 if ((N0C && !N1C) ||
1747 (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue()))
1748 return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT),
1752 if (N1C && N1C->isNullValue()) {
1753 // If the high result is unused fold to add(a, b)
1754 if (N->hasNUsesOfValue(0, 0)) {
1755 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3);
1756 SDValue Ops[] = { Lo, Lo };
1757 return DAG.getMergeValues(Ops, dl);
1759 // Otherwise fold to ladd(a, b, 0)
1761 DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1);
1762 SDValue Carry(Result.getNode(), 1);
1763 SDValue Ops[] = { Carry, Result };
1764 return DAG.getMergeValues(Ops, dl);
1769 // Fold 32 bit expressions such as add(add(mul(x,y),a),b) ->
1770 // lmul(x, y, a, b). The high result of lmul will be ignored.
1771 // This is only profitable if the intermediate results are unused
1773 SDValue Mul0, Mul1, Addend0, Addend1;
1774 if (N->getValueType(0) == MVT::i32 &&
1775 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) {
1776 SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl,
1777 DAG.getVTList(MVT::i32, MVT::i32), Mul0,
1778 Mul1, Addend0, Addend1);
1779 SDValue Result(Ignored.getNode(), 1);
1782 APInt HighMask = APInt::getHighBitsSet(64, 32);
1783 // Fold 64 bit expression such as add(add(mul(x,y),a),b) ->
1784 // lmul(x, y, a, b) if all operands are zero-extended. We do this
1785 // before type legalization as it is messy to match the operands after
1787 if (N->getValueType(0) == MVT::i64 &&
1788 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) &&
1789 DAG.MaskedValueIsZero(Mul0, HighMask) &&
1790 DAG.MaskedValueIsZero(Mul1, HighMask) &&
1791 DAG.MaskedValueIsZero(Addend0, HighMask) &&
1792 DAG.MaskedValueIsZero(Addend1, HighMask)) {
1793 SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1794 Mul0, DAG.getConstant(0, MVT::i32));
1795 SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1796 Mul1, DAG.getConstant(0, MVT::i32));
1797 SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1798 Addend0, DAG.getConstant(0, MVT::i32));
1799 SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1800 Addend1, DAG.getConstant(0, MVT::i32));
1801 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
1802 DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,
1803 Addend0L, Addend1L);
1804 SDValue Lo(Hi.getNode(), 1);
1805 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1810 // Replace unaligned store of unaligned load with memmove.
1811 StoreSDNode *ST = cast<StoreSDNode>(N);
1812 if (!DCI.isBeforeLegalize() ||
1813 allowsMisalignedMemoryAccesses(ST->getMemoryVT(),
1814 ST->getAddressSpace(),
1815 ST->getAlignment()) ||
1816 ST->isVolatile() || ST->isIndexed()) {
1819 SDValue Chain = ST->getChain();
1821 unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits();
1822 if (StoreBits % 8) {
1825 unsigned ABIAlignment = getDataLayout()->getABITypeAlignment(
1826 ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext()));
1827 unsigned Alignment = ST->getAlignment();
1828 if (Alignment >= ABIAlignment) {
1832 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(ST->getValue())) {
1833 if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() &&
1834 LD->getAlignment() == Alignment &&
1835 !LD->isVolatile() && !LD->isIndexed() &&
1836 Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) {
1837 return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
1839 DAG.getConstant(StoreBits/8, MVT::i32),
1840 Alignment, false, ST->getPointerInfo(),
1841 LD->getPointerInfo());
1850 void XCoreTargetLowering::computeKnownBitsForTargetNode(const SDValue Op,
1853 const SelectionDAG &DAG,
1854 unsigned Depth) const {
1855 KnownZero = KnownOne = APInt(KnownZero.getBitWidth(), 0);
1856 switch (Op.getOpcode()) {
1858 case XCoreISD::LADD:
1859 case XCoreISD::LSUB:
1860 if (Op.getResNo() == 1) {
1861 // Top bits of carry / borrow are clear.
1862 KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
1863 KnownZero.getBitWidth() - 1);
1866 case ISD::INTRINSIC_W_CHAIN:
1868 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1870 case Intrinsic::xcore_getts:
1871 // High bits are known to be zero.
1872 KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
1873 KnownZero.getBitWidth() - 16);
1875 case Intrinsic::xcore_int:
1876 case Intrinsic::xcore_inct:
1877 // High bits are known to be zero.
1878 KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
1879 KnownZero.getBitWidth() - 8);
1881 case Intrinsic::xcore_testct:
1882 // Result is either 0 or 1.
1883 KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
1884 KnownZero.getBitWidth() - 1);
1886 case Intrinsic::xcore_testwct:
1887 // Result is in the range 0 - 4.
1888 KnownZero = APInt::getHighBitsSet(KnownZero.getBitWidth(),
1889 KnownZero.getBitWidth() - 3);
1897 //===----------------------------------------------------------------------===//
1898 // Addressing mode description hooks
1899 //===----------------------------------------------------------------------===//
1901 static inline bool isImmUs(int64_t val)
1903 return (val >= 0 && val <= 11);
1906 static inline bool isImmUs2(int64_t val)
1908 return (val%2 == 0 && isImmUs(val/2));
1911 static inline bool isImmUs4(int64_t val)
1913 return (val%4 == 0 && isImmUs(val/4));
1916 /// isLegalAddressingMode - Return true if the addressing mode represented
1917 /// by AM is legal for this target, for a load/store of the specified type.
1919 XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1921 if (Ty->getTypeID() == Type::VoidTyID)
1922 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
1924 const DataLayout *TD = TM.getDataLayout();
1925 unsigned Size = TD->getTypeAllocSize(Ty);
1927 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
1934 if (AM.Scale == 0) {
1935 return isImmUs(AM.BaseOffs);
1938 return AM.Scale == 1 && AM.BaseOffs == 0;
1942 if (AM.Scale == 0) {
1943 return isImmUs2(AM.BaseOffs);
1946 return AM.Scale == 2 && AM.BaseOffs == 0;
1949 if (AM.Scale == 0) {
1950 return isImmUs4(AM.BaseOffs);
1953 return AM.Scale == 4 && AM.BaseOffs == 0;
1957 //===----------------------------------------------------------------------===//
1958 // XCore Inline Assembly Support
1959 //===----------------------------------------------------------------------===//
1961 std::pair<unsigned, const TargetRegisterClass*>
1962 XCoreTargetLowering::
1963 getRegForInlineAsmConstraint(const std::string &Constraint,
1965 if (Constraint.size() == 1) {
1966 switch (Constraint[0]) {
1969 return std::make_pair(0U, &XCore::GRRegsRegClass);
1972 // Use the default implementation in TargetLowering to convert the register
1973 // constraint into a member of a register class.
1974 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);