1 //===-- XCoreISelLowering.cpp - XCore DAG Lowering Implementation ------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the XCoreTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "xcore-lower"
16 #include "XCoreISelLowering.h"
17 #include "XCoreMachineFunctionInfo.h"
19 #include "XCoreTargetObjectFile.h"
20 #include "XCoreTargetMachine.h"
21 #include "XCoreSubtarget.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/Function.h"
24 #include "llvm/Intrinsics.h"
25 #include "llvm/CallingConv.h"
26 #include "llvm/GlobalVariable.h"
27 #include "llvm/GlobalAlias.h"
28 #include "llvm/CodeGen/CallingConvLower.h"
29 #include "llvm/CodeGen/MachineFrameInfo.h"
30 #include "llvm/CodeGen/MachineFunction.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineJumpTableInfo.h"
33 #include "llvm/CodeGen/MachineRegisterInfo.h"
34 #include "llvm/CodeGen/SelectionDAGISel.h"
35 #include "llvm/CodeGen/ValueTypes.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/ErrorHandling.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/ADT/VectorExtras.h"
44 const char *XCoreTargetLowering::
45 getTargetNodeName(unsigned Opcode) const
49 case XCoreISD::BL : return "XCoreISD::BL";
50 case XCoreISD::PCRelativeWrapper : return "XCoreISD::PCRelativeWrapper";
51 case XCoreISD::DPRelativeWrapper : return "XCoreISD::DPRelativeWrapper";
52 case XCoreISD::CPRelativeWrapper : return "XCoreISD::CPRelativeWrapper";
53 case XCoreISD::STWSP : return "XCoreISD::STWSP";
54 case XCoreISD::RETSP : return "XCoreISD::RETSP";
55 case XCoreISD::LADD : return "XCoreISD::LADD";
56 case XCoreISD::LSUB : return "XCoreISD::LSUB";
57 case XCoreISD::LMUL : return "XCoreISD::LMUL";
58 case XCoreISD::MACCU : return "XCoreISD::MACCU";
59 case XCoreISD::MACCS : return "XCoreISD::MACCS";
60 case XCoreISD::BR_JT : return "XCoreISD::BR_JT";
61 case XCoreISD::BR_JT32 : return "XCoreISD::BR_JT32";
62 default : return NULL;
66 XCoreTargetLowering::XCoreTargetLowering(XCoreTargetMachine &XTM)
67 : TargetLowering(XTM, new XCoreTargetObjectFile()),
69 Subtarget(*XTM.getSubtargetImpl()) {
71 // Set up the register classes.
72 addRegisterClass(MVT::i32, XCore::GRRegsRegisterClass);
74 // Compute derived properties from the register classes
75 computeRegisterProperties();
77 // Division is expensive
78 setIntDivIsCheap(false);
80 setShiftAmountType(MVT::i32);
81 setStackPointerRegisterToSaveRestore(XCore::SP);
83 setSchedulingPreference(SchedulingForRegPressure);
85 // Use i32 for setcc operations results (slt, sgt, ...).
86 setBooleanContents(ZeroOrOneBooleanContent);
88 // XCore does not have the NodeTypes below.
89 setOperationAction(ISD::BR_CC, MVT::Other, Expand);
90 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
91 setOperationAction(ISD::ADDC, MVT::i32, Expand);
92 setOperationAction(ISD::ADDE, MVT::i32, Expand);
93 setOperationAction(ISD::SUBC, MVT::i32, Expand);
94 setOperationAction(ISD::SUBE, MVT::i32, Expand);
96 // Stop the combiner recombining select and set_cc
97 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
100 setOperationAction(ISD::ADD, MVT::i64, Custom);
101 setOperationAction(ISD::SUB, MVT::i64, Custom);
102 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
103 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
104 setOperationAction(ISD::MULHS, MVT::i32, Expand);
105 setOperationAction(ISD::MULHU, MVT::i32, Expand);
106 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
107 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
108 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
111 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
112 setOperationAction(ISD::ROTL , MVT::i32, Expand);
113 setOperationAction(ISD::ROTR , MVT::i32, Expand);
115 setOperationAction(ISD::TRAP, MVT::Other, Legal);
118 setOperationAction(ISD::BR_JT, MVT::Other, Custom);
120 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
121 setOperationAction(ISD::BlockAddress, MVT::i32 , Custom);
123 // Thread Local Storage
124 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
126 // Conversion of i64 -> double produces constantpool nodes
127 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
130 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
131 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
132 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
134 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand);
135 setLoadExtAction(ISD::ZEXTLOAD, MVT::i16, Expand);
137 // Custom expand misaligned loads / stores.
138 setOperationAction(ISD::LOAD, MVT::i32, Custom);
139 setOperationAction(ISD::STORE, MVT::i32, Custom);
142 setOperationAction(ISD::VAEND, MVT::Other, Expand);
143 setOperationAction(ISD::VACOPY, MVT::Other, Expand);
144 setOperationAction(ISD::VAARG, MVT::Other, Custom);
145 setOperationAction(ISD::VASTART, MVT::Other, Custom);
148 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
149 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
150 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Expand);
152 maxStoresPerMemset = 4;
153 maxStoresPerMemmove = maxStoresPerMemcpy = 2;
155 // We have target-specific dag combine patterns for the following nodes:
156 setTargetDAGCombine(ISD::STORE);
157 setTargetDAGCombine(ISD::ADD);
160 SDValue XCoreTargetLowering::
161 LowerOperation(SDValue Op, SelectionDAG &DAG) const {
162 switch (Op.getOpcode())
164 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
165 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
166 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG);
167 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
168 case ISD::BR_JT: return LowerBR_JT(Op, DAG);
169 case ISD::LOAD: return LowerLOAD(Op, DAG);
170 case ISD::STORE: return LowerSTORE(Op, DAG);
171 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
172 case ISD::VAARG: return LowerVAARG(Op, DAG);
173 case ISD::VASTART: return LowerVASTART(Op, DAG);
174 case ISD::SMUL_LOHI: return LowerSMUL_LOHI(Op, DAG);
175 case ISD::UMUL_LOHI: return LowerUMUL_LOHI(Op, DAG);
176 // FIXME: Remove these when LegalizeDAGTypes lands.
178 case ISD::SUB: return ExpandADDSUB(Op.getNode(), DAG);
179 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG);
181 llvm_unreachable("unimplemented operand");
186 /// ReplaceNodeResults - Replace the results of node with an illegal result
187 /// type with new values built out of custom code.
188 void XCoreTargetLowering::ReplaceNodeResults(SDNode *N,
189 SmallVectorImpl<SDValue>&Results,
190 SelectionDAG &DAG) const {
191 switch (N->getOpcode()) {
193 llvm_unreachable("Don't know how to custom expand this!");
197 Results.push_back(ExpandADDSUB(N, DAG));
202 /// getFunctionAlignment - Return the Log2 alignment of this function.
203 unsigned XCoreTargetLowering::
204 getFunctionAlignment(const Function *) const {
208 //===----------------------------------------------------------------------===//
209 // Misc Lower Operation implementation
210 //===----------------------------------------------------------------------===//
212 SDValue XCoreTargetLowering::
213 LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
215 DebugLoc dl = Op.getDebugLoc();
216 SDValue Cond = DAG.getNode(ISD::SETCC, dl, MVT::i32, Op.getOperand(2),
217 Op.getOperand(3), Op.getOperand(4));
218 return DAG.getNode(ISD::SELECT, dl, MVT::i32, Cond, Op.getOperand(0),
222 SDValue XCoreTargetLowering::
223 getGlobalAddressWrapper(SDValue GA, const GlobalValue *GV,
224 SelectionDAG &DAG) const
226 // FIXME there is no actual debug info here
227 DebugLoc dl = GA.getDebugLoc();
228 if (isa<Function>(GV)) {
229 return DAG.getNode(XCoreISD::PCRelativeWrapper, dl, MVT::i32, GA);
231 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
233 // If GV is an alias then use the aliasee to determine constness
234 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
235 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
237 bool isConst = GVar && GVar->isConstant();
239 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, GA);
241 return DAG.getNode(XCoreISD::DPRelativeWrapper, dl, MVT::i32, GA);
244 SDValue XCoreTargetLowering::
245 LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const
247 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
248 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
249 // If it's a debug information descriptor, don't mess with it.
250 if (DAG.isVerifiedDebugInfoDesc(Op))
252 return getGlobalAddressWrapper(GA, GV, DAG);
255 static inline SDValue BuildGetId(SelectionDAG &DAG, DebugLoc dl) {
256 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32,
257 DAG.getConstant(Intrinsic::xcore_getid, MVT::i32));
260 static inline bool isZeroLengthArray(const Type *Ty) {
261 const ArrayType *AT = dyn_cast_or_null<ArrayType>(Ty);
262 return AT && (AT->getNumElements() == 0);
265 SDValue XCoreTargetLowering::
266 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
268 // FIXME there isn't really debug info here
269 DebugLoc dl = Op.getDebugLoc();
270 // transform to label + getid() * size
271 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
272 SDValue GA = DAG.getTargetGlobalAddress(GV, MVT::i32);
273 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV);
275 // If GV is an alias then use the aliasee to determine size
276 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
277 GVar = dyn_cast_or_null<GlobalVariable>(GA->resolveAliasedGlobal());
280 llvm_unreachable("Thread local object not a GlobalVariable?");
283 const Type *Ty = cast<PointerType>(GV->getType())->getElementType();
284 if (!Ty->isSized() || isZeroLengthArray(Ty)) {
286 errs() << "Size of thread local object " << GVar->getName()
291 SDValue base = getGlobalAddressWrapper(GA, GV, DAG);
292 const TargetData *TD = TM.getTargetData();
293 unsigned Size = TD->getTypeAllocSize(Ty);
294 SDValue offset = DAG.getNode(ISD::MUL, dl, MVT::i32, BuildGetId(DAG, dl),
295 DAG.getConstant(Size, MVT::i32));
296 return DAG.getNode(ISD::ADD, dl, MVT::i32, base, offset);
299 SDValue XCoreTargetLowering::
300 LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const
302 DebugLoc DL = Op.getDebugLoc();
304 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress();
305 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), /*isTarget=*/true);
307 return DAG.getNode(XCoreISD::PCRelativeWrapper, DL, getPointerTy(), Result);
310 SDValue XCoreTargetLowering::
311 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
313 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
314 // FIXME there isn't really debug info here
315 DebugLoc dl = CP->getDebugLoc();
316 EVT PtrVT = Op.getValueType();
318 if (CP->isMachineConstantPoolEntry()) {
319 Res = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
322 Res = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
325 return DAG.getNode(XCoreISD::CPRelativeWrapper, dl, MVT::i32, Res);
328 unsigned XCoreTargetLowering::getJumpTableEncoding() const {
329 return MachineJumpTableInfo::EK_Inline;
332 SDValue XCoreTargetLowering::
333 LowerBR_JT(SDValue Op, SelectionDAG &DAG) const
335 SDValue Chain = Op.getOperand(0);
336 SDValue Table = Op.getOperand(1);
337 SDValue Index = Op.getOperand(2);
338 DebugLoc dl = Op.getDebugLoc();
339 JumpTableSDNode *JT = cast<JumpTableSDNode>(Table);
340 unsigned JTI = JT->getIndex();
341 MachineFunction &MF = DAG.getMachineFunction();
342 const MachineJumpTableInfo *MJTI = MF.getJumpTableInfo();
343 SDValue TargetJT = DAG.getTargetJumpTable(JT->getIndex(), MVT::i32);
345 unsigned NumEntries = MJTI->getJumpTables()[JTI].MBBs.size();
346 if (NumEntries <= 32) {
347 return DAG.getNode(XCoreISD::BR_JT, dl, MVT::Other, Chain, TargetJT, Index);
349 assert((NumEntries >> 31) == 0);
350 SDValue ScaledIndex = DAG.getNode(ISD::SHL, dl, MVT::i32, Index,
351 DAG.getConstant(1, MVT::i32));
352 return DAG.getNode(XCoreISD::BR_JT32, dl, MVT::Other, Chain, TargetJT,
357 IsWordAlignedBasePlusConstantOffset(SDValue Addr, SDValue &AlignedBase,
360 if (Addr.getOpcode() != ISD::ADD) {
363 ConstantSDNode *CN = 0;
364 if (!(CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1)))) {
367 int64_t off = CN->getSExtValue();
368 const SDValue &Base = Addr.getOperand(0);
369 const SDValue *Root = &Base;
370 if (Base.getOpcode() == ISD::ADD &&
371 Base.getOperand(1).getOpcode() == ISD::SHL) {
372 ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Base.getOperand(1)
374 if (CN && (CN->getSExtValue() >= 2)) {
375 Root = &Base.getOperand(0);
378 if (isa<FrameIndexSDNode>(*Root)) {
379 // All frame indicies are word aligned
384 if (Root->getOpcode() == XCoreISD::DPRelativeWrapper ||
385 Root->getOpcode() == XCoreISD::CPRelativeWrapper) {
386 // All dp / cp relative addresses are word aligned
394 SDValue XCoreTargetLowering::
395 LowerLOAD(SDValue Op, SelectionDAG &DAG) const
397 LoadSDNode *LD = cast<LoadSDNode>(Op);
398 assert(LD->getExtensionType() == ISD::NON_EXTLOAD &&
399 "Unexpected extension type");
400 assert(LD->getMemoryVT() == MVT::i32 && "Unexpected load EVT");
401 if (allowsUnalignedMemoryAccesses(LD->getMemoryVT())) {
404 unsigned ABIAlignment = getTargetData()->
405 getABITypeAlignment(LD->getMemoryVT().getTypeForEVT(*DAG.getContext()));
406 // Leave aligned load alone.
407 if (LD->getAlignment() >= ABIAlignment) {
410 SDValue Chain = LD->getChain();
411 SDValue BasePtr = LD->getBasePtr();
412 DebugLoc dl = Op.getDebugLoc();
416 if (!LD->isVolatile() &&
417 IsWordAlignedBasePlusConstantOffset(BasePtr, Base, Offset)) {
418 if (Offset % 4 == 0) {
419 // We've managed to infer better alignment information than the load
420 // already has. Use an aligned load.
422 // FIXME: No new alignment information is actually passed here.
423 // Should the offset really be 4?
425 return DAG.getLoad(getPointerTy(), dl, Chain, BasePtr, NULL, 4,
429 // ldw low, base[offset >> 2]
430 // ldw high, base[(offset >> 2) + 1]
431 // shr low_shifted, low, (offset & 0x3) * 8
432 // shl high_shifted, high, 32 - (offset & 0x3) * 8
433 // or result, low_shifted, high_shifted
434 SDValue LowOffset = DAG.getConstant(Offset & ~0x3, MVT::i32);
435 SDValue HighOffset = DAG.getConstant((Offset & ~0x3) + 4, MVT::i32);
436 SDValue LowShift = DAG.getConstant((Offset & 0x3) * 8, MVT::i32);
437 SDValue HighShift = DAG.getConstant(32 - (Offset & 0x3) * 8, MVT::i32);
439 SDValue LowAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Base, LowOffset);
440 SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, Base, HighOffset);
442 SDValue Low = DAG.getLoad(getPointerTy(), dl, Chain,
443 LowAddr, NULL, 4, false, false, 0);
444 SDValue High = DAG.getLoad(getPointerTy(), dl, Chain,
445 HighAddr, NULL, 4, false, false, 0);
446 SDValue LowShifted = DAG.getNode(ISD::SRL, dl, MVT::i32, Low, LowShift);
447 SDValue HighShifted = DAG.getNode(ISD::SHL, dl, MVT::i32, High, HighShift);
448 SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, LowShifted, HighShifted);
449 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Low.getValue(1),
451 SDValue Ops[] = { Result, Chain };
452 return DAG.getMergeValues(Ops, 2, dl);
455 if (LD->getAlignment() == 2) {
456 int SVOffset = LD->getSrcValueOffset();
457 SDValue Low = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain,
458 BasePtr, LD->getSrcValue(), SVOffset, MVT::i16,
459 LD->isVolatile(), LD->isNonTemporal(), 2);
460 SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
461 DAG.getConstant(2, MVT::i32));
462 SDValue High = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::i32, Chain,
463 HighAddr, LD->getSrcValue(), SVOffset + 2,
464 MVT::i16, LD->isVolatile(),
465 LD->isNonTemporal(), 2);
466 SDValue HighShifted = DAG.getNode(ISD::SHL, dl, MVT::i32, High,
467 DAG.getConstant(16, MVT::i32));
468 SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, Low, HighShifted);
469 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Low.getValue(1),
471 SDValue Ops[] = { Result, Chain };
472 return DAG.getMergeValues(Ops, 2, dl);
475 // Lower to a call to __misaligned_load(BasePtr).
476 const Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext());
477 TargetLowering::ArgListTy Args;
478 TargetLowering::ArgListEntry Entry;
481 Entry.Node = BasePtr;
482 Args.push_back(Entry);
484 std::pair<SDValue, SDValue> CallResult =
485 LowerCallTo(Chain, IntPtrTy, false, false,
486 false, false, 0, CallingConv::C, false,
487 /*isReturnValueUsed=*/true,
488 DAG.getExternalSymbol("__misaligned_load", getPointerTy()),
492 { CallResult.first, CallResult.second };
494 return DAG.getMergeValues(Ops, 2, dl);
497 SDValue XCoreTargetLowering::
498 LowerSTORE(SDValue Op, SelectionDAG &DAG) const
500 StoreSDNode *ST = cast<StoreSDNode>(Op);
501 assert(!ST->isTruncatingStore() && "Unexpected store type");
502 assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT");
503 if (allowsUnalignedMemoryAccesses(ST->getMemoryVT())) {
506 unsigned ABIAlignment = getTargetData()->
507 getABITypeAlignment(ST->getMemoryVT().getTypeForEVT(*DAG.getContext()));
508 // Leave aligned store alone.
509 if (ST->getAlignment() >= ABIAlignment) {
512 SDValue Chain = ST->getChain();
513 SDValue BasePtr = ST->getBasePtr();
514 SDValue Value = ST->getValue();
515 DebugLoc dl = Op.getDebugLoc();
517 if (ST->getAlignment() == 2) {
518 int SVOffset = ST->getSrcValueOffset();
520 SDValue High = DAG.getNode(ISD::SRL, dl, MVT::i32, Value,
521 DAG.getConstant(16, MVT::i32));
522 SDValue StoreLow = DAG.getTruncStore(Chain, dl, Low, BasePtr,
523 ST->getSrcValue(), SVOffset, MVT::i16,
524 ST->isVolatile(), ST->isNonTemporal(),
526 SDValue HighAddr = DAG.getNode(ISD::ADD, dl, MVT::i32, BasePtr,
527 DAG.getConstant(2, MVT::i32));
528 SDValue StoreHigh = DAG.getTruncStore(Chain, dl, High, HighAddr,
529 ST->getSrcValue(), SVOffset + 2,
530 MVT::i16, ST->isVolatile(),
531 ST->isNonTemporal(), 2);
532 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, StoreLow, StoreHigh);
535 // Lower to a call to __misaligned_store(BasePtr, Value).
536 const Type *IntPtrTy = getTargetData()->getIntPtrType(*DAG.getContext());
537 TargetLowering::ArgListTy Args;
538 TargetLowering::ArgListEntry Entry;
541 Entry.Node = BasePtr;
542 Args.push_back(Entry);
545 Args.push_back(Entry);
547 std::pair<SDValue, SDValue> CallResult =
548 LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), false, false,
549 false, false, 0, CallingConv::C, false,
550 /*isReturnValueUsed=*/true,
551 DAG.getExternalSymbol("__misaligned_store", getPointerTy()),
554 return CallResult.second;
557 SDValue XCoreTargetLowering::
558 LowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
560 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::SMUL_LOHI &&
561 "Unexpected operand to lower!");
562 DebugLoc dl = Op.getDebugLoc();
563 SDValue LHS = Op.getOperand(0);
564 SDValue RHS = Op.getOperand(1);
565 SDValue Zero = DAG.getConstant(0, MVT::i32);
566 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
567 DAG.getVTList(MVT::i32, MVT::i32), Zero, Zero,
569 SDValue Lo(Hi.getNode(), 1);
570 SDValue Ops[] = { Lo, Hi };
571 return DAG.getMergeValues(Ops, 2, dl);
574 SDValue XCoreTargetLowering::
575 LowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const
577 assert(Op.getValueType() == MVT::i32 && Op.getOpcode() == ISD::UMUL_LOHI &&
578 "Unexpected operand to lower!");
579 DebugLoc dl = Op.getDebugLoc();
580 SDValue LHS = Op.getOperand(0);
581 SDValue RHS = Op.getOperand(1);
582 SDValue Zero = DAG.getConstant(0, MVT::i32);
583 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
584 DAG.getVTList(MVT::i32, MVT::i32), LHS, RHS,
586 SDValue Lo(Hi.getNode(), 1);
587 SDValue Ops[] = { Lo, Hi };
588 return DAG.getMergeValues(Ops, 2, dl);
591 /// isADDADDMUL - Return whether Op is in a form that is equivalent to
592 /// add(add(mul(x,y),a),b). If requireIntermediatesHaveOneUse is true then
593 /// each intermediate result in the calculation must also have a single use.
594 /// If the Op is in the correct form the constituent parts are written to Mul0,
595 /// Mul1, Addend0 and Addend1.
597 isADDADDMUL(SDValue Op, SDValue &Mul0, SDValue &Mul1, SDValue &Addend0,
598 SDValue &Addend1, bool requireIntermediatesHaveOneUse)
600 if (Op.getOpcode() != ISD::ADD)
602 SDValue N0 = Op.getOperand(0);
603 SDValue N1 = Op.getOperand(1);
606 if (N0.getOpcode() == ISD::ADD) {
609 } else if (N1.getOpcode() == ISD::ADD) {
615 if (requireIntermediatesHaveOneUse && !AddOp.hasOneUse())
617 if (OtherOp.getOpcode() == ISD::MUL) {
618 // add(add(a,b),mul(x,y))
619 if (requireIntermediatesHaveOneUse && !OtherOp.hasOneUse())
621 Mul0 = OtherOp.getOperand(0);
622 Mul1 = OtherOp.getOperand(1);
623 Addend0 = AddOp.getOperand(0);
624 Addend1 = AddOp.getOperand(1);
627 if (AddOp.getOperand(0).getOpcode() == ISD::MUL) {
628 // add(add(mul(x,y),a),b)
629 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(0).hasOneUse())
631 Mul0 = AddOp.getOperand(0).getOperand(0);
632 Mul1 = AddOp.getOperand(0).getOperand(1);
633 Addend0 = AddOp.getOperand(1);
637 if (AddOp.getOperand(1).getOpcode() == ISD::MUL) {
638 // add(add(a,mul(x,y)),b)
639 if (requireIntermediatesHaveOneUse && !AddOp.getOperand(1).hasOneUse())
641 Mul0 = AddOp.getOperand(1).getOperand(0);
642 Mul1 = AddOp.getOperand(1).getOperand(1);
643 Addend0 = AddOp.getOperand(0);
650 SDValue XCoreTargetLowering::
651 TryExpandADDWithMul(SDNode *N, SelectionDAG &DAG) const
655 if (N->getOperand(0).getOpcode() == ISD::MUL) {
656 Mul = N->getOperand(0);
657 Other = N->getOperand(1);
658 } else if (N->getOperand(1).getOpcode() == ISD::MUL) {
659 Mul = N->getOperand(1);
660 Other = N->getOperand(0);
664 DebugLoc dl = N->getDebugLoc();
665 SDValue LL, RL, AddendL, AddendH;
666 LL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
667 Mul.getOperand(0), DAG.getConstant(0, MVT::i32));
668 RL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
669 Mul.getOperand(1), DAG.getConstant(0, MVT::i32));
670 AddendL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
671 Other, DAG.getConstant(0, MVT::i32));
672 AddendH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
673 Other, DAG.getConstant(1, MVT::i32));
674 APInt HighMask = APInt::getHighBitsSet(64, 32);
675 unsigned LHSSB = DAG.ComputeNumSignBits(Mul.getOperand(0));
676 unsigned RHSSB = DAG.ComputeNumSignBits(Mul.getOperand(1));
677 if (DAG.MaskedValueIsZero(Mul.getOperand(0), HighMask) &&
678 DAG.MaskedValueIsZero(Mul.getOperand(1), HighMask)) {
679 // The inputs are both zero-extended.
680 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
681 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
683 SDValue Lo(Hi.getNode(), 1);
684 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
686 if (LHSSB > 32 && RHSSB > 32) {
687 // The inputs are both sign-extended.
688 SDValue Hi = DAG.getNode(XCoreISD::MACCS, dl,
689 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
691 SDValue Lo(Hi.getNode(), 1);
692 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
695 LH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
696 Mul.getOperand(0), DAG.getConstant(1, MVT::i32));
697 RH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
698 Mul.getOperand(1), DAG.getConstant(1, MVT::i32));
699 SDValue Hi = DAG.getNode(XCoreISD::MACCU, dl,
700 DAG.getVTList(MVT::i32, MVT::i32), AddendH,
702 SDValue Lo(Hi.getNode(), 1);
703 RH = DAG.getNode(ISD::MUL, dl, MVT::i32, LL, RH);
704 LH = DAG.getNode(ISD::MUL, dl, MVT::i32, LH, RL);
705 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, RH);
706 Hi = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, LH);
707 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
710 SDValue XCoreTargetLowering::
711 ExpandADDSUB(SDNode *N, SelectionDAG &DAG) const
713 assert(N->getValueType(0) == MVT::i64 &&
714 (N->getOpcode() == ISD::ADD || N->getOpcode() == ISD::SUB) &&
715 "Unknown operand to lower!");
717 if (N->getOpcode() == ISD::ADD) {
718 SDValue Result = TryExpandADDWithMul(N, DAG);
719 if (Result.getNode() != 0)
723 DebugLoc dl = N->getDebugLoc();
725 // Extract components
726 SDValue LHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
727 N->getOperand(0), DAG.getConstant(0, MVT::i32));
728 SDValue LHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
729 N->getOperand(0), DAG.getConstant(1, MVT::i32));
730 SDValue RHSL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
731 N->getOperand(1), DAG.getConstant(0, MVT::i32));
732 SDValue RHSH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
733 N->getOperand(1), DAG.getConstant(1, MVT::i32));
736 unsigned Opcode = (N->getOpcode() == ISD::ADD) ? XCoreISD::LADD :
738 SDValue Zero = DAG.getConstant(0, MVT::i32);
739 SDValue Carry = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
741 SDValue Lo(Carry.getNode(), 1);
743 SDValue Ignored = DAG.getNode(Opcode, dl, DAG.getVTList(MVT::i32, MVT::i32),
745 SDValue Hi(Ignored.getNode(), 1);
747 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
750 SDValue XCoreTargetLowering::
751 LowerVAARG(SDValue Op, SelectionDAG &DAG) const
753 llvm_unreachable("unimplemented");
754 // FIX Arguments passed by reference need a extra dereference.
755 SDNode *Node = Op.getNode();
756 DebugLoc dl = Node->getDebugLoc();
757 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
758 EVT VT = Node->getValueType(0);
759 SDValue VAList = DAG.getLoad(getPointerTy(), dl, Node->getOperand(0),
760 Node->getOperand(1), V, 0, false, false, 0);
761 // Increment the pointer, VAList, to the next vararg
762 SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList,
763 DAG.getConstant(VT.getSizeInBits(),
765 // Store the incremented VAList to the legalized pointer
766 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1), V, 0,
768 // Load the actual argument out of the pointer VAList
769 return DAG.getLoad(VT, dl, Tmp3, VAList, NULL, 0, false, false, 0);
772 SDValue XCoreTargetLowering::
773 LowerVASTART(SDValue Op, SelectionDAG &DAG) const
775 DebugLoc dl = Op.getDebugLoc();
776 // vastart stores the address of the VarArgsFrameIndex slot into the
777 // memory location argument
778 MachineFunction &MF = DAG.getMachineFunction();
779 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
780 SDValue Addr = DAG.getFrameIndex(XFI->getVarArgsFrameIndex(), MVT::i32);
781 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
782 return DAG.getStore(Op.getOperand(0), dl, Addr, Op.getOperand(1), SV, 0,
786 SDValue XCoreTargetLowering::LowerFRAMEADDR(SDValue Op,
787 SelectionDAG &DAG) const {
788 DebugLoc dl = Op.getDebugLoc();
789 // Depths > 0 not supported yet!
790 if (cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() > 0)
793 MachineFunction &MF = DAG.getMachineFunction();
794 const TargetRegisterInfo *RegInfo = getTargetMachine().getRegisterInfo();
795 return DAG.getCopyFromReg(DAG.getEntryNode(), dl,
796 RegInfo->getFrameRegister(MF), MVT::i32);
799 //===----------------------------------------------------------------------===//
800 // Calling Convention Implementation
801 //===----------------------------------------------------------------------===//
803 #include "XCoreGenCallingConv.inc"
805 //===----------------------------------------------------------------------===//
806 // Call Calling Convention Implementation
807 //===----------------------------------------------------------------------===//
809 /// XCore call implementation
811 XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
812 CallingConv::ID CallConv, bool isVarArg,
814 const SmallVectorImpl<ISD::OutputArg> &Outs,
815 const SmallVectorImpl<ISD::InputArg> &Ins,
816 DebugLoc dl, SelectionDAG &DAG,
817 SmallVectorImpl<SDValue> &InVals) const {
818 // XCore target does not yet support tail call optimization.
821 // For now, only CallingConv::C implemented
825 llvm_unreachable("Unsupported calling convention");
826 case CallingConv::Fast:
828 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
829 Outs, Ins, dl, DAG, InVals);
833 /// LowerCCCCallTo - functions arguments are copied from virtual
834 /// regs to (physical regs)/(stack frame), CALLSEQ_START and
835 /// CALLSEQ_END are emitted.
836 /// TODO: isTailCall, sret.
838 XCoreTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
839 CallingConv::ID CallConv, bool isVarArg,
841 const SmallVectorImpl<ISD::OutputArg> &Outs,
842 const SmallVectorImpl<ISD::InputArg> &Ins,
843 DebugLoc dl, SelectionDAG &DAG,
844 SmallVectorImpl<SDValue> &InVals) const {
846 // Analyze operands of the call, assigning locations to each operand.
847 SmallVector<CCValAssign, 16> ArgLocs;
848 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
849 ArgLocs, *DAG.getContext());
851 // The ABI dictates there should be one stack slot available to the callee
852 // on function entry (for saving lr).
853 CCInfo.AllocateStack(4, 4);
855 CCInfo.AnalyzeCallOperands(Outs, CC_XCore);
857 // Get a count of how many bytes are to be pushed on the stack.
858 unsigned NumBytes = CCInfo.getNextStackOffset();
860 Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(NumBytes,
861 getPointerTy(), true));
863 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
864 SmallVector<SDValue, 12> MemOpChains;
866 // Walk the register/memloc assignments, inserting copies/loads.
867 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
868 CCValAssign &VA = ArgLocs[i];
869 SDValue Arg = Outs[i].Val;
871 // Promote the value if needed.
872 switch (VA.getLocInfo()) {
873 default: llvm_unreachable("Unknown loc info!");
874 case CCValAssign::Full: break;
875 case CCValAssign::SExt:
876 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
878 case CCValAssign::ZExt:
879 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
881 case CCValAssign::AExt:
882 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
886 // Arguments that can be passed on register must be kept at
889 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
891 assert(VA.isMemLoc());
893 int Offset = VA.getLocMemOffset();
895 MemOpChains.push_back(DAG.getNode(XCoreISD::STWSP, dl, MVT::Other,
897 DAG.getConstant(Offset/4, MVT::i32)));
901 // Transform all store nodes into one single node because
902 // all store nodes are independent of each other.
903 if (!MemOpChains.empty())
904 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
905 &MemOpChains[0], MemOpChains.size());
907 // Build a sequence of copy-to-reg nodes chained together with token
908 // chain and flag operands which copy the outgoing args into registers.
909 // The InFlag in necessary since all emited instructions must be
912 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
913 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
914 RegsToPass[i].second, InFlag);
915 InFlag = Chain.getValue(1);
918 // If the callee is a GlobalAddress node (quite common, every direct call is)
919 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
920 // Likewise ExternalSymbol -> TargetExternalSymbol.
921 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
922 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), MVT::i32);
923 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
924 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), MVT::i32);
926 // XCoreBranchLink = #chain, #target_address, #opt_in_flags...
927 // = Chain, Callee, Reg#1, Reg#2, ...
929 // Returns a chain & a flag for retval copy to use.
930 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
931 SmallVector<SDValue, 8> Ops;
932 Ops.push_back(Chain);
933 Ops.push_back(Callee);
935 // Add argument registers to the end of the list so that they are
936 // known live into the call.
937 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
938 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
939 RegsToPass[i].second.getValueType()));
941 if (InFlag.getNode())
942 Ops.push_back(InFlag);
944 Chain = DAG.getNode(XCoreISD::BL, dl, NodeTys, &Ops[0], Ops.size());
945 InFlag = Chain.getValue(1);
947 // Create the CALLSEQ_END node.
948 Chain = DAG.getCALLSEQ_END(Chain,
949 DAG.getConstant(NumBytes, getPointerTy(), true),
950 DAG.getConstant(0, getPointerTy(), true),
952 InFlag = Chain.getValue(1);
954 // Handle result values, copying them out of physregs into vregs that we
956 return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
957 Ins, dl, DAG, InVals);
960 /// LowerCallResult - Lower the result values of a call into the
961 /// appropriate copies out of appropriate physical registers.
963 XCoreTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
964 CallingConv::ID CallConv, bool isVarArg,
965 const SmallVectorImpl<ISD::InputArg> &Ins,
966 DebugLoc dl, SelectionDAG &DAG,
967 SmallVectorImpl<SDValue> &InVals) const {
969 // Assign locations to each value returned by this call.
970 SmallVector<CCValAssign, 16> RVLocs;
971 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
972 RVLocs, *DAG.getContext());
974 CCInfo.AnalyzeCallResult(Ins, RetCC_XCore);
976 // Copy all of the result registers out of their specified physreg.
977 for (unsigned i = 0; i != RVLocs.size(); ++i) {
978 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
979 RVLocs[i].getValVT(), InFlag).getValue(1);
980 InFlag = Chain.getValue(2);
981 InVals.push_back(Chain.getValue(0));
987 //===----------------------------------------------------------------------===//
988 // Formal Arguments Calling Convention Implementation
989 //===----------------------------------------------------------------------===//
991 /// XCore formal arguments implementation
993 XCoreTargetLowering::LowerFormalArguments(SDValue Chain,
994 CallingConv::ID CallConv,
996 const SmallVectorImpl<ISD::InputArg> &Ins,
999 SmallVectorImpl<SDValue> &InVals)
1004 llvm_unreachable("Unsupported calling convention");
1005 case CallingConv::C:
1006 case CallingConv::Fast:
1007 return LowerCCCArguments(Chain, CallConv, isVarArg,
1008 Ins, dl, DAG, InVals);
1012 /// LowerCCCArguments - transform physical registers into
1013 /// virtual registers and generate load operations for
1014 /// arguments places on the stack.
1017 XCoreTargetLowering::LowerCCCArguments(SDValue Chain,
1018 CallingConv::ID CallConv,
1020 const SmallVectorImpl<ISD::InputArg>
1024 SmallVectorImpl<SDValue> &InVals) const {
1025 MachineFunction &MF = DAG.getMachineFunction();
1026 MachineFrameInfo *MFI = MF.getFrameInfo();
1027 MachineRegisterInfo &RegInfo = MF.getRegInfo();
1029 // Assign locations to all of the incoming arguments.
1030 SmallVector<CCValAssign, 16> ArgLocs;
1031 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1032 ArgLocs, *DAG.getContext());
1034 CCInfo.AnalyzeFormalArguments(Ins, CC_XCore);
1036 unsigned StackSlotSize = XCoreFrameInfo::stackSlotSize();
1038 unsigned LRSaveSize = StackSlotSize;
1040 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
1042 CCValAssign &VA = ArgLocs[i];
1044 if (VA.isRegLoc()) {
1045 // Arguments passed in registers
1046 EVT RegVT = VA.getLocVT();
1047 switch (RegVT.getSimpleVT().SimpleTy) {
1051 errs() << "LowerFormalArguments Unhandled argument type: "
1052 << RegVT.getSimpleVT().SimpleTy << "\n";
1054 llvm_unreachable(0);
1057 unsigned VReg = RegInfo.createVirtualRegister(
1058 XCore::GRRegsRegisterClass);
1059 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1060 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
1064 assert(VA.isMemLoc());
1065 // Load the argument to a virtual register
1066 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
1067 if (ObjSize > StackSlotSize) {
1068 errs() << "LowerFormalArguments Unhandled argument type: "
1069 << (unsigned)VA.getLocVT().getSimpleVT().SimpleTy
1072 // Create the frame index object for this incoming parameter...
1073 int FI = MFI->CreateFixedObject(ObjSize,
1074 LRSaveSize + VA.getLocMemOffset(),
1077 // Create the SelectionDAG nodes corresponding to a load
1078 //from this parameter
1079 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1080 InVals.push_back(DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, NULL, 0,
1086 /* Argument registers */
1087 static const unsigned ArgRegs[] = {
1088 XCore::R0, XCore::R1, XCore::R2, XCore::R3
1090 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
1091 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs,
1092 array_lengthof(ArgRegs));
1093 if (FirstVAReg < array_lengthof(ArgRegs)) {
1094 SmallVector<SDValue, 4> MemOps;
1096 // Save remaining registers, storing higher register numbers at a higher
1098 for (unsigned i = array_lengthof(ArgRegs) - 1; i >= FirstVAReg; --i) {
1099 // Create a stack slot
1100 int FI = MFI->CreateFixedObject(4, offset, true, false);
1101 if (i == FirstVAReg) {
1102 XFI->setVarArgsFrameIndex(FI);
1104 offset -= StackSlotSize;
1105 SDValue FIN = DAG.getFrameIndex(FI, MVT::i32);
1106 // Move argument from phys reg -> virt reg
1107 unsigned VReg = RegInfo.createVirtualRegister(
1108 XCore::GRRegsRegisterClass);
1109 RegInfo.addLiveIn(ArgRegs[i], VReg);
1110 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
1111 // Move argument from virt reg -> stack
1112 SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN, NULL, 0,
1114 MemOps.push_back(Store);
1116 if (!MemOps.empty())
1117 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
1118 &MemOps[0], MemOps.size());
1120 // This will point to the next argument passed via stack.
1121 XFI->setVarArgsFrameIndex(
1122 MFI->CreateFixedObject(4, LRSaveSize + CCInfo.getNextStackOffset(),
1130 //===----------------------------------------------------------------------===//
1131 // Return Value Calling Convention Implementation
1132 //===----------------------------------------------------------------------===//
1134 bool XCoreTargetLowering::
1135 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1136 const SmallVectorImpl<EVT> &OutTys,
1137 const SmallVectorImpl<ISD::ArgFlagsTy> &ArgsFlags,
1138 SelectionDAG &DAG) const {
1139 SmallVector<CCValAssign, 16> RVLocs;
1140 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1141 RVLocs, *DAG.getContext());
1142 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_XCore);
1146 XCoreTargetLowering::LowerReturn(SDValue Chain,
1147 CallingConv::ID CallConv, bool isVarArg,
1148 const SmallVectorImpl<ISD::OutputArg> &Outs,
1149 DebugLoc dl, SelectionDAG &DAG) const {
1151 // CCValAssign - represent the assignment of
1152 // the return value to a location
1153 SmallVector<CCValAssign, 16> RVLocs;
1155 // CCState - Info about the registers and stack slot.
1156 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
1157 RVLocs, *DAG.getContext());
1159 // Analize return values.
1160 CCInfo.AnalyzeReturn(Outs, RetCC_XCore);
1162 // If this is the first return lowered for this function, add
1163 // the regs to the liveout set for the function.
1164 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
1165 for (unsigned i = 0; i != RVLocs.size(); ++i)
1166 if (RVLocs[i].isRegLoc())
1167 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
1172 // Copy the result values into the output registers.
1173 for (unsigned i = 0; i != RVLocs.size(); ++i) {
1174 CCValAssign &VA = RVLocs[i];
1175 assert(VA.isRegLoc() && "Can only return in registers!");
1177 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
1180 // guarantee that all emitted copies are
1181 // stuck together, avoiding something bad
1182 Flag = Chain.getValue(1);
1185 // Return on XCore is always a "retsp 0"
1187 return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
1188 Chain, DAG.getConstant(0, MVT::i32), Flag);
1190 return DAG.getNode(XCoreISD::RETSP, dl, MVT::Other,
1191 Chain, DAG.getConstant(0, MVT::i32));
1194 //===----------------------------------------------------------------------===//
1195 // Other Lowering Code
1196 //===----------------------------------------------------------------------===//
1199 XCoreTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1200 MachineBasicBlock *BB) const {
1201 const TargetInstrInfo &TII = *getTargetMachine().getInstrInfo();
1202 DebugLoc dl = MI->getDebugLoc();
1203 assert((MI->getOpcode() == XCore::SELECT_CC) &&
1204 "Unexpected instr type to insert");
1206 // To "insert" a SELECT_CC instruction, we actually have to insert the diamond
1207 // control-flow pattern. The incoming instruction knows the destination vreg
1208 // to set, the condition code register to branch on, the true/false values to
1209 // select between, and a branch opcode to use.
1210 const BasicBlock *LLVM_BB = BB->getBasicBlock();
1211 MachineFunction::iterator It = BB;
1217 // cmpTY ccX, r1, r2
1219 // fallthrough --> copy0MBB
1220 MachineBasicBlock *thisMBB = BB;
1221 MachineFunction *F = BB->getParent();
1222 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
1223 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
1224 BuildMI(BB, dl, TII.get(XCore::BRFT_lru6))
1225 .addReg(MI->getOperand(1).getReg()).addMBB(sinkMBB);
1226 F->insert(It, copy0MBB);
1227 F->insert(It, sinkMBB);
1228 // Update machine-CFG edges by first adding all successors of the current
1229 // block to the new block which will contain the Phi node for the select.
1230 for (MachineBasicBlock::succ_iterator I = BB->succ_begin(),
1231 E = BB->succ_end(); I != E; ++I)
1232 sinkMBB->addSuccessor(*I);
1233 // Next, remove all successors of the current block, and add the true
1234 // and fallthrough blocks as its successors.
1235 while (!BB->succ_empty())
1236 BB->removeSuccessor(BB->succ_begin());
1237 // Next, add the true and fallthrough blocks as its successors.
1238 BB->addSuccessor(copy0MBB);
1239 BB->addSuccessor(sinkMBB);
1242 // %FalseValue = ...
1243 // # fallthrough to sinkMBB
1246 // Update machine-CFG edges
1247 BB->addSuccessor(sinkMBB);
1250 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
1253 BuildMI(BB, dl, TII.get(XCore::PHI), MI->getOperand(0).getReg())
1254 .addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB)
1255 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB);
1257 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.
1261 //===----------------------------------------------------------------------===//
1262 // Target Optimization Hooks
1263 //===----------------------------------------------------------------------===//
1265 SDValue XCoreTargetLowering::PerformDAGCombine(SDNode *N,
1266 DAGCombinerInfo &DCI) const {
1267 SelectionDAG &DAG = DCI.DAG;
1268 DebugLoc dl = N->getDebugLoc();
1269 switch (N->getOpcode()) {
1271 case XCoreISD::LADD: {
1272 SDValue N0 = N->getOperand(0);
1273 SDValue N1 = N->getOperand(1);
1274 SDValue N2 = N->getOperand(2);
1275 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1276 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1277 EVT VT = N0.getValueType();
1279 // canonicalize constant to RHS
1281 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2);
1283 // fold (ladd 0, 0, x) -> 0, x & 1
1284 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1285 SDValue Carry = DAG.getConstant(0, VT);
1286 SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2,
1287 DAG.getConstant(1, VT));
1288 SDValue Ops [] = { Carry, Result };
1289 return DAG.getMergeValues(Ops, 2, dl);
1292 // fold (ladd x, 0, y) -> 0, add x, y iff carry is unused and y has only the
1294 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 0)) {
1295 APInt KnownZero, KnownOne;
1296 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1297 VT.getSizeInBits() - 1);
1298 DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne);
1299 if (KnownZero == Mask) {
1300 SDValue Carry = DAG.getConstant(0, VT);
1301 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2);
1302 SDValue Ops [] = { Carry, Result };
1303 return DAG.getMergeValues(Ops, 2, dl);
1308 case XCoreISD::LSUB: {
1309 SDValue N0 = N->getOperand(0);
1310 SDValue N1 = N->getOperand(1);
1311 SDValue N2 = N->getOperand(2);
1312 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1313 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1314 EVT VT = N0.getValueType();
1316 // fold (lsub 0, 0, x) -> x, -x iff x has only the low bit set
1317 if (N0C && N0C->isNullValue() && N1C && N1C->isNullValue()) {
1318 APInt KnownZero, KnownOne;
1319 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1320 VT.getSizeInBits() - 1);
1321 DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne);
1322 if (KnownZero == Mask) {
1323 SDValue Borrow = N2;
1324 SDValue Result = DAG.getNode(ISD::SUB, dl, VT,
1325 DAG.getConstant(0, VT), N2);
1326 SDValue Ops [] = { Borrow, Result };
1327 return DAG.getMergeValues(Ops, 2, dl);
1331 // fold (lsub x, 0, y) -> 0, sub x, y iff borrow is unused and y has only the
1333 if (N1C && N1C->isNullValue() && N->hasNUsesOfValue(0, 0)) {
1334 APInt KnownZero, KnownOne;
1335 APInt Mask = APInt::getHighBitsSet(VT.getSizeInBits(),
1336 VT.getSizeInBits() - 1);
1337 DAG.ComputeMaskedBits(N2, Mask, KnownZero, KnownOne);
1338 if (KnownZero == Mask) {
1339 SDValue Borrow = DAG.getConstant(0, VT);
1340 SDValue Result = DAG.getNode(ISD::SUB, dl, VT, N0, N2);
1341 SDValue Ops [] = { Borrow, Result };
1342 return DAG.getMergeValues(Ops, 2, dl);
1347 case XCoreISD::LMUL: {
1348 SDValue N0 = N->getOperand(0);
1349 SDValue N1 = N->getOperand(1);
1350 SDValue N2 = N->getOperand(2);
1351 SDValue N3 = N->getOperand(3);
1352 ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
1353 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
1354 EVT VT = N0.getValueType();
1355 // Canonicalize multiplicative constant to RHS. If both multiplicative
1356 // operands are constant canonicalize smallest to RHS.
1357 if ((N0C && !N1C) ||
1358 (N0C && N1C && N0C->getZExtValue() < N1C->getZExtValue()))
1359 return DAG.getNode(XCoreISD::LMUL, dl, DAG.getVTList(VT, VT), N1, N0, N2, N3);
1362 if (N1C && N1C->isNullValue()) {
1363 // If the high result is unused fold to add(a, b)
1364 if (N->hasNUsesOfValue(0, 0)) {
1365 SDValue Lo = DAG.getNode(ISD::ADD, dl, VT, N2, N3);
1366 SDValue Ops [] = { Lo, Lo };
1367 return DAG.getMergeValues(Ops, 2, dl);
1369 // Otherwise fold to ladd(a, b, 0)
1370 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N2, N3, N1);
1375 // Fold 32 bit expressions such as add(add(mul(x,y),a),b) ->
1376 // lmul(x, y, a, b). The high result of lmul will be ignored.
1377 // This is only profitable if the intermediate results are unused
1379 SDValue Mul0, Mul1, Addend0, Addend1;
1380 if (N->getValueType(0) == MVT::i32 &&
1381 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, true)) {
1382 SDValue Zero = DAG.getConstant(0, MVT::i32);
1383 SDValue Ignored = DAG.getNode(XCoreISD::LMUL, dl,
1384 DAG.getVTList(MVT::i32, MVT::i32), Mul0,
1385 Mul1, Addend0, Addend1);
1386 SDValue Result(Ignored.getNode(), 1);
1389 APInt HighMask = APInt::getHighBitsSet(64, 32);
1390 // Fold 64 bit expression such as add(add(mul(x,y),a),b) ->
1391 // lmul(x, y, a, b) if all operands are zero-extended. We do this
1392 // before type legalization as it is messy to match the operands after
1394 if (N->getValueType(0) == MVT::i64 &&
1395 isADDADDMUL(SDValue(N, 0), Mul0, Mul1, Addend0, Addend1, false) &&
1396 DAG.MaskedValueIsZero(Mul0, HighMask) &&
1397 DAG.MaskedValueIsZero(Mul1, HighMask) &&
1398 DAG.MaskedValueIsZero(Addend0, HighMask) &&
1399 DAG.MaskedValueIsZero(Addend1, HighMask)) {
1400 SDValue Mul0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1401 Mul0, DAG.getConstant(0, MVT::i32));
1402 SDValue Mul1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1403 Mul1, DAG.getConstant(0, MVT::i32));
1404 SDValue Addend0L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1405 Addend0, DAG.getConstant(0, MVT::i32));
1406 SDValue Addend1L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
1407 Addend1, DAG.getConstant(0, MVT::i32));
1408 SDValue Hi = DAG.getNode(XCoreISD::LMUL, dl,
1409 DAG.getVTList(MVT::i32, MVT::i32), Mul0L, Mul1L,
1410 Addend0L, Addend1L);
1411 SDValue Lo(Hi.getNode(), 1);
1412 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi);
1417 // Replace unaligned store of unaligned load with memmove.
1418 StoreSDNode *ST = cast<StoreSDNode>(N);
1419 if (!DCI.isBeforeLegalize() ||
1420 allowsUnalignedMemoryAccesses(ST->getMemoryVT()) ||
1421 ST->isVolatile() || ST->isIndexed()) {
1424 SDValue Chain = ST->getChain();
1426 unsigned StoreBits = ST->getMemoryVT().getStoreSizeInBits();
1427 if (StoreBits % 8) {
1430 unsigned ABIAlignment = getTargetData()->getABITypeAlignment(
1431 ST->getMemoryVT().getTypeForEVT(*DCI.DAG.getContext()));
1432 unsigned Alignment = ST->getAlignment();
1433 if (Alignment >= ABIAlignment) {
1437 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(ST->getValue())) {
1438 if (LD->hasNUsesOfValue(1, 0) && ST->getMemoryVT() == LD->getMemoryVT() &&
1439 LD->getAlignment() == Alignment &&
1440 !LD->isVolatile() && !LD->isIndexed() &&
1441 Chain.reachesChainWithoutSideEffects(SDValue(LD, 1))) {
1442 return DAG.getMemmove(Chain, dl, ST->getBasePtr(),
1444 DAG.getConstant(StoreBits/8, MVT::i32),
1445 Alignment, false, ST->getSrcValue(),
1446 ST->getSrcValueOffset(), LD->getSrcValue(),
1447 LD->getSrcValueOffset());
1456 void XCoreTargetLowering::computeMaskedBitsForTargetNode(const SDValue Op,
1460 const SelectionDAG &DAG,
1461 unsigned Depth) const {
1462 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0);
1463 switch (Op.getOpcode()) {
1465 case XCoreISD::LADD:
1466 case XCoreISD::LSUB:
1467 if (Op.getResNo() == 0) {
1468 // Top bits of carry / borrow are clear.
1469 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(),
1470 Mask.getBitWidth() - 1);
1477 //===----------------------------------------------------------------------===//
1478 // Addressing mode description hooks
1479 //===----------------------------------------------------------------------===//
1481 static inline bool isImmUs(int64_t val)
1483 return (val >= 0 && val <= 11);
1486 static inline bool isImmUs2(int64_t val)
1488 return (val%2 == 0 && isImmUs(val/2));
1491 static inline bool isImmUs4(int64_t val)
1493 return (val%4 == 0 && isImmUs(val/4));
1496 /// isLegalAddressingMode - Return true if the addressing mode represented
1497 /// by AM is legal for this target, for a load/store of the specified type.
1499 XCoreTargetLowering::isLegalAddressingMode(const AddrMode &AM,
1500 const Type *Ty) const {
1501 if (Ty->getTypeID() == Type::VoidTyID)
1502 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs);
1504 const TargetData *TD = TM.getTargetData();
1505 unsigned Size = TD->getTypeAllocSize(Ty);
1507 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 &&
1514 if (AM.Scale == 0) {
1515 return isImmUs(AM.BaseOffs);
1518 return AM.Scale == 1 && AM.BaseOffs == 0;
1522 if (AM.Scale == 0) {
1523 return isImmUs2(AM.BaseOffs);
1526 return AM.Scale == 2 && AM.BaseOffs == 0;
1529 if (AM.Scale == 0) {
1530 return isImmUs4(AM.BaseOffs);
1533 return AM.Scale == 4 && AM.BaseOffs == 0;
1539 //===----------------------------------------------------------------------===//
1540 // XCore Inline Assembly Support
1541 //===----------------------------------------------------------------------===//
1543 std::vector<unsigned> XCoreTargetLowering::
1544 getRegClassForInlineAsmConstraint(const std::string &Constraint,
1547 if (Constraint.size() != 1)
1548 return std::vector<unsigned>();
1550 switch (Constraint[0]) {
1553 return make_vector<unsigned>(XCore::R0, XCore::R1, XCore::R2,
1554 XCore::R3, XCore::R4, XCore::R5,
1555 XCore::R6, XCore::R7, XCore::R8,
1556 XCore::R9, XCore::R10, XCore::R11, 0);
1559 return std::vector<unsigned>();