1 //===-- XCoreFrameLowering.cpp - Frame info for XCore Target --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains XCore frame information that doesn't fit anywhere else
13 //===----------------------------------------------------------------------===//
15 #include "XCoreFrameLowering.h"
17 #include "XCoreInstrInfo.h"
18 #include "XCoreMachineFunctionInfo.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineFunction.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineModuleInfo.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/RegisterScavenging.h"
25 #include "llvm/IR/DataLayout.h"
26 #include "llvm/IR/Function.h"
27 #include "llvm/Support/ErrorHandling.h"
28 #include "llvm/Target/TargetOptions.h"
32 // helper functions. FIXME: Eliminate.
33 static inline bool isImmUs(unsigned val) {
37 static inline bool isImmU6(unsigned val) {
38 return val < (1 << 6);
41 static inline bool isImmU16(unsigned val) {
42 return val < (1 << 16);
45 static void loadFromStack(MachineBasicBlock &MBB,
46 MachineBasicBlock::iterator I,
47 unsigned DstReg, int Offset, DebugLoc dl,
48 const TargetInstrInfo &TII) {
49 assert(Offset%4 == 0 && "Misaligned stack offset");
51 bool isU6 = isImmU6(Offset);
52 if (!isU6 && !isImmU16(Offset))
53 report_fatal_error("loadFromStack offset too big " + Twine(Offset));
54 int Opcode = isU6 ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
55 BuildMI(MBB, I, dl, TII.get(Opcode), DstReg)
60 static void storeToStack(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator I,
62 unsigned SrcReg, int Offset, DebugLoc dl,
63 const TargetInstrInfo &TII) {
64 assert(Offset%4 == 0 && "Misaligned stack offset");
66 bool isU6 = isImmU6(Offset);
67 if (!isU6 && !isImmU16(Offset))
68 report_fatal_error("storeToStack offset too big " + Twine(Offset));
69 int Opcode = isU6 ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
70 BuildMI(MBB, I, dl, TII.get(Opcode))
76 //===----------------------------------------------------------------------===//
77 // XCoreFrameLowering:
78 //===----------------------------------------------------------------------===//
80 XCoreFrameLowering::XCoreFrameLowering(const XCoreSubtarget &sti)
81 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 0) {
85 bool XCoreFrameLowering::hasFP(const MachineFunction &MF) const {
86 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
87 MF.getFrameInfo()->hasVarSizedObjects();
90 void XCoreFrameLowering::emitPrologue(MachineFunction &MF) const {
91 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
92 MachineBasicBlock::iterator MBBI = MBB.begin();
93 MachineFrameInfo *MFI = MF.getFrameInfo();
94 MachineModuleInfo *MMI = &MF.getMMI();
95 const XCoreInstrInfo &TII =
96 *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
97 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
98 DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
101 const AttributeSet &PAL = MF.getFunction()->getAttributes();
103 if (PAL.hasAttrSomewhere(Attribute::Nest))
104 loadFromStack(MBB, MBBI, XCore::R11, 0, dl, TII);
106 // Work out frame sizes.
107 int FrameSize = MFI->getStackSize();
108 assert(FrameSize%4 == 0 && "Misaligned frame size");
111 bool isU6 = isImmU6(FrameSize);
113 if (!isU6 && !isImmU16(FrameSize)) {
114 // FIXME could emit multiple instructions.
115 report_fatal_error("emitPrologue Frame size too big: " + Twine(FrameSize));
117 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(MF);
119 bool saveLR = XFI->getUsesLR();
120 // Do we need to allocate space on the stack?
123 if (saveLR && (MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0)) {
124 Opcode = (isU6) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
125 MBB.addLiveIn(XCore::LR);
128 Opcode = (isU6) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
130 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
132 if (emitFrameMoves) {
134 // Show update of SP.
135 MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
136 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
140 int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
141 storeToStack(MBB, MBBI, XCore::LR, LRSpillOffset + FrameSize*4, dl, TII);
142 MBB.addLiveIn(XCore::LR);
144 if (emitFrameMoves) {
145 MCSymbol *SaveLRLabel = MMI->getContext().CreateTempSymbol();
146 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLRLabel);
151 // Save R10 to the stack.
152 int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
153 storeToStack(MBB, MBBI, XCore::R10, FPSpillOffset + FrameSize*4, dl, TII);
154 // R10 is live-in. It is killed at the spill.
155 MBB.addLiveIn(XCore::R10);
156 if (emitFrameMoves) {
157 MCSymbol *SaveR10Label = MMI->getContext().CreateTempSymbol();
158 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(SaveR10Label);
160 // Set the FP from the SP.
161 unsigned FramePtr = XCore::R10;
162 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr)
164 if (emitFrameMoves) {
165 // Show FP is now valid.
166 MCSymbol *FrameLabel = MMI->getContext().CreateTempSymbol();
167 BuildMI(MBB, MBBI, dl, TII.get(XCore::PROLOG_LABEL)).addSym(FrameLabel);
172 void XCoreFrameLowering::emitEpilogue(MachineFunction &MF,
173 MachineBasicBlock &MBB) const {
174 MachineFrameInfo *MFI = MF.getFrameInfo();
175 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
176 const XCoreInstrInfo &TII =
177 *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
178 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
179 DebugLoc dl = MBBI->getDebugLoc();
183 // Restore the stack pointer.
184 unsigned FramePtr = XCore::R10;
185 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r))
189 // Work out frame sizes.
190 int FrameSize = MFI->getStackSize();
192 assert(FrameSize%4 == 0 && "Misaligned frame size");
196 bool isU6 = isImmU6(FrameSize);
198 if (!isU6 && !isImmU16(FrameSize)) {
199 // FIXME could emit multiple instructions.
200 report_fatal_error("emitEpilogue Frame size too big: " + Twine(FrameSize));
205 int FPSpillOffset = MFI->getObjectOffset(XFI->getFPSpillSlot());
206 FPSpillOffset += FrameSize*4;
207 loadFromStack(MBB, MBBI, XCore::R10, FPSpillOffset, dl, TII);
210 bool restoreLR = XFI->getUsesLR();
212 (FrameSize == 0 || MFI->getObjectOffset(XFI->getLRSpillSlot()) != 0)) {
213 int LRSpillOffset = MFI->getObjectOffset(XFI->getLRSpillSlot());
214 LRSpillOffset += FrameSize*4;
215 loadFromStack(MBB, MBBI, XCore::LR, LRSpillOffset, dl, TII);
221 // Fold prologue into return instruction
222 assert(MFI->getObjectOffset(XFI->getLRSpillSlot()) == 0);
223 assert(MBBI->getOpcode() == XCore::RETSP_u6
224 || MBBI->getOpcode() == XCore::RETSP_lu6);
225 int Opcode = (isU6) ? XCore::RETSP_u6 : XCore::RETSP_lu6;
226 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(FrameSize);
229 int Opcode = (isU6) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
230 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(FrameSize);
235 bool XCoreFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
236 MachineBasicBlock::iterator MI,
237 const std::vector<CalleeSavedInfo> &CSI,
238 const TargetRegisterInfo *TRI) const {
242 MachineFunction *MF = MBB.getParent();
243 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
245 XCoreFunctionInfo *XFI = MF->getInfo<XCoreFunctionInfo>();
246 bool emitFrameMoves = XCoreRegisterInfo::needsFrameMoves(*MF);
249 if (MI != MBB.end()) DL = MI->getDebugLoc();
251 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
252 it != CSI.end(); ++it) {
253 // Add the callee-saved register as live-in. It's killed at the spill.
254 MBB.addLiveIn(it->getReg());
256 unsigned Reg = it->getReg();
257 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
258 TII.storeRegToStackSlot(MBB, MI, Reg, true,
259 it->getFrameIdx(), RC, TRI);
260 if (emitFrameMoves) {
261 MCSymbol *SaveLabel = MF->getContext().CreateTempSymbol();
262 BuildMI(MBB, MI, DL, TII.get(XCore::PROLOG_LABEL)).addSym(SaveLabel);
263 XFI->getSpillLabels().push_back(std::make_pair(SaveLabel, *it));
269 bool XCoreFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
270 MachineBasicBlock::iterator MI,
271 const std::vector<CalleeSavedInfo> &CSI,
272 const TargetRegisterInfo *TRI) const{
273 MachineFunction *MF = MBB.getParent();
274 const TargetInstrInfo &TII = *MF->getTarget().getInstrInfo();
276 bool AtStart = MI == MBB.begin();
277 MachineBasicBlock::iterator BeforeI = MI;
280 for (std::vector<CalleeSavedInfo>::const_iterator it = CSI.begin();
281 it != CSI.end(); ++it) {
282 unsigned Reg = it->getReg();
283 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
284 TII.loadRegFromStackSlot(MBB, MI, it->getReg(), it->getFrameIdx(),
286 assert(MI != MBB.begin() &&
287 "loadRegFromStackSlot didn't insert any code!");
288 // Insert in reverse order. loadRegFromStackSlot can insert multiple
300 // This function eliminates ADJCALLSTACKDOWN,
301 // ADJCALLSTACKUP pseudo instructions
302 void XCoreFrameLowering::
303 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
304 MachineBasicBlock::iterator I) const {
305 const XCoreInstrInfo &TII =
306 *static_cast<const XCoreInstrInfo*>(MF.getTarget().getInstrInfo());
307 if (!hasReservedCallFrame(MF)) {
308 // Turn the adjcallstackdown instruction into 'extsp <amt>' and the
309 // adjcallstackup instruction into 'ldaw sp, sp[<amt>]'
310 MachineInstr *Old = I;
311 uint64_t Amount = Old->getOperand(0).getImm();
313 // We need to keep the stack aligned properly. To do this, we round the
314 // amount of space needed for the outgoing arguments up to the next
315 // alignment boundary.
316 unsigned Align = getStackAlignment();
317 Amount = (Amount+Align-1)/Align*Align;
319 assert(Amount%4 == 0);
322 bool isU6 = isImmU6(Amount);
323 if (!isU6 && !isImmU16(Amount)) {
324 // FIX could emit multiple instructions in this case.
326 errs() << "eliminateCallFramePseudoInstr size too big: "
333 if (Old->getOpcode() == XCore::ADJCALLSTACKDOWN) {
334 int Opcode = isU6 ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
335 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode))
338 assert(Old->getOpcode() == XCore::ADJCALLSTACKUP);
339 int Opcode = isU6 ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
340 New=BuildMI(MF, Old->getDebugLoc(), TII.get(Opcode), XCore::SP)
344 // Replace the pseudo instruction with a new instruction...
353 XCoreFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
354 RegScavenger *RS) const {
355 MachineFrameInfo *MFI = MF.getFrameInfo();
356 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
357 bool LRUsed = MF.getRegInfo().isPhysRegUsed(XCore::LR);
358 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
359 XCoreFunctionInfo *XFI = MF.getInfo<XCoreFunctionInfo>();
361 MF.getRegInfo().setPhysRegUnused(XCore::LR);
363 bool isVarArg = MF.getFunction()->isVarArg();
366 // A fixed offset of 0 allows us to save / restore LR using entsp / retsp.
367 FrameIdx = MFI->CreateFixedObject(RC->getSize(), 0, true);
369 FrameIdx = MFI->CreateStackObject(RC->getSize(), RC->getAlignment(),
372 XFI->setUsesLR(FrameIdx);
373 XFI->setLRSpillSlot(FrameIdx);
375 if (RegInfo->requiresRegisterScavenging(MF)) {
376 // Reserve a slot close to SP or frame pointer.
377 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
382 // A callee save register is used to hold the FP.
383 // This needs saving / restoring in the epilogue / prologue.
384 XFI->setFPSpillSlot(MFI->CreateStackObject(RC->getSize(),